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/TwlSDK-5.4/include/nitro/gx/
Dgx_load.h39 void GX_LoadBGPltt(const void *pSrc, u32 offset, u32 szByte);
40 void GX_LoadOBJPltt(const void *pSrc, u32 offset, u32 szByte);
41 void GX_LoadOAM(const void *pSrc, u32 offset, u32 szByte);
42 void GX_LoadOBJ(const void *pSrc, u32 offset, u32 szByte);
44 void GX_LoadBG0Scr(const void *pSrc, u32 offset, u32 szByte);
45 void GX_LoadBG1Scr(const void *pSrc, u32 offset, u32 szByte);
46 void GX_LoadBG2Scr(const void *pSrc, u32 offset, u32 szByte);
47 void GX_LoadBG3Scr(const void *pSrc, u32 offset, u32 szByte);
49 void GX_LoadBG0Char(const void *pSrc, u32 offset, u32 szByte);
50 void GX_LoadBG1Char(const void *pSrc, u32 offset, u32 szByte);
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/TwlSDK-5.4/include/twl/ssp/ARM9/
Djpegenc.h46 u32 SSP_GetJpegEncoderBufferSize(u32 width, u32 height, u32 sampling, u32 option);
72 u32 SSP_StartJpegEncoder(const void* src, u8 *dst, u32 limit, u8 *wrk,
73 u32 width, u32 height,
74 u32 quality, u32 sampling, u32 option);
101 static inline u32 SSP_StartJpegEncoderEx(const void* src, u8 *dst, u32 limit, u8 *wrk, in SSP_StartJpegEncoderEx()
102 u32 width, u32 height, in SSP_StartJpegEncoderEx()
103 u32 quality, u32 sampling, u32 option, BOOL sign) in SSP_StartJpegEncoderEx()
105 u32 result; in SSP_StartJpegEncoderEx()
138 u32 width, u32 height, u32 sampling, u32 option);
164 u32 SSP_StartJpegEncoderWithEncodeData(u8 *dst, u32 limit, u8 *wrk,
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/TwlSDK-5.4/build/libraries/card/common/include/
Dcard_command.h39 #define CARD_BACKUP_CAPS_AVAILABLE (u32)(CARD_BACKUP_CAPS_READ - 1)
40 #define CARD_BACKUP_CAPS_READ (u32)(1 << CARD_REQ_READ_BACKUP)
41 #define CARD_BACKUP_CAPS_WRITE (u32)(1 << CARD_REQ_WRITE_BACKUP)
42 #define CARD_BACKUP_CAPS_PROGRAM (u32)(1 << CARD_REQ_PROGRAM_BACKUP)
43 #define CARD_BACKUP_CAPS_VERIFY (u32)(1 << CARD_REQ_VERIFY_BACKUP)
44 #define CARD_BACKUP_CAPS_ERASE_PAGE (u32)(1 << CARD_REQ_ERASE_PAGE_BACKUP)
45 #define CARD_BACKUP_CAPS_ERASE_SECTOR (u32)(1 << CARD_REQ_ERASE_SECTOR_BACKUP)
46 #define CARD_BACKUP_CAPS_ERASE_CHIP (u32)(1 << CARD_REQ_ERASE_CHIP_BACKUP)
47 #define CARD_BACKUP_CAPS_READ_STATUS (u32)(1 << CARD_REQ_READ_STATUS)
48 #define CARD_BACKUP_CAPS_WRITE_STATUS (u32)(1 << CARD_REQ_WRITE_STATUS)
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/TwlSDK-5.4/build/libraries/os/common/include/
Dmi_dma.h41 u32 b32;
52 void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
53 void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
54 void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
55 void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
58 static inline void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl) in MIi_DmaSetParams()
61 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams()
68 static inline void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl) in MIi_DmaSetParams_wait()
71 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait()
78 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParams_wait()
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/TwlSDK-5.4/build/libraries/init/common/include/
Dmi_dma.h41 u32 b32;
52 void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
53 void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
54 void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
55 void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
58 static inline void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl) in MIi_DmaSetParams()
61 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams()
68 static inline void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl) in MIi_DmaSetParams_wait()
71 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait()
78 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParams_wait()
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/TwlSDK-5.4/include/twl/mi/common/
Ddma.h177 u32 intervalTimer;
178 u32 prescaler;
179 u32 blockWord;
180 u32 wordCount;
188 typedef u32 MINDmaDevice;
299 void MI_NDmaFill (u32 ndmaNo,
300 void *dest, u32 data, u32 size );
301 void MI_NDmaFill_SetUp (u32 ndmaNo,
302 void *dest, u32 data, u32 size );
303 void MI_NDmaCopy (u32 ndmaNo,
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/TwlSDK-5.4/build/libraries/gx/ARM9/src/
Dg3imm.c44 reg_G3_MTX_LOAD_4x4 = (u32)m->_00; in G3_LoadMtx44()
45 reg_G3_MTX_LOAD_4x4 = (u32)m->_01; in G3_LoadMtx44()
46 reg_G3_MTX_LOAD_4x4 = (u32)m->_02; in G3_LoadMtx44()
47 reg_G3_MTX_LOAD_4x4 = (u32)m->_03; in G3_LoadMtx44()
49 reg_G3_MTX_LOAD_4x4 = (u32)m->_10; in G3_LoadMtx44()
50 reg_G3_MTX_LOAD_4x4 = (u32)m->_11; in G3_LoadMtx44()
51 reg_G3_MTX_LOAD_4x4 = (u32)m->_12; in G3_LoadMtx44()
52 reg_G3_MTX_LOAD_4x4 = (u32)m->_13; in G3_LoadMtx44()
54 reg_G3_MTX_LOAD_4x4 = (u32)m->_20; in G3_LoadMtx44()
55 reg_G3_MTX_LOAD_4x4 = (u32)m->_21; in G3_LoadMtx44()
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/TwlSDK-5.4/include/nitro/mi/
Dmemory.h31 void MIi_CpuClear16(u16 data, void *destp, u32 size);
32 void MIi_CpuCopy16(const void *srcp, void *destp, u32 size);
33 void MIi_CpuSend16(const void *srcp, volatile void *destp, u32 size);
34 void MIi_CpuRecv16(volatile const void *srcp, void *destp, u32 size);
35 void MIi_CpuPipe16(volatile const void *srcp, volatile void *destp, u32 size);
36 void MIi_CpuMove16(const void *src, void *dest, u32 size);
37 void* MIi_CpuFind16(const void *src, u16 data, u32 size);
38 int MIi_CpuComp16(const void *mem1, const void *mem2, u32 size);
40 void MIi_CpuClear32(u32 data, void *destp, u32 size);
41 void MIi_CpuCopy32(const void *srcp, void *destp, u32 size);
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Ddma.h61 # define MIi_DMA_TIMING_ANY (u32)(~0) // for internal use (MIi_CardDmaCopy32)
227 void MIi_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size, BOOL dmaEnable);
228 static inline void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size) in MI_DmaFill32()
232 static inline void MI_DmaFill32_SetUp(u32 dmaNo, void *dest, u32 data, u32 size) in MI_DmaFill32_SetUp()
250 void MIi_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size, BOOL dmaEnable);
251 static inline void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size) in MI_DmaCopy32()
255 static inline void MI_DmaCopy32_SetUp(u32 dmaNo, const void *src, void *dest, u32 size) in MI_DmaCopy32_SetUp()
272 static inline void MI_DmaClear32(u32 dmaNo, void *dest, u32 size) in MI_DmaClear32()
276 static inline void MI_DmaClear32_SetUp(u32 dmaNo, void *dest, u32 size) in MI_DmaClear32_SetUp()
294 void MIi_DmaSend32(u32 dmaNo, const void *src, volatile void *dest, u32 size, BOOL dmaEnable);
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/TwlSDK-5.4/build/libraries/gx/ARM9/include/
Dgxstate.h60 void GX_RegionCheck_BG_(u32 first, u32 last);
61 void GX_RegionCheck_OBJ_(u32 first, u32 last);
62 void GX_RegionCheck_SubBG_(u32 first, u32 last);
63 void GX_RegionCheck_SubOBJ_(u32 first, u32 last);
64 void GX_RegionCheck_Tex_(GXVRamTex tex, u32 first, u32 last);
65 void GX_RegionCheck_TexPltt_(GXVRamTexPltt texPltt, u32 first, u32 last);
74 static inline void GX_RegionCheck_BG(u32 first, u32 last) in GX_RegionCheck_BG()
79 static inline void GX_RegionCheck_OBJ(u32 first, u32 last) in GX_RegionCheck_OBJ()
84 static inline void GX_RegionCheck_SubBG(u32 first, u32 last) in GX_RegionCheck_SubBG()
89 static inline void GX_RegionCheck_SubOBJ(u32 first, u32 last) in GX_RegionCheck_SubOBJ()
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/TwlSDK-5.4/include/nitro/os/common/
Devent.h70 u32 OS_WaitEvent(OSEvent* event, u32 pattern, OSEventMode mode );
87 u32 OS_WaitEventEx(OSEvent* event, u32 pattern, OSEventMode mode, u32 clearBit );
91 static inline u32 OS_WaitEvent_And( OSEvent* event, u32 pattern ) in OS_WaitEvent_And()
95 static inline u32 OS_WaitEvent_Or(OSEvent* event, u32 pattern ) in OS_WaitEvent_Or()
99 static inline u32 OS_WaitEventEx_And( OSEvent* event, u32 pattern, u32 clearBit ) in OS_WaitEventEx_And()
103 static inline u32 OS_WaitEventEx_Or(OSEvent* event, u32 pattern, u32 clearBit ) in OS_WaitEventEx_Or()
119 void OS_SignalEvent(OSEvent* event, u32 setPattern);
131 void OS_ClearEvent(OSEvent* event, u32 clearBit);
158 u32 OS_PollEvent(OSEvent* event, u32 pattern, OSEventMode mode );
175 u32 OS_PollEventEx(OSEvent* event, u32 pattern, OSEventMode mode, u32 clearBit );
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/TwlSDK-5.4/build/libraries/stubs/istd/common/src/
Dstubs_istd.c40 int _ISTDbgLib_RegistOverlayInfo( OVERLAYPROC, u32, u32, u32, u32);
41 int _ISTDbgLib_UnregistOverlayInfo( OVERLAYPROC, u32, u32 );
44 BOOL _ISTDbgLib_RegistOverlayInfoByAddr(ISTDOVERLAYPROC, u32, u32, u32, u32);
45 BOOL _ISTDbgLib_UnregistOverlayInfoByAddr(ISTDOVERLAYPROC, u32, u32);
87 SDK_WEAK_SYMBOL int _ISTDbgLib_RegistOverlayInfo( OVERLAYPROC, u32, u32, u32, u32) in _ISTDbgLib_RegistOverlayInfo() argument
92 SDK_WEAK_SYMBOL int _ISTDbgLib_UnregistOverlayInfo( OVERLAYPROC, u32, u32) in _ISTDbgLib_UnregistOverlayInfo() argument
97 SDK_WEAK_SYMBOL BOOL _ISTDbgLib_RegistOverlayInfoByAddr(ISTDOVERLAYPROC, u32, u32, u32, u32) in _ISTDbgLib_RegistOverlayInfoByAddr() argument
102 SDK_WEAK_SYMBOL BOOL _ISTDbgLib_UnregistOverlayInfoByAddr(ISTDOVERLAYPROC, u32, u32) in _ISTDbgLib_UnregistOverlayInfoByAddr() argument
/TwlSDK-5.4/include/nitro/rtc/common/
Dtype.h61 u32 year:8; // Year ( 00 - 99 )
62 u32 month:5; // Month ( 01 - 12 )
63 u32 dummy0:3;
64 …u32 day:6; // Day ( 01 - 31 ) Month / Upper limit will change with leap ye…
65 u32 dummy1:2;
66 u32 week:3; // Day of week ( 00 - 06 )
67 u32 dummy2:5;
75 u32 hour:6; // Hour ( 00 - 23 or 00 - 11 )
76 u32 afternoon:1; // P.M. flag in the case of 12-hour notation
77 u32 dummy0:1;
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/TwlSDK-5.4/include/nitro/hw/ARM9/
Dioreg_G3.h270 (u32)( \
271 ((u32)(m) << REG_G3_MTX_MODE_M_SHIFT))
289 (u32)( \
290 ((u32)(s) << REG_G3_MTX_POP_S_SHIFT) | \
291 ((u32)(int) << REG_G3_MTX_POP_INT_SHIFT))
303 (u32)( \
304 ((u32)(index) << REG_G3_MTX_STORE_INDEX_SHIFT))
316 (u32)( \
317 ((u32)(index) << REG_G3_MTX_RESTORE_INDEX_SHIFT))
339 (u32)( \
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Dioreg_G3X.h867 ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \
868 ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \
869 ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \
870 ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \
871 ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \
872 ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \
873 ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \
874 ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \
875 ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \
876 ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \
[all …]
Dioreg_MI.h186 (u32)( \
187 ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT))
199 (u32)( \
200 ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT))
240 (u32)( \
241 ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \
242 ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \
243 ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \
244 ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \
245 ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \
[all …]
/TwlSDK-5.4/include/twl/hw/ARM9/
Dioreg_G3.h270 (u32)( \
271 ((u32)(m) << REG_G3_MTX_MODE_M_SHIFT))
289 (u32)( \
290 ((u32)(s) << REG_G3_MTX_POP_S_SHIFT) | \
291 ((u32)(int) << REG_G3_MTX_POP_INT_SHIFT))
303 (u32)( \
304 ((u32)(index) << REG_G3_MTX_STORE_INDEX_SHIFT))
316 (u32)( \
317 ((u32)(index) << REG_G3_MTX_RESTORE_INDEX_SHIFT))
339 (u32)( \
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Dioreg_G3X.h867 ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \
868 ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \
869 ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \
870 ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \
871 ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \
872 ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \
873 ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \
874 ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \
875 ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \
876 ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \
[all …]
Dioreg_MI.h666 (u32)( \
667 ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT))
679 (u32)( \
680 ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT))
720 (u32)( \
721 ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \
722 ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \
723 ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \
724 ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \
725 ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \
[all …]
Dioreg_OS.h121 ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT))
142 ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \
143 ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \
144 ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT))
157 ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT))
182 ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \
183 ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \
184 ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \
185 ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT))
198 ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT))
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/TwlSDK-5.4/include/nitro/fs/
Dromfat.h90 typedef FSResult (*FS_ARCHIVE_READ_FUNC) (struct FSArchive *p, void *dst, u32 pos, u32 size);
91 typedef FSResult (*FS_ARCHIVE_WRITE_FUNC) (struct FSArchive *p, const void *src, u32 pos, u32 size);
95 u32 top;
96 u32 bottom;
102 u32 start;
110 u32 base; \
111 u32 fat; \
112 u32 fat_size; \
113 u32 fnt; \
114 u32 fnt_size; \
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/TwlSDK-5.4/include/nitro/snd/ARM9/
Dinterface.h48 void SND_StartSeq(int playerNo, const void *base, u32 offset, const struct SNDBankData *bank);
49 void SND_PrepareSeq(int playerNo, const void *base, u32 offset, const struct SNDBankData *bank);
68 void SND_SetTrackMute(int playerNo, u32 trackBitMask, BOOL flag);
69 void SND_SetTrackMuteEx(int playerNo, u32 trackBitMask, SNDSeqMute mute);
70 void SND_SetTrackVolume(int playerNo, u32 trackBitMask, int volume);
71 void SND_SetTrackPitch(int playerNo, u32 trackBitMask, int pitch);
72 void SND_SetTrackPan(int playerNo, u32 trackBitMask, int pan);
73 void SND_SetTrackPanRange(int playerNo, u32 trackBitMask, int panRange);
74 void SND_SetTrackModDepth(int playerNo, u32 trackBitMask, int depth);
75 void SND_SetTrackModSpeed(int playerNo, u32 trackBitMask, int speed);
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/TwlSDK-5.4/build/libraries/mi/common.TWL/src/
Dmi_ndma.c39 static void MIi_Wait(u32 ndmaNo);
42 static inline void MIi_SetSrc( u32 ndmaNo, u32 src ) in MIi_SetSrc()
46 static inline void MIi_SetDest( u32 ndmaNo, u32 dest ) in MIi_SetDest()
50 static inline void MIi_SetTotalWordCount( u32 ndmaNo, u32 size ) in MIi_SetTotalWordCount()
54 static inline void MIi_SetWordCount( u32 ndmaNo, u32 size ) in MIi_SetWordCount()
58 static inline void MIi_SetInterval( u32 ndmaNo, u32 intervalTimer, u32 prescaler ) in MIi_SetInterval()
66 static inline void MIi_SetFillData( u32 ndmaNo, u32 data ) in MIi_SetFillData()
70 static inline void MIi_SetControl( u32 ndmaNo, u32 contData ) in MIi_SetControl()
76 static u32 MIi_GetControlData( MIiNDmaType ndmaType ) in MIi_GetControlData()
78 u32 contData; in MIi_GetControlData()
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/TwlSDK-5.4/include/nitro/ctrdg/ARM9/
Dctrdg_sram.h63 extern void CTRDG_ReadAgbSram(u32 src, void *dst, u32 size);
64 extern void CTRDG_ReadAgbSramAsync(u32 src, void *dst, u32 size, CTRDG_TASK_FUNC callback);
86 extern void CTRDG_WriteAgbSram(u32 dst, const void *src, u32 size);
87 extern void CTRDG_WriteAgbSramAsync(u32 dst, const void *src, u32 size, CTRDG_TASK_FUNC callback);
113 extern u32 CTRDG_VerifyAgbSram(u32 tgt, const void *src, u32 size);
114 extern void CTRDG_VerifyAgbSramAsync(u32 tgt, const void *src, u32 size, CTRDG_TASK_FUNC callback);
140 extern u32 CTRDG_WriteAndVerifyAgbSram(u32 dst, const void *src, u32 size);
141 extern void CTRDG_WriteAndVerifyAgbSramAsync(u32 dst, const void *src, u32 size,
/TwlSDK-5.4/build/libraries/mi/common/src/
Dmi_dma.c26 void MIi_DmaSetParameters(u32 dmaNo, u32 src, u32 dest, u32 ctrl, u32 mode) in MIi_DmaSetParameters()
40 MIiDmaClearSrc *srcp = (MIiDmaClearSrc *) ((u32)MIi_DMA_CLEAR_DATA_BUF + dmaNo * 4); in MIi_DmaSetParameters()
42 src = (u32)srcp; in MIi_DmaSetParameters()
46 MIiDmaClearSrc *srcp = (MIiDmaClearSrc *) ((u32)MIi_DMA_CLEAR_DATA_BUF + dmaNo * 4); in MIi_DmaSetParameters()
48 src = (u32)srcp; in MIi_DmaSetParameters()
59 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParameters()
62 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParameters()
86 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParameters()
89 u32 dummy = reg_MI_DMA0SAD; in MIi_DmaSetParameters()
95 void MIi_DmaSetParameters(u32 dmaNo, u32 src, u32 dest, u32 ctrl, u32 mode) in MIi_DmaSetParameters()
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