Lines Matching refs:u32
666 (u32)( \
667 ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT))
679 (u32)( \
680 ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT))
720 (u32)( \
721 ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \
722 ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \
723 ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \
724 ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \
725 ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \
726 ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \
727 ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \
728 ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT))
740 (u32)( \
741 ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT))
753 (u32)( \
754 ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT))
794 (u32)( \
795 ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \
796 ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \
797 ((u32)(mode) << REG_MI_DMA1CNT_MODE_SHIFT) | \
798 ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \
799 ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \
800 ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \
801 ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \
802 ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT))
814 (u32)( \
815 ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT))
827 (u32)( \
828 ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT))
868 (u32)( \
869 ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \
870 ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \
871 ((u32)(mode) << REG_MI_DMA2CNT_MODE_SHIFT) | \
872 ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \
873 ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \
874 ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \
875 ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \
876 ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT))
888 (u32)( \
889 ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT))
901 (u32)( \
902 ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT))
942 (u32)( \
943 ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \
944 ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \
945 ((u32)(mode) << REG_MI_DMA3CNT_MODE_SHIFT) | \
946 ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \
947 ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \
948 ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \
949 ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \
950 ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT))
974 (u32)( \
975 ((u32)(arbiter) << REG_MI_NDMAGCNT_ARBITER_SHIFT) | \
976 ((u32)(cpucycle) << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT))
988 (u32)( \
989 ((u32)(dmasrc) << REG_MI_NDMA0SAD_DMASRC_SHIFT))
1001 (u32)( \
1002 ((u32)(dmadest) << REG_MI_NDAM0DAD_DMADEST_SHIFT))
1014 (u32)( \
1015 ((u32)(totalcnt) << REG_MI_NDMA0TCNT_TOTALCNT_SHIFT))
1027 (u32)( \
1028 ((u32)(wordcnt) << REG_MI_NDMA0WCNT_WORDCNT_SHIFT))
1044 (u32)( \
1045 ((u32)(ps) << REG_MI_NDMA0BCNT_PS_SHIFT) | \
1046 ((u32)(icnt) << REG_MI_NDMA0BCNT_ICNT_SHIFT))
1058 (u32)( \
1059 ((u32)(fdata) << REG_MI_NDMA0FDATA_FDATA_SHIFT))
1107 (u32)( \
1108 ((u32)(e) << REG_MI_NDMA0CNT_E_SHIFT) | \
1109 ((u32)(i) << REG_MI_NDMA0CNT_I_SHIFT) | \
1110 ((u32)(cm) << REG_MI_NDMA0CNT_CM_SHIFT) | \
1111 ((u32)(im) << REG_MI_NDMA0CNT_IM_SHIFT) | \
1112 ((u32)(mode) << REG_MI_NDMA0CNT_MODE_SHIFT) | \
1113 ((u32)(wordcnt) << REG_MI_NDMA0CNT_WORDCNT_SHIFT) | \
1114 ((u32)(srl) << REG_MI_NDMA0CNT_SRL_SHIFT) | \
1115 ((u32)(sar) << REG_MI_NDMA0CNT_SAR_SHIFT) | \
1116 ((u32)(drl) << REG_MI_NDMA0CNT_DRL_SHIFT) | \
1117 ((u32)(dar) << REG_MI_NDMA0CNT_DAR_SHIFT))
1129 (u32)( \
1130 ((u32)(dmasrc) << REG_MI_NDMA1SAD_DMASRC_SHIFT))
1142 (u32)( \
1143 ((u32)(dmadest) << REG_MI_NDAM1DAD_DMADEST_SHIFT))
1155 (u32)( \
1156 ((u32)(totalcnt) << REG_MI_NDMA1TCNT_TOTALCNT_SHIFT))
1168 (u32)( \
1169 ((u32)(wordcnt) << REG_MI_NDMA1WCNT_WORDCNT_SHIFT))
1185 (u32)( \
1186 ((u32)(ps) << REG_MI_NDMA1BCNT_PS_SHIFT) | \
1187 ((u32)(icnt) << REG_MI_NDMA1BCNT_ICNT_SHIFT))
1199 (u32)( \
1200 ((u32)(fdata) << REG_MI_NDMA1FDATA_FDATA_SHIFT))
1248 (u32)( \
1249 ((u32)(e) << REG_MI_NDMA1CNT_E_SHIFT) | \
1250 ((u32)(i) << REG_MI_NDMA1CNT_I_SHIFT) | \
1251 ((u32)(cm) << REG_MI_NDMA1CNT_CM_SHIFT) | \
1252 ((u32)(im) << REG_MI_NDMA1CNT_IM_SHIFT) | \
1253 ((u32)(mode) << REG_MI_NDMA1CNT_MODE_SHIFT) | \
1254 ((u32)(wordcnt) << REG_MI_NDMA1CNT_WORDCNT_SHIFT) | \
1255 ((u32)(srl) << REG_MI_NDMA1CNT_SRL_SHIFT) | \
1256 ((u32)(sar) << REG_MI_NDMA1CNT_SAR_SHIFT) | \
1257 ((u32)(drl) << REG_MI_NDMA1CNT_DRL_SHIFT) | \
1258 ((u32)(dar) << REG_MI_NDMA1CNT_DAR_SHIFT))
1270 (u32)( \
1271 ((u32)(dmasrc) << REG_MI_NDMA2SAD_DMASRC_SHIFT))
1283 (u32)( \
1284 ((u32)(dmadest) << REG_MI_NDAM2DAD_DMADEST_SHIFT))
1296 (u32)( \
1297 ((u32)(totalcnt) << REG_MI_NDMA2TCNT_TOTALCNT_SHIFT))
1309 (u32)( \
1310 ((u32)(wordcnt) << REG_MI_NDMA2WCNT_WORDCNT_SHIFT))
1326 (u32)( \
1327 ((u32)(ps) << REG_MI_NDMA2BCNT_PS_SHIFT) | \
1328 ((u32)(icnt) << REG_MI_NDMA2BCNT_ICNT_SHIFT))
1340 (u32)( \
1341 ((u32)(fdata) << REG_MI_NDMA2FDATA_FDATA_SHIFT))
1389 (u32)( \
1390 ((u32)(e) << REG_MI_NDMA2CNT_E_SHIFT) | \
1391 ((u32)(i) << REG_MI_NDMA2CNT_I_SHIFT) | \
1392 ((u32)(cm) << REG_MI_NDMA2CNT_CM_SHIFT) | \
1393 ((u32)(im) << REG_MI_NDMA2CNT_IM_SHIFT) | \
1394 ((u32)(mode) << REG_MI_NDMA2CNT_MODE_SHIFT) | \
1395 ((u32)(wordcnt) << REG_MI_NDMA2CNT_WORDCNT_SHIFT) | \
1396 ((u32)(srl) << REG_MI_NDMA2CNT_SRL_SHIFT) | \
1397 ((u32)(sar) << REG_MI_NDMA2CNT_SAR_SHIFT) | \
1398 ((u32)(drl) << REG_MI_NDMA2CNT_DRL_SHIFT) | \
1399 ((u32)(dar) << REG_MI_NDMA2CNT_DAR_SHIFT))
1411 (u32)( \
1412 ((u32)(dmasrc) << REG_MI_NDMA3SAD_DMASRC_SHIFT))
1424 (u32)( \
1425 ((u32)(dmadest) << REG_MI_NDAM3DAD_DMADEST_SHIFT))
1437 (u32)( \
1438 ((u32)(totalcnt) << REG_MI_NDMA3TCNT_TOTALCNT_SHIFT))
1450 (u32)( \
1451 ((u32)(wordcnt) << REG_MI_NDMA3WCNT_WORDCNT_SHIFT))
1467 (u32)( \
1468 ((u32)(ps) << REG_MI_NDMA3BCNT_PS_SHIFT) | \
1469 ((u32)(icnt) << REG_MI_NDMA3BCNT_ICNT_SHIFT))
1481 (u32)( \
1482 ((u32)(fdata) << REG_MI_NDMA3FDATA_FDATA_SHIFT))
1530 (u32)( \
1531 ((u32)(e) << REG_MI_NDMA3CNT_E_SHIFT) | \
1532 ((u32)(i) << REG_MI_NDMA3CNT_I_SHIFT) | \
1533 ((u32)(cm) << REG_MI_NDMA3CNT_CM_SHIFT) | \
1534 ((u32)(im) << REG_MI_NDMA3CNT_IM_SHIFT) | \
1535 ((u32)(mode) << REG_MI_NDMA3CNT_MODE_SHIFT) | \
1536 ((u32)(wordcnt) << REG_MI_NDMA3CNT_WORDCNT_SHIFT) | \
1537 ((u32)(srl) << REG_MI_NDMA3CNT_SRL_SHIFT) | \
1538 ((u32)(sar) << REG_MI_NDMA3CNT_SAR_SHIFT) | \
1539 ((u32)(drl) << REG_MI_NDMA3CNT_DRL_SHIFT) | \
1540 ((u32)(dar) << REG_MI_NDMA3CNT_DAR_SHIFT))
1573 ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \
1574 ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \
1575 ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \
1576 ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \
1577 ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \
1578 ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT))
1591 ((u32)(data) << REG_MI_MCD0_DATA_SHIFT))
1649 (u32)( \
1650 ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \
1651 ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \
1652 ((u32)(resb) << REG_MI_MCCNT1_RESB_SHIFT) | \
1653 ((u32)(rtm) << REG_MI_MCCNT1_RTM_SHIFT) | \
1654 ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \
1655 ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \
1656 ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \
1657 ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \
1658 ((u32)(scr) << REG_MI_MCCNT1_SCR_SHIFT) | \
1659 ((u32)(se) << REG_MI_MCCNT1_SE_SHIFT) | \
1660 ((u32)(ds) << REG_MI_MCCNT1_DS_SHIFT) | \
1661 ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT))
1685 (u32)( \
1686 ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \
1687 ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \
1688 ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \
1689 ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT))
1713 (u32)( \
1714 ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \
1715 ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \
1716 ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \
1717 ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT))
1750 ((u32)(e) << REG_MI_MCCNT0_A_E_SHIFT) | \
1751 ((u32)(i) << REG_MI_MCCNT0_A_I_SHIFT) | \
1752 ((u32)(sel) << REG_MI_MCCNT0_A_SEL_SHIFT) | \
1753 ((u32)(busy) << REG_MI_MCCNT0_A_BUSY_SHIFT) | \
1754 ((u32)(mode) << REG_MI_MCCNT0_A_MODE_SHIFT) | \
1755 ((u32)(baudrate) << REG_MI_MCCNT0_A_BAUDRATE_SHIFT))
1768 ((u32)(data) << REG_MI_MCD0_A_DATA_SHIFT))
1780 (u32)( \
1781 ((u32)(data) << REG_MI_MCD1_A_DATA_SHIFT))
1841 (u32)( \
1842 ((u32)(start) << REG_MI_MCCNT1_A_START_SHIFT) | \
1843 ((u32)(wr) << REG_MI_MCCNT1_A_WR_SHIFT) | \
1844 ((u32)(resb) << REG_MI_MCCNT1_A_RESB_SHIFT) | \
1845 ((u32)(trm) << REG_MI_MCCNT1_A_TRM_SHIFT) | \
1846 ((u32)(ct) << REG_MI_MCCNT1_A_CT_SHIFT) | \
1847 ((u32)(pc) << REG_MI_MCCNT1_A_PC_SHIFT) | \
1848 ((u32)(rdy) << REG_MI_MCCNT1_A_RDY_SHIFT) | \
1849 ((u32)(cs) << REG_MI_MCCNT1_A_CS_SHIFT) | \
1850 ((u32)(l2) << REG_MI_MCCNT1_A_L2_SHIFT) | \
1851 ((u32)(scr) << REG_MI_MCCNT1_A_SCR_SHIFT) | \
1852 ((u32)(se) << REG_MI_MCCNT1_A_SE_SHIFT) | \
1853 ((u32)(ds) << REG_MI_MCCNT1_A_DS_SHIFT) | \
1854 ((u32)(l1) << REG_MI_MCCNT1_A_L1_SHIFT))
1878 (u32)( \
1879 ((u32)(cmd3) << REG_MI_MCCMD0_A_CMD3_SHIFT) | \
1880 ((u32)(cmd2) << REG_MI_MCCMD0_A_CMD2_SHIFT) | \
1881 ((u32)(cmd1) << REG_MI_MCCMD0_A_CMD1_SHIFT) | \
1882 ((u32)(cmd0) << REG_MI_MCCMD0_A_CMD0_SHIFT))
1906 (u32)( \
1907 ((u32)(cmd7) << REG_MI_MCCMD1_A_CMD7_SHIFT) | \
1908 ((u32)(cmd6) << REG_MI_MCCMD1_A_CMD6_SHIFT) | \
1909 ((u32)(cmd5) << REG_MI_MCCMD1_A_CMD5_SHIFT) | \
1910 ((u32)(cmd4) << REG_MI_MCCMD1_A_CMD4_SHIFT))
1922 (u32)( \
1923 ((u32)(scra) << REG_MI_MCSRC0_A_SCRA_SHIFT))
1935 (u32)( \
1936 ((u32)(scrb) << REG_MI_MCSRC1_A_SCRB_SHIFT))
1952 (u32)( \
1953 ((u32)(scrb) << REG_MI_MCSRC2_A_SCRB_SHIFT) | \
1954 ((u32)(scra) << REG_MI_MCSRC2_A_SCRA_SHIFT))
1987 ((u32)(e) << REG_MI_MCCNT0_B_E_SHIFT) | \
1988 ((u32)(i) << REG_MI_MCCNT0_B_I_SHIFT) | \
1989 ((u32)(sel) << REG_MI_MCCNT0_B_SEL_SHIFT) | \
1990 ((u32)(busy) << REG_MI_MCCNT0_B_BUSY_SHIFT) | \
1991 ((u32)(mode) << REG_MI_MCCNT0_B_MODE_SHIFT) | \
1992 ((u32)(baudrate) << REG_MI_MCCNT0_B_BAUDRATE_SHIFT))
2005 ((u32)(data) << REG_MI_MCD0_B_DATA_SHIFT))
2017 (u32)( \
2018 ((u32)(data) << REG_MI_MCD1_B_DATA_SHIFT))
2078 (u32)( \
2079 ((u32)(start) << REG_MI_MCCNT1_B_START_SHIFT) | \
2080 ((u32)(wr) << REG_MI_MCCNT1_B_WR_SHIFT) | \
2081 ((u32)(resb) << REG_MI_MCCNT1_B_RESB_SHIFT) | \
2082 ((u32)(trm) << REG_MI_MCCNT1_B_TRM_SHIFT) | \
2083 ((u32)(ct) << REG_MI_MCCNT1_B_CT_SHIFT) | \
2084 ((u32)(pc) << REG_MI_MCCNT1_B_PC_SHIFT) | \
2085 ((u32)(rdy) << REG_MI_MCCNT1_B_RDY_SHIFT) | \
2086 ((u32)(cs) << REG_MI_MCCNT1_B_CS_SHIFT) | \
2087 ((u32)(l2) << REG_MI_MCCNT1_B_L2_SHIFT) | \
2088 ((u32)(scr) << REG_MI_MCCNT1_B_SCR_SHIFT) | \
2089 ((u32)(se) << REG_MI_MCCNT1_B_SE_SHIFT) | \
2090 ((u32)(ds) << REG_MI_MCCNT1_B_DS_SHIFT) | \
2091 ((u32)(l1) << REG_MI_MCCNT1_B_L1_SHIFT))
2115 (u32)( \
2116 ((u32)(cmd3) << REG_MI_MCCMD0_B_CMD3_SHIFT) | \
2117 ((u32)(cmd2) << REG_MI_MCCMD0_B_CMD2_SHIFT) | \
2118 ((u32)(cmd1) << REG_MI_MCCMD0_B_CMD1_SHIFT) | \
2119 ((u32)(cmd0) << REG_MI_MCCMD0_B_CMD0_SHIFT))
2143 (u32)( \
2144 ((u32)(cmd7) << REG_MI_MCCMD1_B_CMD7_SHIFT) | \
2145 ((u32)(cmd6) << REG_MI_MCCMD1_B_CMD6_SHIFT) | \
2146 ((u32)(cmd5) << REG_MI_MCCMD1_B_CMD5_SHIFT) | \
2147 ((u32)(cmd4) << REG_MI_MCCMD1_B_CMD4_SHIFT))
2159 (u32)( \
2160 ((u32)(scra) << REG_MI_MCSRC0_B_SCRA_SHIFT))
2172 (u32)( \
2173 ((u32)(scrb) << REG_MI_MCSRC1_B_SCRB_SHIFT))
2189 (u32)( \
2190 ((u32)(scrb) << REG_MI_MCSRC2_B_SCRB_SHIFT) | \
2191 ((u32)(scra) << REG_MI_MCSRC2_B_SCRA_SHIFT))
2244 ((u32)(ep) << REG_MI_EXMEMCNT_EP_SHIFT) | \
2245 ((u32)(ifm) << REG_MI_EXMEMCNT_IFM_SHIFT) | \
2246 ((u32)(ce2) << REG_MI_EXMEMCNT_CE2_SHIFT) | \
2247 ((u32)(mpa) << REG_MI_EXMEMCNT_MPA_SHIFT) | \
2248 ((u32)(mp) << REG_MI_EXMEMCNT_MP_SHIFT) | \
2249 ((u32)(mpb) << REG_MI_EXMEMCNT_MPB_SHIFT) | \
2250 ((u32)(cp) << REG_MI_EXMEMCNT_CP_SHIFT) | \
2251 ((u32)(phi) << REG_MI_EXMEMCNT_PHI_SHIFT) | \
2252 ((u32)(rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT) | \
2253 ((u32)(rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT) | \
2254 ((u32)(ram) << REG_MI_EXMEMCNT_RAM_SHIFT))
2283 ((u32)(swp) << REG_MI_MC_SWP_SHIFT) | \
2284 ((u32)(sl2_mode) << REG_MI_MC_SL2_MODE_SHIFT) | \
2285 ((u32)(sl2_cdet) << REG_MI_MC_SL2_CDET_SHIFT) | \
2286 ((u32)(sl1_mode) << REG_MI_MC_SL1_MODE_SHIFT) | \
2287 ((u32)(sl1_cdet) << REG_MI_MC_SL1_CDET_SHIFT))
2343 (u32)( \
2344 ((u32)(wa3_e) << REG_MI_MBK1_WA3_E_SHIFT) | \
2345 ((u32)(wa3_of) << REG_MI_MBK1_WA3_OF_SHIFT) | \
2346 ((u32)(wa3_m) << REG_MI_MBK1_WA3_M_SHIFT) | \
2347 ((u32)(wa2_e) << REG_MI_MBK1_WA2_E_SHIFT) | \
2348 ((u32)(wa2_of) << REG_MI_MBK1_WA2_OF_SHIFT) | \
2349 ((u32)(wa2_m) << REG_MI_MBK1_WA2_M_SHIFT) | \
2350 ((u32)(wa1_e) << REG_MI_MBK1_WA1_E_SHIFT) | \
2351 ((u32)(wa1_of) << REG_MI_MBK1_WA1_OF_SHIFT) | \
2352 ((u32)(wa1_m) << REG_MI_MBK1_WA1_M_SHIFT) | \
2353 ((u32)(wa0_e) << REG_MI_MBK1_WA0_E_SHIFT) | \
2354 ((u32)(wa0_of) << REG_MI_MBK1_WA0_OF_SHIFT) | \
2355 ((u32)(wa0_m) << REG_MI_MBK1_WA0_M_SHIFT))
2376 ((u32)(e) << REG_MI_MBK_A0_E_SHIFT) | \
2377 ((u32)(of) << REG_MI_MBK_A0_OF_SHIFT) | \
2378 ((u32)(m) << REG_MI_MBK_A0_M_SHIFT))
2399 ((u32)(e) << REG_MI_MBK_A1_E_SHIFT) | \
2400 ((u32)(of) << REG_MI_MBK_A1_OF_SHIFT) | \
2401 ((u32)(m) << REG_MI_MBK_A1_M_SHIFT))
2422 ((u32)(e) << REG_MI_MBK_A2_E_SHIFT) | \
2423 ((u32)(of) << REG_MI_MBK_A2_OF_SHIFT) | \
2424 ((u32)(m) << REG_MI_MBK_A2_M_SHIFT))
2445 ((u32)(e) << REG_MI_MBK_A3_E_SHIFT) | \
2446 ((u32)(of) << REG_MI_MBK_A3_OF_SHIFT) | \
2447 ((u32)(m) << REG_MI_MBK_A3_M_SHIFT))
2503 (u32)( \
2504 ((u32)(wb3_e) << REG_MI_MBK2_WB3_E_SHIFT) | \
2505 ((u32)(wb3_of) << REG_MI_MBK2_WB3_OF_SHIFT) | \
2506 ((u32)(wb3_m) << REG_MI_MBK2_WB3_M_SHIFT) | \
2507 ((u32)(wb2_e) << REG_MI_MBK2_WB2_E_SHIFT) | \
2508 ((u32)(wb2_of) << REG_MI_MBK2_WB2_OF_SHIFT) | \
2509 ((u32)(wb2_m) << REG_MI_MBK2_WB2_M_SHIFT) | \
2510 ((u32)(wb1_e) << REG_MI_MBK2_WB1_E_SHIFT) | \
2511 ((u32)(wb1_of) << REG_MI_MBK2_WB1_OF_SHIFT) | \
2512 ((u32)(wb1_m) << REG_MI_MBK2_WB1_M_SHIFT) | \
2513 ((u32)(wb0_e) << REG_MI_MBK2_WB0_E_SHIFT) | \
2514 ((u32)(wb0_of) << REG_MI_MBK2_WB0_OF_SHIFT) | \
2515 ((u32)(wb0_m) << REG_MI_MBK2_WB0_M_SHIFT))
2536 ((u32)(e) << REG_MI_MBK_B0_E_SHIFT) | \
2537 ((u32)(of) << REG_MI_MBK_B0_OF_SHIFT) | \
2538 ((u32)(m) << REG_MI_MBK_B0_M_SHIFT))
2559 ((u32)(e) << REG_MI_MBK_B1_E_SHIFT) | \
2560 ((u32)(of) << REG_MI_MBK_B1_OF_SHIFT) | \
2561 ((u32)(m) << REG_MI_MBK_B1_M_SHIFT))
2582 ((u32)(e) << REG_MI_MBK_B2_E_SHIFT) | \
2583 ((u32)(of) << REG_MI_MBK_B2_OF_SHIFT) | \
2584 ((u32)(m) << REG_MI_MBK_B2_M_SHIFT))
2605 ((u32)(e) << REG_MI_MBK_B3_E_SHIFT) | \
2606 ((u32)(of) << REG_MI_MBK_B3_OF_SHIFT) | \
2607 ((u32)(m) << REG_MI_MBK_B3_M_SHIFT))
2663 (u32)( \
2664 ((u32)(wb7_e) << REG_MI_MBK3_WB7_E_SHIFT) | \
2665 ((u32)(wb7_of) << REG_MI_MBK3_WB7_OF_SHIFT) | \
2666 ((u32)(wb7_m) << REG_MI_MBK3_WB7_M_SHIFT) | \
2667 ((u32)(wb6_e) << REG_MI_MBK3_WB6_E_SHIFT) | \
2668 ((u32)(wb6_of) << REG_MI_MBK3_WB6_OF_SHIFT) | \
2669 ((u32)(wb6_m) << REG_MI_MBK3_WB6_M_SHIFT) | \
2670 ((u32)(wb5_e) << REG_MI_MBK3_WB5_E_SHIFT) | \
2671 ((u32)(wb5_of) << REG_MI_MBK3_WB5_OF_SHIFT) | \
2672 ((u32)(wb5_m) << REG_MI_MBK3_WB5_M_SHIFT) | \
2673 ((u32)(wb4_e) << REG_MI_MBK3_WB4_E_SHIFT) | \
2674 ((u32)(wb4_of) << REG_MI_MBK3_WB4_OF_SHIFT) | \
2675 ((u32)(wb4_m) << REG_MI_MBK3_WB4_M_SHIFT))
2696 ((u32)(e) << REG_MI_MBK_B4_E_SHIFT) | \
2697 ((u32)(of) << REG_MI_MBK_B4_OF_SHIFT) | \
2698 ((u32)(m) << REG_MI_MBK_B4_M_SHIFT))
2719 ((u32)(e) << REG_MI_MBK_B5_E_SHIFT) | \
2720 ((u32)(of) << REG_MI_MBK_B5_OF_SHIFT) | \
2721 ((u32)(m) << REG_MI_MBK_B5_M_SHIFT))
2742 ((u32)(e) << REG_MI_MBK_B6_E_SHIFT) | \
2743 ((u32)(of) << REG_MI_MBK_B6_OF_SHIFT) | \
2744 ((u32)(m) << REG_MI_MBK_B6_M_SHIFT))
2765 ((u32)(e) << REG_MI_MBK_B7_E_SHIFT) | \
2766 ((u32)(of) << REG_MI_MBK_B7_OF_SHIFT) | \
2767 ((u32)(m) << REG_MI_MBK_B7_M_SHIFT))
2823 (u32)( \
2824 ((u32)(wc3_e) << REG_MI_MBK4_WC3_E_SHIFT) | \
2825 ((u32)(wc3_of) << REG_MI_MBK4_WC3_OF_SHIFT) | \
2826 ((u32)(wc3_m) << REG_MI_MBK4_WC3_M_SHIFT) | \
2827 ((u32)(wc2_e) << REG_MI_MBK4_WC2_E_SHIFT) | \
2828 ((u32)(wc2_of) << REG_MI_MBK4_WC2_OF_SHIFT) | \
2829 ((u32)(wc2_m) << REG_MI_MBK4_WC2_M_SHIFT) | \
2830 ((u32)(wc1_e) << REG_MI_MBK4_WC1_E_SHIFT) | \
2831 ((u32)(wc1_of) << REG_MI_MBK4_WC1_OF_SHIFT) | \
2832 ((u32)(wc1_m) << REG_MI_MBK4_WC1_M_SHIFT) | \
2833 ((u32)(wc0_e) << REG_MI_MBK4_WC0_E_SHIFT) | \
2834 ((u32)(wc0_of) << REG_MI_MBK4_WC0_OF_SHIFT) | \
2835 ((u32)(wc0_m) << REG_MI_MBK4_WC0_M_SHIFT))
2856 ((u32)(e) << REG_MI_MBK_C0_E_SHIFT) | \
2857 ((u32)(of) << REG_MI_MBK_C0_OF_SHIFT) | \
2858 ((u32)(m) << REG_MI_MBK_C0_M_SHIFT))
2879 ((u32)(e) << REG_MI_MBK_C1_E_SHIFT) | \
2880 ((u32)(of) << REG_MI_MBK_C1_OF_SHIFT) | \
2881 ((u32)(m) << REG_MI_MBK_C1_M_SHIFT))
2902 ((u32)(e) << REG_MI_MBK_C2_E_SHIFT) | \
2903 ((u32)(of) << REG_MI_MBK_C2_OF_SHIFT) | \
2904 ((u32)(m) << REG_MI_MBK_C2_M_SHIFT))
2925 ((u32)(e) << REG_MI_MBK_C3_E_SHIFT) | \
2926 ((u32)(of) << REG_MI_MBK_C3_OF_SHIFT) | \
2927 ((u32)(m) << REG_MI_MBK_C3_M_SHIFT))
2983 (u32)( \
2984 ((u32)(wc7_e) << REG_MI_MBK5_WC7_E_SHIFT) | \
2985 ((u32)(wc7_of) << REG_MI_MBK5_WC7_OF_SHIFT) | \
2986 ((u32)(wc7_m) << REG_MI_MBK5_WC7_M_SHIFT) | \
2987 ((u32)(wc6_e) << REG_MI_MBK5_WC6_E_SHIFT) | \
2988 ((u32)(wc6_of) << REG_MI_MBK5_WC6_OF_SHIFT) | \
2989 ((u32)(wc6_m) << REG_MI_MBK5_WC6_M_SHIFT) | \
2990 ((u32)(wc5_e) << REG_MI_MBK5_WC5_E_SHIFT) | \
2991 ((u32)(wc5_of) << REG_MI_MBK5_WC5_OF_SHIFT) | \
2992 ((u32)(wc5_m) << REG_MI_MBK5_WC5_M_SHIFT) | \
2993 ((u32)(wc4_e) << REG_MI_MBK5_WC4_E_SHIFT) | \
2994 ((u32)(wc4_of) << REG_MI_MBK5_WC4_OF_SHIFT) | \
2995 ((u32)(wc4_m) << REG_MI_MBK5_WC4_M_SHIFT))
3016 ((u32)(e) << REG_MI_MBK_C4_E_SHIFT) | \
3017 ((u32)(of) << REG_MI_MBK_C4_OF_SHIFT) | \
3018 ((u32)(m) << REG_MI_MBK_C4_M_SHIFT))
3039 ((u32)(e) << REG_MI_MBK_C5_E_SHIFT) | \
3040 ((u32)(of) << REG_MI_MBK_C5_OF_SHIFT) | \
3041 ((u32)(m) << REG_MI_MBK_C5_M_SHIFT))
3062 ((u32)(e) << REG_MI_MBK_C6_E_SHIFT) | \
3063 ((u32)(of) << REG_MI_MBK_C6_OF_SHIFT) | \
3064 ((u32)(m) << REG_MI_MBK_C6_M_SHIFT))
3085 ((u32)(e) << REG_MI_MBK_C7_E_SHIFT) | \
3086 ((u32)(of) << REG_MI_MBK_C7_OF_SHIFT) | \
3087 ((u32)(m) << REG_MI_MBK_C7_M_SHIFT))
3107 (u32)( \
3108 ((u32)(wa_eaddr) << REG_MI_MBK6_WA_EADDR_SHIFT) | \
3109 ((u32)(wa_isize) << REG_MI_MBK6_WA_ISIZE_SHIFT) | \
3110 ((u32)(wa_saddr) << REG_MI_MBK6_WA_SADDR_SHIFT))
3130 (u32)( \
3131 ((u32)(wb_eaddr) << REG_MI_MBK7_WB_EADDR_SHIFT) | \
3132 ((u32)(wb_isize) << REG_MI_MBK7_WB_ISIZE_SHIFT) | \
3133 ((u32)(wb_saddr) << REG_MI_MBK7_WB_SADDR_SHIFT))
3153 (u32)( \
3154 ((u32)(wc_eaddr) << REG_MI_MBK8_WC_EADDR_SHIFT) | \
3155 ((u32)(wc_isize) << REG_MI_MBK8_WC_ISIZE_SHIFT) | \
3156 ((u32)(wc_saddr) << REG_MI_MBK8_WC_SADDR_SHIFT))
3176 (u32)( \
3177 ((u32)(wc_lockst) << REG_MI_MBK9_WC_LOCKST_SHIFT) | \
3178 ((u32)(wb_loclst) << REG_MI_MBK9_WB_LOCLST_SHIFT) | \
3179 ((u32)(wa_lockst) << REG_MI_MBK9_WA_LOCKST_SHIFT))
3204 ((u32)(a3) << REG_MI_MBK_A_LOCK_A3_SHIFT) | \
3205 ((u32)(a2) << REG_MI_MBK_A_LOCK_A2_SHIFT) | \
3206 ((u32)(a1) << REG_MI_MBK_A_LOCK_A1_SHIFT) | \
3207 ((u32)(a0) << REG_MI_MBK_A_LOCK_A0_SHIFT))
3248 ((u32)(b7) << REG_MI_MBK_B_LOCK_B7_SHIFT) | \
3249 ((u32)(b6) << REG_MI_MBK_B_LOCK_B6_SHIFT) | \
3250 ((u32)(b5) << REG_MI_MBK_B_LOCK_B5_SHIFT) | \
3251 ((u32)(b4) << REG_MI_MBK_B_LOCK_B4_SHIFT) | \
3252 ((u32)(b3) << REG_MI_MBK_B_LOCK_B3_SHIFT) | \
3253 ((u32)(b2) << REG_MI_MBK_B_LOCK_B2_SHIFT) | \
3254 ((u32)(b1) << REG_MI_MBK_B_LOCK_B1_SHIFT) | \
3255 ((u32)(b0) << REG_MI_MBK_B_LOCK_B0_SHIFT))
3296 ((u32)(c7) << REG_MI_MBK_C_LOCK_C7_SHIFT) | \
3297 ((u32)(c6) << REG_MI_MBK_C_LOCK_C6_SHIFT) | \
3298 ((u32)(c5) << REG_MI_MBK_C_LOCK_C5_SHIFT) | \
3299 ((u32)(c4) << REG_MI_MBK_C_LOCK_C4_SHIFT) | \
3300 ((u32)(c3) << REG_MI_MBK_C_LOCK_C3_SHIFT) | \
3301 ((u32)(c2) << REG_MI_MBK_C_LOCK_C2_SHIFT) | \
3302 ((u32)(c1) << REG_MI_MBK_C_LOCK_C1_SHIFT) | \
3303 ((u32)(c0) << REG_MI_MBK_C_LOCK_C0_SHIFT))