Lines Matching refs:u32

186     (u32)( \
187     ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT))
199     (u32)( \
200     ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT))
240     (u32)( \
241     ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \
242     ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \
243     ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \
244     ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \
245     ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \
246     ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \
247     ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \
248     ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT))
260     (u32)( \
261     ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT))
273     (u32)( \
274     ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT))
314     (u32)( \
315     ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \
316     ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \
317     ((u32)(mode) << REG_MI_DMA1CNT_MODE_SHIFT) | \
318     ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \
319     ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \
320     ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \
321     ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \
322     ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT))
334     (u32)( \
335     ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT))
347     (u32)( \
348     ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT))
388     (u32)( \
389     ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \
390     ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \
391     ((u32)(mode) << REG_MI_DMA2CNT_MODE_SHIFT) | \
392     ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \
393     ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \
394     ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \
395     ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \
396     ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT))
408     (u32)( \
409     ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT))
421     (u32)( \
422     ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT))
462     (u32)( \
463     ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \
464     ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \
465     ((u32)(mode) << REG_MI_DMA3CNT_MODE_SHIFT) | \
466     ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \
467     ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \
468     ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \
469     ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \
470     ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT))
511     ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \
512     ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \
513     ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \
514     ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \
515     ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \
516     ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT))
529     ((u32)(data) << REG_MI_MCD0_DATA_SHIFT))
567     (u32)( \
568     ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \
569     ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \
570     ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \
571     ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \
572     ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \
573     ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \
574     ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT))
598     (u32)( \
599     ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \
600     ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \
601     ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \
602     ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT))
626     (u32)( \
627     ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \
628     ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \
629     ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \
630     ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT))
671     ((u32)(ep) << REG_MI_EXMEMCNT_EP_SHIFT) | \
672     ((u32)(ifm) << REG_MI_EXMEMCNT_IFM_SHIFT) | \
673     ((u32)(mp) << REG_MI_EXMEMCNT_MP_SHIFT) | \
674     ((u32)(cp) << REG_MI_EXMEMCNT_CP_SHIFT) | \
675     ((u32)(phi) << REG_MI_EXMEMCNT_PHI_SHIFT) | \
676     ((u32)(rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT) | \
677     ((u32)(rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT) | \
678     ((u32)(ram) << REG_MI_EXMEMCNT_RAM_SHIFT))