Lines Matching refs:u32
867 ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \
868 ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \
869 ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \
870 ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \
871 ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \
872 ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \
873 ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \
874 ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \
875 ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \
876 ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \
877 ((u32)(ths) << REG_G3X_DISP3DCNT_THS_SHIFT) | \
878 ((u32)(tme) << REG_G3X_DISP3DCNT_TME_SHIFT))
891 ((u32)(rendered_lines_min) << REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT))
923 (u32)( \
924 ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT) | \
925 ((u32)(green1) << REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT) | \
926 ((u32)(red1) << REG_G3X_EDGE_COLOR_0_RED1_SHIFT) | \
927 ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT) | \
928 ((u32)(green0) << REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT) | \
929 ((u32)(red0) << REG_G3X_EDGE_COLOR_0_RED0_SHIFT))
950 ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT) | \
951 ((u32)(green0) << REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT) | \
952 ((u32)(red0) << REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT))
973 ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT) | \
974 ((u32)(green1) << REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT) | \
975 ((u32)(red1) << REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT))
1007 (u32)( \
1008 ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT) | \
1009 ((u32)(green3) << REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT) | \
1010 ((u32)(red3) << REG_G3X_EDGE_COLOR_1_RED3_SHIFT) | \
1011 ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT) | \
1012 ((u32)(green2) << REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT) | \
1013 ((u32)(red2) << REG_G3X_EDGE_COLOR_1_RED2_SHIFT))
1034 ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT) | \
1035 ((u32)(green2) << REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT) | \
1036 ((u32)(red2) << REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT))
1057 ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT) | \
1058 ((u32)(green3) << REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT) | \
1059 ((u32)(red3) << REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT))
1091 (u32)( \
1092 ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT) | \
1093 ((u32)(green5) << REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT) | \
1094 ((u32)(red5) << REG_G3X_EDGE_COLOR_2_RED5_SHIFT) | \
1095 ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT) | \
1096 ((u32)(green4) << REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT) | \
1097 ((u32)(red4) << REG_G3X_EDGE_COLOR_2_RED4_SHIFT))
1118 ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT) | \
1119 ((u32)(green4) << REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT) | \
1120 ((u32)(red4) << REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT))
1141 ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT) | \
1142 ((u32)(green5) << REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT) | \
1143 ((u32)(red5) << REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT))
1175 (u32)( \
1176 ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT) | \
1177 ((u32)(green7) << REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT) | \
1178 ((u32)(red7) << REG_G3X_EDGE_COLOR_3_RED7_SHIFT) | \
1179 ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT) | \
1180 ((u32)(green6) << REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT) | \
1181 ((u32)(red6) << REG_G3X_EDGE_COLOR_3_RED6_SHIFT))
1202 ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT) | \
1203 ((u32)(green6) << REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT) | \
1204 ((u32)(red6) << REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT))
1225 ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT) | \
1226 ((u32)(green7) << REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT) | \
1227 ((u32)(red7) << REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT))
1240 ((u32)(alpha_reference) << REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT))
1272 (u32)( \
1273 ((u32)(polygonid) << REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT) | \
1274 ((u32)(alpha) << REG_G3X_CLEAR_COLOR_ALPHA_SHIFT) | \
1275 ((u32)(f) << REG_G3X_CLEAR_COLOR_F_SHIFT) | \
1276 ((u32)(blue) << REG_G3X_CLEAR_COLOR_BLUE_SHIFT) | \
1277 ((u32)(green) << REG_G3X_CLEAR_COLOR_GREEN_SHIFT) | \
1278 ((u32)(red) << REG_G3X_CLEAR_COLOR_RED_SHIFT))
1291 ((u32)(cleardepth) << REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT))
1308 ((u32)(offsety) << REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT) | \
1309 ((u32)(offsetx) << REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT))
1333 (u32)( \
1334 ((u32)(fog_alpha) << REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT) | \
1335 ((u32)(fog_blue) << REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT) | \
1336 ((u32)(fog_green) << REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT) | \
1337 ((u32)(fog_red) << REG_G3X_FOG_COLOR_FOG_RED_SHIFT))
1350 ((u32)(fog_offset) << REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT))
1374 (u32)( \
1375 ((u32)(density3) << REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT) | \
1376 ((u32)(density2) << REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT) | \
1377 ((u32)(density1) << REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT) | \
1378 ((u32)(density0) << REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT))
1395 ((u32)(density1) << REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT) | \
1396 ((u32)(density0) << REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT))
1413 ((u32)(density3) << REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT) | \
1414 ((u32)(density2) << REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT))
1438 (u32)( \
1439 ((u32)(density7) << REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT) | \
1440 ((u32)(density6) << REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT) | \
1441 ((u32)(density5) << REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT) | \
1442 ((u32)(density4) << REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT))
1459 ((u32)(density5) << REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT) | \
1460 ((u32)(density4) << REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT))
1477 ((u32)(density7) << REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT) | \
1478 ((u32)(density6) << REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT))
1502 (u32)( \
1503 ((u32)(density11) << REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT) | \
1504 ((u32)(density10) << REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT) | \
1505 ((u32)(density9) << REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT) | \
1506 ((u32)(density8) << REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT))
1523 ((u32)(density9) << REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT) | \
1524 ((u32)(density8) << REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT))
1541 ((u32)(density11) << REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT) | \
1542 ((u32)(density10) << REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT))
1566 (u32)( \
1567 ((u32)(density15) << REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT) | \
1568 ((u32)(density14) << REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT) | \
1569 ((u32)(density13) << REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT) | \
1570 ((u32)(density12) << REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT))
1587 ((u32)(density13) << REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT) | \
1588 ((u32)(density12) << REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT))
1605 ((u32)(density15) << REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT) | \
1606 ((u32)(density14) << REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT))
1630 (u32)( \
1631 ((u32)(density19) << REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT) | \
1632 ((u32)(density18) << REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT) | \
1633 ((u32)(density17) << REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT) | \
1634 ((u32)(density16) << REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT))
1651 ((u32)(density17) << REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT) | \
1652 ((u32)(density16) << REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT))
1669 ((u32)(density19) << REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT) | \
1670 ((u32)(density18) << REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT))
1694 (u32)( \
1695 ((u32)(density23) << REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT) | \
1696 ((u32)(density22) << REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT) | \
1697 ((u32)(density21) << REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT) | \
1698 ((u32)(density20) << REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT))
1715 ((u32)(density21) << REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT) | \
1716 ((u32)(density20) << REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT))
1733 ((u32)(density23) << REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT) | \
1734 ((u32)(density22) << REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT))
1758 (u32)( \
1759 ((u32)(density27) << REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT) | \
1760 ((u32)(density26) << REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT) | \
1761 ((u32)(density25) << REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT) | \
1762 ((u32)(density24) << REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT))
1779 ((u32)(density25) << REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT) | \
1780 ((u32)(density24) << REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT))
1797 ((u32)(density27) << REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT) | \
1798 ((u32)(density26) << REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT))
1822 (u32)( \
1823 ((u32)(density31) << REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT) | \
1824 ((u32)(density30) << REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT) | \
1825 ((u32)(density29) << REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT) | \
1826 ((u32)(density28) << REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT))
1843 ((u32)(density29) << REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT) | \
1844 ((u32)(density28) << REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT))
1861 ((u32)(density31) << REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT) | \
1862 ((u32)(density30) << REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT))
1894 (u32)( \
1895 ((u32)(blue1) << REG_G3X_TOON_TABLE_0_BLUE1_SHIFT) | \
1896 ((u32)(green1) << REG_G3X_TOON_TABLE_0_GREEN1_SHIFT) | \
1897 ((u32)(red1) << REG_G3X_TOON_TABLE_0_RED1_SHIFT) | \
1898 ((u32)(blue0) << REG_G3X_TOON_TABLE_0_BLUE0_SHIFT) | \
1899 ((u32)(green0) << REG_G3X_TOON_TABLE_0_GREEN0_SHIFT) | \
1900 ((u32)(red0) << REG_G3X_TOON_TABLE_0_RED0_SHIFT))
1921 ((u32)(blue0) << REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT) | \
1922 ((u32)(green0) << REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT) | \
1923 ((u32)(red0) << REG_G3X_TOON_TABLE_0_L_RED0_SHIFT))
1944 ((u32)(blue1) << REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT) | \
1945 ((u32)(green1) << REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT) | \
1946 ((u32)(red1) << REG_G3X_TOON_TABLE_0_H_RED1_SHIFT))
1978 (u32)( \
1979 ((u32)(blue3) << REG_G3X_TOON_TABLE_1_BLUE3_SHIFT) | \
1980 ((u32)(green3) << REG_G3X_TOON_TABLE_1_GREEN3_SHIFT) | \
1981 ((u32)(red3) << REG_G3X_TOON_TABLE_1_RED3_SHIFT) | \
1982 ((u32)(blue2) << REG_G3X_TOON_TABLE_1_BLUE2_SHIFT) | \
1983 ((u32)(green2) << REG_G3X_TOON_TABLE_1_GREEN2_SHIFT) | \
1984 ((u32)(red2) << REG_G3X_TOON_TABLE_1_RED2_SHIFT))
2005 ((u32)(blue2) << REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT) | \
2006 ((u32)(green2) << REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT) | \
2007 ((u32)(red2) << REG_G3X_TOON_TABLE_1_L_RED2_SHIFT))
2028 ((u32)(blue3) << REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT) | \
2029 ((u32)(green3) << REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT) | \
2030 ((u32)(red3) << REG_G3X_TOON_TABLE_1_H_RED3_SHIFT))
2062 (u32)( \
2063 ((u32)(blue5) << REG_G3X_TOON_TABLE_2_BLUE5_SHIFT) | \
2064 ((u32)(green5) << REG_G3X_TOON_TABLE_2_GREEN5_SHIFT) | \
2065 ((u32)(red5) << REG_G3X_TOON_TABLE_2_RED5_SHIFT) | \
2066 ((u32)(blue4) << REG_G3X_TOON_TABLE_2_BLUE4_SHIFT) | \
2067 ((u32)(green4) << REG_G3X_TOON_TABLE_2_GREEN4_SHIFT) | \
2068 ((u32)(red4) << REG_G3X_TOON_TABLE_2_RED4_SHIFT))
2089 ((u32)(blue4) << REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT) | \
2090 ((u32)(green4) << REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT) | \
2091 ((u32)(red4) << REG_G3X_TOON_TABLE_2_L_RED4_SHIFT))
2112 ((u32)(blue5) << REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT) | \
2113 ((u32)(green5) << REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT) | \
2114 ((u32)(red5) << REG_G3X_TOON_TABLE_2_H_RED5_SHIFT))
2146 (u32)( \
2147 ((u32)(blue7) << REG_G3X_TOON_TABLE_3_BLUE7_SHIFT) | \
2148 ((u32)(green7) << REG_G3X_TOON_TABLE_3_GREEN7_SHIFT) | \
2149 ((u32)(red7) << REG_G3X_TOON_TABLE_3_RED7_SHIFT) | \
2150 ((u32)(blue6) << REG_G3X_TOON_TABLE_3_BLUE6_SHIFT) | \
2151 ((u32)(green6) << REG_G3X_TOON_TABLE_3_GREEN6_SHIFT) | \
2152 ((u32)(red6) << REG_G3X_TOON_TABLE_3_RED6_SHIFT))
2173 ((u32)(blue6) << REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT) | \
2174 ((u32)(green6) << REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT) | \
2175 ((u32)(red6) << REG_G3X_TOON_TABLE_3_L_RED6_SHIFT))
2196 ((u32)(blue7) << REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT) | \
2197 ((u32)(green7) << REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT) | \
2198 ((u32)(red7) << REG_G3X_TOON_TABLE_3_H_RED7_SHIFT))
2230 (u32)( \
2231 ((u32)(blue9) << REG_G3X_TOON_TABLE_4_BLUE9_SHIFT) | \
2232 ((u32)(green9) << REG_G3X_TOON_TABLE_4_GREEN9_SHIFT) | \
2233 ((u32)(red9) << REG_G3X_TOON_TABLE_4_RED9_SHIFT) | \
2234 ((u32)(blue8) << REG_G3X_TOON_TABLE_4_BLUE8_SHIFT) | \
2235 ((u32)(green8) << REG_G3X_TOON_TABLE_4_GREEN8_SHIFT) | \
2236 ((u32)(red8) << REG_G3X_TOON_TABLE_4_RED8_SHIFT))
2257 ((u32)(blue8) << REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT) | \
2258 ((u32)(green8) << REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT) | \
2259 ((u32)(red8) << REG_G3X_TOON_TABLE_4_L_RED8_SHIFT))
2280 ((u32)(blue9) << REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT) | \
2281 ((u32)(green9) << REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT) | \
2282 ((u32)(red9) << REG_G3X_TOON_TABLE_4_H_RED9_SHIFT))
2314 (u32)( \
2315 ((u32)(blue11) << REG_G3X_TOON_TABLE_5_BLUE11_SHIFT) | \
2316 ((u32)(green11) << REG_G3X_TOON_TABLE_5_GREEN11_SHIFT) | \
2317 ((u32)(red11) << REG_G3X_TOON_TABLE_5_RED11_SHIFT) | \
2318 ((u32)(blue10) << REG_G3X_TOON_TABLE_5_BLUE10_SHIFT) | \
2319 ((u32)(green10) << REG_G3X_TOON_TABLE_5_GREEN10_SHIFT) | \
2320 ((u32)(red10) << REG_G3X_TOON_TABLE_5_RED10_SHIFT))
2341 ((u32)(blue10) << REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT) | \
2342 ((u32)(green10) << REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT) | \
2343 ((u32)(red10) << REG_G3X_TOON_TABLE_5_L_RED10_SHIFT))
2364 ((u32)(blue11) << REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT) | \
2365 ((u32)(green11) << REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT) | \
2366 ((u32)(red11) << REG_G3X_TOON_TABLE_5_H_RED11_SHIFT))
2398 (u32)( \
2399 ((u32)(blue13) << REG_G3X_TOON_TABLE_6_BLUE13_SHIFT) | \
2400 ((u32)(green13) << REG_G3X_TOON_TABLE_6_GREEN13_SHIFT) | \
2401 ((u32)(red13) << REG_G3X_TOON_TABLE_6_RED13_SHIFT) | \
2402 ((u32)(blue12) << REG_G3X_TOON_TABLE_6_BLUE12_SHIFT) | \
2403 ((u32)(green12) << REG_G3X_TOON_TABLE_6_GREEN12_SHIFT) | \
2404 ((u32)(red12) << REG_G3X_TOON_TABLE_6_RED12_SHIFT))
2425 ((u32)(blue12) << REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT) | \
2426 ((u32)(green12) << REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT) | \
2427 ((u32)(red12) << REG_G3X_TOON_TABLE_6_L_RED12_SHIFT))
2448 ((u32)(blue13) << REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT) | \
2449 ((u32)(green13) << REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT) | \
2450 ((u32)(red13) << REG_G3X_TOON_TABLE_6_H_RED13_SHIFT))
2482 (u32)( \
2483 ((u32)(blue15) << REG_G3X_TOON_TABLE_7_BLUE15_SHIFT) | \
2484 ((u32)(green15) << REG_G3X_TOON_TABLE_7_GREEN15_SHIFT) | \
2485 ((u32)(red15) << REG_G3X_TOON_TABLE_7_RED15_SHIFT) | \
2486 ((u32)(blue14) << REG_G3X_TOON_TABLE_7_BLUE14_SHIFT) | \
2487 ((u32)(green14) << REG_G3X_TOON_TABLE_7_GREEN14_SHIFT) | \
2488 ((u32)(red14) << REG_G3X_TOON_TABLE_7_RED14_SHIFT))
2509 ((u32)(blue14) << REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT) | \
2510 ((u32)(green14) << REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT) | \
2511 ((u32)(red14) << REG_G3X_TOON_TABLE_7_L_RED14_SHIFT))
2532 ((u32)(blue15) << REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT) | \
2533 ((u32)(green15) << REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT) | \
2534 ((u32)(red15) << REG_G3X_TOON_TABLE_7_H_RED15_SHIFT))
2566 (u32)( \
2567 ((u32)(blue17) << REG_G3X_TOON_TABLE_8_BLUE17_SHIFT) | \
2568 ((u32)(green17) << REG_G3X_TOON_TABLE_8_GREEN17_SHIFT) | \
2569 ((u32)(red17) << REG_G3X_TOON_TABLE_8_RED17_SHIFT) | \
2570 ((u32)(blue16) << REG_G3X_TOON_TABLE_8_BLUE16_SHIFT) | \
2571 ((u32)(green16) << REG_G3X_TOON_TABLE_8_GREEN16_SHIFT) | \
2572 ((u32)(red16) << REG_G3X_TOON_TABLE_8_RED16_SHIFT))
2593 ((u32)(blue16) << REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT) | \
2594 ((u32)(green16) << REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT) | \
2595 ((u32)(red16) << REG_G3X_TOON_TABLE_8_L_RED16_SHIFT))
2616 ((u32)(blue17) << REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT) | \
2617 ((u32)(green17) << REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT) | \
2618 ((u32)(red17) << REG_G3X_TOON_TABLE_8_H_RED17_SHIFT))
2650 (u32)( \
2651 ((u32)(blue19) << REG_G3X_TOON_TABLE_9_BLUE19_SHIFT) | \
2652 ((u32)(green19) << REG_G3X_TOON_TABLE_9_GREEN19_SHIFT) | \
2653 ((u32)(red19) << REG_G3X_TOON_TABLE_9_RED19_SHIFT) | \
2654 ((u32)(blue18) << REG_G3X_TOON_TABLE_9_BLUE18_SHIFT) | \
2655 ((u32)(green18) << REG_G3X_TOON_TABLE_9_GREEN18_SHIFT) | \
2656 ((u32)(red18) << REG_G3X_TOON_TABLE_9_RED18_SHIFT))
2677 ((u32)(blue18) << REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT) | \
2678 ((u32)(green18) << REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT) | \
2679 ((u32)(red18) << REG_G3X_TOON_TABLE_9_L_RED18_SHIFT))
2700 ((u32)(blue19) << REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT) | \
2701 ((u32)(green19) << REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT) | \
2702 ((u32)(red19) << REG_G3X_TOON_TABLE_9_H_RED19_SHIFT))
2734 (u32)( \
2735 ((u32)(blue21) << REG_G3X_TOON_TABLE_10_BLUE21_SHIFT) | \
2736 ((u32)(green21) << REG_G3X_TOON_TABLE_10_GREEN21_SHIFT) | \
2737 ((u32)(red21) << REG_G3X_TOON_TABLE_10_RED21_SHIFT) | \
2738 ((u32)(blue20) << REG_G3X_TOON_TABLE_10_BLUE20_SHIFT) | \
2739 ((u32)(green20) << REG_G3X_TOON_TABLE_10_GREEN20_SHIFT) | \
2740 ((u32)(red20) << REG_G3X_TOON_TABLE_10_RED20_SHIFT))
2761 ((u32)(blue20) << REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT) | \
2762 ((u32)(green20) << REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT) | \
2763 ((u32)(red20) << REG_G3X_TOON_TABLE_10_L_RED20_SHIFT))
2784 ((u32)(blue21) << REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT) | \
2785 ((u32)(green21) << REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT) | \
2786 ((u32)(red21) << REG_G3X_TOON_TABLE_10_H_RED21_SHIFT))
2818 (u32)( \
2819 ((u32)(blue23) << REG_G3X_TOON_TABLE_11_BLUE23_SHIFT) | \
2820 ((u32)(green23) << REG_G3X_TOON_TABLE_11_GREEN23_SHIFT) | \
2821 ((u32)(red23) << REG_G3X_TOON_TABLE_11_RED23_SHIFT) | \
2822 ((u32)(blue22) << REG_G3X_TOON_TABLE_11_BLUE22_SHIFT) | \
2823 ((u32)(green22) << REG_G3X_TOON_TABLE_11_GREEN22_SHIFT) | \
2824 ((u32)(red22) << REG_G3X_TOON_TABLE_11_RED22_SHIFT))
2845 ((u32)(blue22) << REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT) | \
2846 ((u32)(green22) << REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT) | \
2847 ((u32)(red22) << REG_G3X_TOON_TABLE_11_L_RED22_SHIFT))
2868 ((u32)(blue23) << REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT) | \
2869 ((u32)(green23) << REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT) | \
2870 ((u32)(red23) << REG_G3X_TOON_TABLE_11_H_RED23_SHIFT))
2902 (u32)( \
2903 ((u32)(blue25) << REG_G3X_TOON_TABLE_12_BLUE25_SHIFT) | \
2904 ((u32)(green25) << REG_G3X_TOON_TABLE_12_GREEN25_SHIFT) | \
2905 ((u32)(red25) << REG_G3X_TOON_TABLE_12_RED25_SHIFT) | \
2906 ((u32)(blue24) << REG_G3X_TOON_TABLE_12_BLUE24_SHIFT) | \
2907 ((u32)(green24) << REG_G3X_TOON_TABLE_12_GREEN24_SHIFT) | \
2908 ((u32)(red24) << REG_G3X_TOON_TABLE_12_RED24_SHIFT))
2929 ((u32)(blue24) << REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT) | \
2930 ((u32)(green24) << REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT) | \
2931 ((u32)(red24) << REG_G3X_TOON_TABLE_12_L_RED24_SHIFT))
2952 ((u32)(blue25) << REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT) | \
2953 ((u32)(green25) << REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT) | \
2954 ((u32)(red25) << REG_G3X_TOON_TABLE_12_H_RED25_SHIFT))
2986 (u32)( \
2987 ((u32)(blue27) << REG_G3X_TOON_TABLE_13_BLUE27_SHIFT) | \
2988 ((u32)(green27) << REG_G3X_TOON_TABLE_13_GREEN27_SHIFT) | \
2989 ((u32)(red27) << REG_G3X_TOON_TABLE_13_RED27_SHIFT) | \
2990 ((u32)(blue26) << REG_G3X_TOON_TABLE_13_BLUE26_SHIFT) | \
2991 ((u32)(green26) << REG_G3X_TOON_TABLE_13_GREEN26_SHIFT) | \
2992 ((u32)(red26) << REG_G3X_TOON_TABLE_13_RED26_SHIFT))
3013 ((u32)(blue26) << REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT) | \
3014 ((u32)(green26) << REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT) | \
3015 ((u32)(red26) << REG_G3X_TOON_TABLE_13_L_RED26_SHIFT))
3036 ((u32)(blue27) << REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT) | \
3037 ((u32)(green27) << REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT) | \
3038 ((u32)(red27) << REG_G3X_TOON_TABLE_13_H_RED27_SHIFT))
3070 (u32)( \
3071 ((u32)(blue29) << REG_G3X_TOON_TABLE_14_BLUE29_SHIFT) | \
3072 ((u32)(green29) << REG_G3X_TOON_TABLE_14_GREEN29_SHIFT) | \
3073 ((u32)(red29) << REG_G3X_TOON_TABLE_14_RED29_SHIFT) | \
3074 ((u32)(blue28) << REG_G3X_TOON_TABLE_14_BLUE28_SHIFT) | \
3075 ((u32)(green28) << REG_G3X_TOON_TABLE_14_GREEN28_SHIFT) | \
3076 ((u32)(red28) << REG_G3X_TOON_TABLE_14_RED28_SHIFT))
3097 ((u32)(blue28) << REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT) | \
3098 ((u32)(green28) << REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT) | \
3099 ((u32)(red28) << REG_G3X_TOON_TABLE_14_L_RED28_SHIFT))
3120 ((u32)(blue29) << REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT) | \
3121 ((u32)(green29) << REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT) | \
3122 ((u32)(red29) << REG_G3X_TOON_TABLE_14_H_RED29_SHIFT))
3154 (u32)( \
3155 ((u32)(blue31) << REG_G3X_TOON_TABLE_15_BLUE31_SHIFT) | \
3156 ((u32)(green31) << REG_G3X_TOON_TABLE_15_GREEN31_SHIFT) | \
3157 ((u32)(red31) << REG_G3X_TOON_TABLE_15_RED31_SHIFT) | \
3158 ((u32)(blue30) << REG_G3X_TOON_TABLE_15_BLUE30_SHIFT) | \
3159 ((u32)(green30) << REG_G3X_TOON_TABLE_15_GREEN30_SHIFT) | \
3160 ((u32)(red30) << REG_G3X_TOON_TABLE_15_RED30_SHIFT))
3181 ((u32)(blue30) << REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT) | \
3182 ((u32)(green30) << REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT) | \
3183 ((u32)(red30) << REG_G3X_TOON_TABLE_15_L_RED30_SHIFT))
3204 ((u32)(blue31) << REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT) | \
3205 ((u32)(green31) << REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT) | \
3206 ((u32)(red31) << REG_G3X_TOON_TABLE_15_H_RED31_SHIFT))
3264 (u32)( \
3265 ((u32)(fi) << REG_G3X_GXSTAT_FI_SHIFT) | \
3266 ((u32)(b) << REG_G3X_GXSTAT_B_SHIFT) | \
3267 ((u32)(e) << REG_G3X_GXSTAT_E_SHIFT) | \
3268 ((u32)(h) << REG_G3X_GXSTAT_H_SHIFT) | \
3269 ((u32)(f) << REG_G3X_GXSTAT_F_SHIFT) | \
3270 ((u32)(fifocnt) << REG_G3X_GXSTAT_FIFOCNT_SHIFT) | \
3271 ((u32)(se) << REG_G3X_GXSTAT_SE_SHIFT) | \
3272 ((u32)(sb) << REG_G3X_GXSTAT_SB_SHIFT) | \
3273 ((u32)(pj) << REG_G3X_GXSTAT_PJ_SHIFT) | \
3274 ((u32)(pv) << REG_G3X_GXSTAT_PV_SHIFT) | \
3275 ((u32)(tr) << REG_G3X_GXSTAT_TR_SHIFT) | \
3276 ((u32)(tb) << REG_G3X_GXSTAT_TB_SHIFT))
3289 ((u32)(ramcnt) << REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT))
3302 ((u32)(vtxcnt) << REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT))
3319 ((u32)(integer_w) << REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT) | \
3320 ((u32)(decimal_w) << REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT))
3340 (u32)( \
3341 ((u32)(sx) << REG_G3X_POS_RESULT_X_SX_SHIFT) | \
3342 ((u32)(integer_x) << REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT) | \
3343 ((u32)(decimal_x) << REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT))
3363 (u32)( \
3364 ((u32)(sy) << REG_G3X_POS_RESULT_Y_SY_SHIFT) | \
3365 ((u32)(integer_y) << REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT) | \
3366 ((u32)(decimal_y) << REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT))
3386 (u32)( \
3387 ((u32)(sz) << REG_G3X_POS_RESULT_Z_SZ_SHIFT) | \
3388 ((u32)(integer_z) << REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT) | \
3389 ((u32)(decimal_z) << REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT))
3409 (u32)( \
3410 ((u32)(sw) << REG_G3X_POS_RESULT_W_SW_SHIFT) | \
3411 ((u32)(integer_w) << REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT) | \
3412 ((u32)(decimal_w) << REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT))
3433 ((u32)(sx) << REG_G3X_VEC_RESULT_X_SX_SHIFT) | \
3434 ((u32)(integer_x) << REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT) | \
3435 ((u32)(decimal_x) << REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT))
3456 ((u32)(sy) << REG_G3X_VEC_RESULT_Y_SY_SHIFT) | \
3457 ((u32)(integer_y) << REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT) | \
3458 ((u32)(decimal_y) << REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT))
3479 ((u32)(sz) << REG_G3X_VEC_RESULT_Z_SZ_SHIFT) | \
3480 ((u32)(integer_z) << REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT) | \
3481 ((u32)(decimal_z) << REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT))
3501 (u32)( \
3502 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_0_S_SHIFT) | \
3503 ((u32)(integer_m0) << REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT) | \
3504 ((u32)(decimal_m0) << REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT))
3524 (u32)( \
3525 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_1_S_SHIFT) | \
3526 ((u32)(integer_m1) << REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT) | \
3527 ((u32)(decimal_m1) << REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT))
3547 (u32)( \
3548 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_2_S_SHIFT) | \
3549 ((u32)(integer_m2) << REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT) | \
3550 ((u32)(decimal_m2) << REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT))
3570 (u32)( \
3571 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_3_S_SHIFT) | \
3572 ((u32)(integer_m3) << REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT) | \
3573 ((u32)(decimal_m3) << REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT))
3593 (u32)( \
3594 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_4_S_SHIFT) | \
3595 ((u32)(integer_m4) << REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT) | \
3596 ((u32)(decimal_m4) << REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT))
3616 (u32)( \
3617 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_5_S_SHIFT) | \
3618 ((u32)(integer_m5) << REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT) | \
3619 ((u32)(decimal_m5) << REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT))
3639 (u32)( \
3640 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_6_S_SHIFT) | \
3641 ((u32)(integer_m6) << REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT) | \
3642 ((u32)(decimal_m6) << REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT))
3662 (u32)( \
3663 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_7_S_SHIFT) | \
3664 ((u32)(integer_m7) << REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT) | \
3665 ((u32)(decimal_m7) << REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT))
3685 (u32)( \
3686 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_8_S_SHIFT) | \
3687 ((u32)(integer_m8) << REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT) | \
3688 ((u32)(decimal_m8) << REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT))
3708 (u32)( \
3709 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_9_S_SHIFT) | \
3710 ((u32)(integer_m9) << REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT) | \
3711 ((u32)(decimal_m9) << REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT))
3731 (u32)( \
3732 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_10_S_SHIFT) | \
3733 ((u32)(integer_m10) << REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT) | \
3734 ((u32)(decimal_m10) << REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT))
3754 (u32)( \
3755 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_11_S_SHIFT) | \
3756 ((u32)(integer_m11) << REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT) | \
3757 ((u32)(decimal_m11) << REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT))
3777 (u32)( \
3778 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_12_S_SHIFT) | \
3779 ((u32)(integer_m12) << REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT) | \
3780 ((u32)(decimal_m12) << REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT))
3800 (u32)( \
3801 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_13_S_SHIFT) | \
3802 ((u32)(integer_m13) << REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT) | \
3803 ((u32)(decimal_m13) << REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT))
3823 (u32)( \
3824 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_14_S_SHIFT) | \
3825 ((u32)(integer_m14) << REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT) | \
3826 ((u32)(decimal_m14) << REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT))
3846 (u32)( \
3847 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_15_S_SHIFT) | \
3848 ((u32)(integer_m15) << REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT) | \
3849 ((u32)(decimal_m15) << REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT))
3869 (u32)( \
3870 ((u32)(s) << REG_G3X_VECMTX_RESULT_0_S_SHIFT) | \
3871 ((u32)(integer_m0) << REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT) | \
3872 ((u32)(decimal_m0) << REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT))
3892 (u32)( \
3893 ((u32)(s) << REG_G3X_VECMTX_RESULT_1_S_SHIFT) | \
3894 ((u32)(integer_m1) << REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT) | \
3895 ((u32)(decimal_m1) << REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT))
3915 (u32)( \
3916 ((u32)(s) << REG_G3X_VECMTX_RESULT_2_S_SHIFT) | \
3917 ((u32)(integer_m2) << REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT) | \
3918 ((u32)(decimal_m2) << REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT))
3938 (u32)( \
3939 ((u32)(s) << REG_G3X_VECMTX_RESULT_3_S_SHIFT) | \
3940 ((u32)(integer_m3) << REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT) | \
3941 ((u32)(decimal_m3) << REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT))
3961 (u32)( \
3962 ((u32)(s) << REG_G3X_VECMTX_RESULT_4_S_SHIFT) | \
3963 ((u32)(integer_m4) << REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT) | \
3964 ((u32)(decimal_m4) << REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT))
3984 (u32)( \
3985 ((u32)(s) << REG_G3X_VECMTX_RESULT_5_S_SHIFT) | \
3986 ((u32)(integer_m5) << REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT) | \
3987 ((u32)(decimal_m5) << REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT))
4007 (u32)( \
4008 ((u32)(s) << REG_G3X_VECMTX_RESULT_6_S_SHIFT) | \
4009 ((u32)(integer_m6) << REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT) | \
4010 ((u32)(decimal_m6) << REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT))
4030 (u32)( \
4031 ((u32)(s) << REG_G3X_VECMTX_RESULT_7_S_SHIFT) | \
4032 ((u32)(integer_m7) << REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT) | \
4033 ((u32)(decimal_m7) << REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT))
4053 (u32)( \
4054 ((u32)(s) << REG_G3X_VECMTX_RESULT_8_S_SHIFT) | \
4055 ((u32)(integer_m8) << REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT) | \
4056 ((u32)(decimal_m8) << REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT))