Lines Matching refs:u32
121 ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT))
142 ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \
143 ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \
144 ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT))
157 ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT))
182 ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \
183 ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \
184 ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \
185 ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT))
198 ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT))
223 ((u32)(e) << REG_OS_TM2CNT_H_E_SHIFT) | \
224 ((u32)(i) << REG_OS_TM2CNT_H_I_SHIFT) | \
225 ((u32)(ch) << REG_OS_TM2CNT_H_CH_SHIFT) | \
226 ((u32)(ps) << REG_OS_TM2CNT_H_PS_SHIFT))
239 ((u32)(timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT))
264 ((u32)(e) << REG_OS_TM3CNT_H_E_SHIFT) | \
265 ((u32)(i) << REG_OS_TM3CNT_H_I_SHIFT) | \
266 ((u32)(ch) << REG_OS_TM3CNT_H_CH_SHIFT) | \
267 ((u32)(ps) << REG_OS_TM3CNT_H_PS_SHIFT))
280 ((u32)(ime) << REG_OS_IME_IME_SHIFT))
420 (u32)( \
421 ((u32)(nd3) << REG_OS_IE_ND3_SHIFT) | \
422 ((u32)(nd2) << REG_OS_IE_ND2_SHIFT) | \
423 ((u32)(nd1) << REG_OS_IE_ND1_SHIFT) | \
424 ((u32)(nd0) << REG_OS_IE_ND0_SHIFT) | \
425 ((u32)(mib) << REG_OS_IE_MIB_SHIFT) | \
426 ((u32)(mcb) << REG_OS_IE_MCB_SHIFT) | \
427 ((u32)(cam) << REG_OS_IE_CAM_SHIFT) | \
428 ((u32)(dsp) << REG_OS_IE_DSP_SHIFT) | \
429 ((u32)(dwe) << REG_OS_IE_DWE_SHIFT) | \
430 ((u32)(dre) << REG_OS_IE_DRE_SHIFT) | \
431 ((u32)(gf) << REG_OS_IE_GF_SHIFT) | \
432 ((u32)(mia) << REG_OS_IE_MIA_SHIFT) | \
433 ((u32)(mi) << REG_OS_IE_MI_SHIFT) | \
434 ((u32)(mca) << REG_OS_IE_MCA_SHIFT) | \
435 ((u32)(mc) << REG_OS_IE_MC_SHIFT) | \
436 ((u32)(ifn) << REG_OS_IE_IFN_SHIFT) | \
437 ((u32)(ife) << REG_OS_IE_IFE_SHIFT) | \
438 ((u32)(a7) << REG_OS_IE_A7_SHIFT) | \
439 ((u32)(mcbdet) << REG_OS_IE_MCBDET_SHIFT) | \
440 ((u32)(mcadet) << REG_OS_IE_MCADET_SHIFT) | \
441 ((u32)(i_d) << REG_OS_IE_I_D_SHIFT) | \
442 ((u32)(k) << REG_OS_IE_K_SHIFT) | \
443 ((u32)(d3) << REG_OS_IE_D3_SHIFT) | \
444 ((u32)(d2) << REG_OS_IE_D2_SHIFT) | \
445 ((u32)(d1) << REG_OS_IE_D1_SHIFT) | \
446 ((u32)(d0) << REG_OS_IE_D0_SHIFT) | \
447 ((u32)(t3) << REG_OS_IE_T3_SHIFT) | \
448 ((u32)(t2) << REG_OS_IE_T2_SHIFT) | \
449 ((u32)(t1) << REG_OS_IE_T1_SHIFT) | \
450 ((u32)(t0) << REG_OS_IE_T0_SHIFT) | \
451 ((u32)(ve) << REG_OS_IE_VE_SHIFT) | \
452 ((u32)(hb) << REG_OS_IE_HB_SHIFT) | \
453 ((u32)(vb) << REG_OS_IE_VB_SHIFT))
593 (u32)( \
594 ((u32)(nd3) << REG_OS_IF_ND3_SHIFT) | \
595 ((u32)(nd2) << REG_OS_IF_ND2_SHIFT) | \
596 ((u32)(nd1) << REG_OS_IF_ND1_SHIFT) | \
597 ((u32)(nd0) << REG_OS_IF_ND0_SHIFT) | \
598 ((u32)(mib) << REG_OS_IF_MIB_SHIFT) | \
599 ((u32)(mcb) << REG_OS_IF_MCB_SHIFT) | \
600 ((u32)(cam) << REG_OS_IF_CAM_SHIFT) | \
601 ((u32)(dsp) << REG_OS_IF_DSP_SHIFT) | \
602 ((u32)(dwe) << REG_OS_IF_DWE_SHIFT) | \
603 ((u32)(dre) << REG_OS_IF_DRE_SHIFT) | \
604 ((u32)(gf) << REG_OS_IF_GF_SHIFT) | \
605 ((u32)(mia) << REG_OS_IF_MIA_SHIFT) | \
606 ((u32)(mi) << REG_OS_IF_MI_SHIFT) | \
607 ((u32)(mca) << REG_OS_IF_MCA_SHIFT) | \
608 ((u32)(mc) << REG_OS_IF_MC_SHIFT) | \
609 ((u32)(ifn) << REG_OS_IF_IFN_SHIFT) | \
610 ((u32)(ife) << REG_OS_IF_IFE_SHIFT) | \
611 ((u32)(a7) << REG_OS_IF_A7_SHIFT) | \
612 ((u32)(mcbdet) << REG_OS_IF_MCBDET_SHIFT) | \
613 ((u32)(mcadet) << REG_OS_IF_MCADET_SHIFT) | \
614 ((u32)(i_d) << REG_OS_IF_I_D_SHIFT) | \
615 ((u32)(k) << REG_OS_IF_K_SHIFT) | \
616 ((u32)(d3) << REG_OS_IF_D3_SHIFT) | \
617 ((u32)(d2) << REG_OS_IF_D2_SHIFT) | \
618 ((u32)(d1) << REG_OS_IF_D1_SHIFT) | \
619 ((u32)(d0) << REG_OS_IF_D0_SHIFT) | \
620 ((u32)(t3) << REG_OS_IF_T3_SHIFT) | \
621 ((u32)(t2) << REG_OS_IF_T2_SHIFT) | \
622 ((u32)(t1) << REG_OS_IF_T1_SHIFT) | \
623 ((u32)(t0) << REG_OS_IF_T0_SHIFT) | \
624 ((u32)(ve) << REG_OS_IF_VE_SHIFT) | \
625 ((u32)(hb) << REG_OS_IF_HB_SHIFT) | \
626 ((u32)(vb) << REG_OS_IF_VB_SHIFT))
647 ((u32)(mod) << REG_OS_PAUSE_MOD_SHIFT) | \
648 ((u32)(jtag_e) << REG_OS_PAUSE_JTAG_E_SHIFT) | \
649 ((u32)(chk) << REG_OS_PAUSE_CHK_SHIFT))