Searched refs:REGType32v (Results 1 – 25 of 30) sorted by relevance
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50 #define reg_CP_DIV_NUMER_L (*( REGType32v *) REG_DIV_NUMER_L_ADDR)56 #define reg_CP_DIV_NUMER_H (*( REGType32v *) REG_DIV_NUMER_H_ADDR)68 #define reg_CP_DIV_DENOM_L (*( REGType32v *) REG_DIV_DENOM_L_ADDR)74 #define reg_CP_DIV_DENOM_H (*( REGType32v *) REG_DIV_DENOM_H_ADDR)86 #define reg_CP_DIV_RESULT_L (*( REGType32v *) REG_DIV_RESULT_L_ADDR)92 #define reg_CP_DIV_RESULT_H (*( REGType32v *) REG_DIV_RESULT_H_ADDR)104 #define reg_CP_DIVREM_RESULT_L (*( REGType32v *) REG_DIVREM_RESULT_L_AD…110 #define reg_CP_DIVREM_RESULT_H (*( REGType32v *) REG_DIVREM_RESULT_H_AD…122 #define reg_CP_SQRT_RESULT (*( REGType32v *) REG_SQRT_RESULT_ADDR)134 #define reg_CP_SQRT_PARAM_L (*( REGType32v *) REG_SQRT_PARAM_L_ADDR)[all …]
38 #define reg_MI_DMA0SAD (*( REGType32v *) REG_DMA0SAD_ADDR)44 #define reg_MI_DMA0DAD (*( REGType32v *) REG_DMA0DAD_ADDR)50 #define reg_MI_DMA0CNT (*( REGType32v *) REG_DMA0CNT_ADDR)56 #define reg_MI_DMA1SAD (*( REGType32v *) REG_DMA1SAD_ADDR)62 #define reg_MI_DMA1DAD (*( REGType32v *) REG_DMA1DAD_ADDR)68 #define reg_MI_DMA1CNT (*( REGType32v *) REG_DMA1CNT_ADDR)74 #define reg_MI_DMA2SAD (*( REGType32v *) REG_DMA2SAD_ADDR)80 #define reg_MI_DMA2DAD (*( REGType32v *) REG_DMA2DAD_ADDR)86 #define reg_MI_DMA2CNT (*( REGType32v *) REG_DMA2CNT_ADDR)92 #define reg_MI_DMA3SAD (*( REGType32v *) REG_DMA3SAD_ADDR)[all …]
38 #define reg_G3_MTX_MODE (*( REGType32v *) REG_MTX_MODE_ADDR)44 #define reg_G3_MTX_PUSH (*( REGType32v *) REG_MTX_PUSH_ADDR)50 #define reg_G3_MTX_POP (*( REGType32v *) REG_MTX_POP_ADDR)56 #define reg_G3_MTX_STORE (*( REGType32v *) REG_MTX_STORE_ADDR)62 #define reg_G3_MTX_RESTORE (*( REGType32v *) REG_MTX_RESTORE_ADDR)68 #define reg_G3_MTX_IDENTITY (*( REGType32v *) REG_MTX_IDENTITY_ADDR)74 #define reg_G3_MTX_LOAD_4x4 (*( REGType32v *) REG_MTX_LOAD_4x4_ADDR)80 #define reg_G3_MTX_LOAD_4x3 (*( REGType32v *) REG_MTX_LOAD_4x3_ADDR)86 #define reg_G3_MTX_MULT_4x4 (*( REGType32v *) REG_MTX_MULT_4x4_ADDR)92 #define reg_G3_MTX_MULT_4x3 (*( REGType32v *) REG_MTX_MULT_4x3_ADDR)[all …]
50 #define reg_G3X_EDGE_COLOR_0 (*( REGType32v *) REG_EDGE_COLOR_0_ADDR)68 #define reg_G3X_EDGE_COLOR_1 (*( REGType32v *) REG_EDGE_COLOR_1_ADDR)86 #define reg_G3X_EDGE_COLOR_2 (*( REGType32v *) REG_EDGE_COLOR_2_ADDR)104 #define reg_G3X_EDGE_COLOR_3 (*( REGType32v *) REG_EDGE_COLOR_3_ADDR)128 #define reg_G3X_CLEAR_COLOR (*( REGType32v *) REG_CLEAR_COLOR_ADDR)146 #define reg_G3X_FOG_COLOR (*( REGType32v *) REG_FOG_COLOR_ADDR)158 #define reg_G3X_FOG_TABLE_0 (*( REGType32v *) REG_FOG_TABLE_0_ADDR)176 #define reg_G3X_FOG_TABLE_1 (*( REGType32v *) REG_FOG_TABLE_1_ADDR)194 #define reg_G3X_FOG_TABLE_2 (*( REGType32v *) REG_FOG_TABLE_2_ADDR)212 #define reg_G3X_FOG_TABLE_3 (*( REGType32v *) REG_FOG_TABLE_3_ADDR)[all …]
50 #define reg_PXI_SEND_FIFO (*( REGType32v *) REG_SEND_FIFO_ADDR)56 #define reg_PXI_RECV_FIFO (*( REGType32v *) REG_RECV_FIFO_ADDR)
62 #define reg_G2S_DB_BG0OFS (*( REGType32v *) REG_DB_BG0OFS_ADDR)80 #define reg_G2S_DB_BG1OFS (*( REGType32v *) REG_DB_BG1OFS_ADDR)98 #define reg_G2S_DB_BG2OFS (*( REGType32v *) REG_DB_BG2OFS_ADDR)116 #define reg_G2S_DB_BG3OFS (*( REGType32v *) REG_DB_BG3OFS_ADDR)158 #define reg_G2S_DB_BG2X (*( REGType32v *) REG_DB_BG2X_ADDR)164 #define reg_G2S_DB_BG2Y (*( REGType32v *) REG_DB_BG2Y_ADDR)194 #define reg_G2S_DB_BG3X (*( REGType32v *) REG_DB_BG3X_ADDR)200 #define reg_G2S_DB_BG3Y (*( REGType32v *) REG_DB_BG3Y_ADDR)
62 #define reg_G2_BG0OFS (*( REGType32v *) REG_BG0OFS_ADDR)80 #define reg_G2_BG1OFS (*( REGType32v *) REG_BG1OFS_ADDR)98 #define reg_G2_BG2OFS (*( REGType32v *) REG_BG2OFS_ADDR)116 #define reg_G2_BG3OFS (*( REGType32v *) REG_BG3OFS_ADDR)158 #define reg_G2_BG2X (*( REGType32v *) REG_BG2X_ADDR)164 #define reg_G2_BG2Y (*( REGType32v *) REG_BG2Y_ADDR)194 #define reg_G2_BG3X (*( REGType32v *) REG_BG3X_ADDR)200 #define reg_G2_BG3Y (*( REGType32v *) REG_BG3Y_ADDR)
38 #define reg_EXI_SIODATA32 (*( REGType32v *) REG_SIODATA32_ADDR)
38 #define reg_GX_DISPCNT (*( REGType32v *) REG_DISPCNT_ADDR)56 #define reg_GX_DISPCAPCNT (*( REGType32v *) REG_DISPCAPCNT_ADDR)62 #define reg_GX_DISP_MMEM_FIFO (*( REGType32v *) REG_DISP_MMEM_FIFO_ADD…92 #define reg_GX_VRAMCNT (*( REGType32v *) REG_VRAMCNT_ADDR)122 #define reg_GX_WVRAMCNT (*( REGType32v *) REG_WVRAMCNT_ADDR)
38 #define reg_GXS_DB_DISPCNT (*( REGType32v *) REG_DB_DISPCNT_ADDR)
50 #define reg_CAM_DAT (*(const REGType32v *) REG_DAT_ADDR)56 #define reg_CAM_SOFS (*( REGType32v *) REG_SOFS_ADDR)62 #define reg_CAM_EOFS (*( REGType32v *) REG_EOFS_ADDR)
107 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = 0; in G3_Direct0()123 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; in G3_Direct1()140 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; in G3_Direct2()141 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param1; in G3_Direct2()159 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; in G3_Direct3()160 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param1; in G3_Direct3()161 *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param2; in G3_Direct3()
76 typedef vu32 REGType32v; typedef
81 typedef vu32 REGType32v; typedef