1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_GXS.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_GXS_H_ 18 #define TWL_HW_ARM9_IOREG_GXS_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DB_DISPCNT */ 35 36 #define REG_DB_DISPCNT_OFFSET 0x1000 37 #define REG_DB_DISPCNT_ADDR (HW_REG_BASE + REG_DB_DISPCNT_OFFSET) 38 #define reg_GXS_DB_DISPCNT (*( REGType32v *) REG_DB_DISPCNT_ADDR) 39 40 /* DB_MASTER_BRIGHT */ 41 42 #define REG_DB_MASTER_BRIGHT_OFFSET 0x106c 43 #define REG_DB_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_DB_MASTER_BRIGHT_OFFSET) 44 #define reg_GXS_DB_MASTER_BRIGHT (*( REGType16v *) REG_DB_MASTER_BRIGHT_ADDR) 45 46 47 /* 48 * Definitions of Register fields 49 */ 50 51 52 /* DB_DISPCNT */ 53 54 #define REG_GXS_DB_DISPCNT_O_SHIFT 31 55 #define REG_GXS_DB_DISPCNT_O_SIZE 1 56 #define REG_GXS_DB_DISPCNT_O_MASK 0x80000000 57 58 #define REG_GXS_DB_DISPCNT_BG_SHIFT 30 59 #define REG_GXS_DB_DISPCNT_BG_SIZE 1 60 #define REG_GXS_DB_DISPCNT_BG_MASK 0x40000000 61 62 #define REG_GXS_DB_DISPCNT_OH_SHIFT 23 63 #define REG_GXS_DB_DISPCNT_OH_SIZE 1 64 #define REG_GXS_DB_DISPCNT_OH_MASK 0x00800000 65 66 #define REG_GXS_DB_DISPCNT_EXOBJ_SHIFT 20 67 #define REG_GXS_DB_DISPCNT_EXOBJ_SIZE 2 68 #define REG_GXS_DB_DISPCNT_EXOBJ_MASK 0x00300000 69 70 #define REG_GXS_DB_DISPCNT_MODE_SHIFT 16 71 #define REG_GXS_DB_DISPCNT_MODE_SIZE 1 72 #define REG_GXS_DB_DISPCNT_MODE_MASK 0x00010000 73 74 #define REG_GXS_DB_DISPCNT_OW_SHIFT 15 75 #define REG_GXS_DB_DISPCNT_OW_SIZE 1 76 #define REG_GXS_DB_DISPCNT_OW_MASK 0x00008000 77 78 #define REG_GXS_DB_DISPCNT_W1_SHIFT 14 79 #define REG_GXS_DB_DISPCNT_W1_SIZE 1 80 #define REG_GXS_DB_DISPCNT_W1_MASK 0x00004000 81 82 #define REG_GXS_DB_DISPCNT_W0_SHIFT 13 83 #define REG_GXS_DB_DISPCNT_W0_SIZE 1 84 #define REG_GXS_DB_DISPCNT_W0_MASK 0x00002000 85 86 #define REG_GXS_DB_DISPCNT_DISPLAY_SHIFT 8 87 #define REG_GXS_DB_DISPCNT_DISPLAY_SIZE 5 88 #define REG_GXS_DB_DISPCNT_DISPLAY_MASK 0x00001f00 89 90 #define REG_GXS_DB_DISPCNT_BLANK_SHIFT 7 91 #define REG_GXS_DB_DISPCNT_BLANK_SIZE 1 92 #define REG_GXS_DB_DISPCNT_BLANK_MASK 0x00000080 93 94 #define REG_GXS_DB_DISPCNT_OBJMAP_SHIFT 4 95 #define REG_GXS_DB_DISPCNT_OBJMAP_SIZE 3 96 #define REG_GXS_DB_DISPCNT_OBJMAP_MASK 0x00000070 97 98 #define REG_GXS_DB_DISPCNT_BGMODE_SHIFT 0 99 #define REG_GXS_DB_DISPCNT_BGMODE_SIZE 3 100 #define REG_GXS_DB_DISPCNT_BGMODE_MASK 0x00000007 101 102 #define REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT 4 103 #define REG_GXS_DB_DISPCNT_OBJMAP_CH_SIZE 1 104 #define REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK 0x00000010 105 106 #define REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT 5 107 #define REG_GXS_DB_DISPCNT_OBJMAP_BM_SIZE 2 108 #define REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK 0x00000060 109 110 #define REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT 20 111 #define REG_GXS_DB_DISPCNT_EXOBJ_CH_SIZE 2 112 #define REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK 0x00300000 113 114 #ifndef SDK_ASM 115 #define REG_GXS_DB_DISPCNT_FIELD( o, bg, oh, exobj, mode, ow, w1, w0, display, blank, objmap, bgmode, objmap_ch, objmap_bm, exobj_ch ) \ 116 (u32)( \ 117 ((u32)(o) << REG_GXS_DB_DISPCNT_O_SHIFT) | \ 118 ((u32)(bg) << REG_GXS_DB_DISPCNT_BG_SHIFT) | \ 119 ((u32)(oh) << REG_GXS_DB_DISPCNT_OH_SHIFT) | \ 120 ((u32)(exobj) << REG_GXS_DB_DISPCNT_EXOBJ_SHIFT) | \ 121 ((u32)(mode) << REG_GXS_DB_DISPCNT_MODE_SHIFT) | \ 122 ((u32)(ow) << REG_GXS_DB_DISPCNT_OW_SHIFT) | \ 123 ((u32)(w1) << REG_GXS_DB_DISPCNT_W1_SHIFT) | \ 124 ((u32)(w0) << REG_GXS_DB_DISPCNT_W0_SHIFT) | \ 125 ((u32)(display) << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT) | \ 126 ((u32)(blank) << REG_GXS_DB_DISPCNT_BLANK_SHIFT) | \ 127 ((u32)(objmap) << REG_GXS_DB_DISPCNT_OBJMAP_SHIFT) | \ 128 ((u32)(bgmode) << REG_GXS_DB_DISPCNT_BGMODE_SHIFT) | \ 129 ((u32)(objmap_ch) << REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT) | \ 130 ((u32)(objmap_bm) << REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT) | \ 131 ((u32)(exobj_ch) << REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT)) 132 #endif 133 134 135 /* DB_MASTER_BRIGHT */ 136 137 #define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT 14 138 #define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SIZE 2 139 #define REG_GXS_DB_MASTER_BRIGHT_E_MOD_MASK 0xc000 140 141 #define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT 0 142 #define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SIZE 5 143 #define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_MASK 0x001f 144 145 #ifndef SDK_ASM 146 #define REG_GXS_DB_MASTER_BRIGHT_FIELD( e_mod, e_value ) \ 147 (u16)( \ 148 ((u32)(e_mod) << REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT) | \ 149 ((u32)(e_value) << REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT)) 150 #endif 151 152 153 #ifdef __cplusplus 154 } /* extern "C" */ 155 #endif 156 157 /* TWL_HW_ARM9_IOREG_GXS_H_ */ 158 #endif 159