1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_CP.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_CP_H_ 18 #define NITRO_HW_ARM9_IOREG_CP_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DIVCNT */ 35 36 #define REG_DIVCNT_OFFSET 0x280 37 #define REG_DIVCNT_ADDR (HW_REG_BASE + REG_DIVCNT_OFFSET) 38 #define reg_CP_DIVCNT (*( REGType16v *) REG_DIVCNT_ADDR) 39 40 /* DIV_NUMER */ 41 42 #define REG_DIV_NUMER_OFFSET 0x290 43 #define REG_DIV_NUMER_ADDR (HW_REG_BASE + REG_DIV_NUMER_OFFSET) 44 #define reg_CP_DIV_NUMER (*( REGType64v *) REG_DIV_NUMER_ADDR) 45 46 /* DIV_NUMER_L */ 47 48 #define REG_DIV_NUMER_L_OFFSET 0x290 49 #define REG_DIV_NUMER_L_ADDR (HW_REG_BASE + REG_DIV_NUMER_L_OFFSET) 50 #define reg_CP_DIV_NUMER_L (*( REGType32v *) REG_DIV_NUMER_L_ADDR) 51 52 /* DIV_NUMER_H */ 53 54 #define REG_DIV_NUMER_H_OFFSET 0x294 55 #define REG_DIV_NUMER_H_ADDR (HW_REG_BASE + REG_DIV_NUMER_H_OFFSET) 56 #define reg_CP_DIV_NUMER_H (*( REGType32v *) REG_DIV_NUMER_H_ADDR) 57 58 /* DIV_DENOM */ 59 60 #define REG_DIV_DENOM_OFFSET 0x298 61 #define REG_DIV_DENOM_ADDR (HW_REG_BASE + REG_DIV_DENOM_OFFSET) 62 #define reg_CP_DIV_DENOM (*( REGType64v *) REG_DIV_DENOM_ADDR) 63 64 /* DIV_DENOM_L */ 65 66 #define REG_DIV_DENOM_L_OFFSET 0x298 67 #define REG_DIV_DENOM_L_ADDR (HW_REG_BASE + REG_DIV_DENOM_L_OFFSET) 68 #define reg_CP_DIV_DENOM_L (*( REGType32v *) REG_DIV_DENOM_L_ADDR) 69 70 /* DIV_DENOM_H */ 71 72 #define REG_DIV_DENOM_H_OFFSET 0x29c 73 #define REG_DIV_DENOM_H_ADDR (HW_REG_BASE + REG_DIV_DENOM_H_OFFSET) 74 #define reg_CP_DIV_DENOM_H (*( REGType32v *) REG_DIV_DENOM_H_ADDR) 75 76 /* DIV_RESULT */ 77 78 #define REG_DIV_RESULT_OFFSET 0x2a0 79 #define REG_DIV_RESULT_ADDR (HW_REG_BASE + REG_DIV_RESULT_OFFSET) 80 #define reg_CP_DIV_RESULT (*( REGType64v *) REG_DIV_RESULT_ADDR) 81 82 /* DIV_RESULT_L */ 83 84 #define REG_DIV_RESULT_L_OFFSET 0x2a0 85 #define REG_DIV_RESULT_L_ADDR (HW_REG_BASE + REG_DIV_RESULT_L_OFFSET) 86 #define reg_CP_DIV_RESULT_L (*( REGType32v *) REG_DIV_RESULT_L_ADDR) 87 88 /* DIV_RESULT_H */ 89 90 #define REG_DIV_RESULT_H_OFFSET 0x2a4 91 #define REG_DIV_RESULT_H_ADDR (HW_REG_BASE + REG_DIV_RESULT_H_OFFSET) 92 #define reg_CP_DIV_RESULT_H (*( REGType32v *) REG_DIV_RESULT_H_ADDR) 93 94 /* DIVREM_RESULT */ 95 96 #define REG_DIVREM_RESULT_OFFSET 0x2a8 97 #define REG_DIVREM_RESULT_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_OFFSET) 98 #define reg_CP_DIVREM_RESULT (*( REGType64v *) REG_DIVREM_RESULT_ADDR) 99 100 /* DIVREM_RESULT_L */ 101 102 #define REG_DIVREM_RESULT_L_OFFSET 0x2a8 103 #define REG_DIVREM_RESULT_L_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_L_OFFSET) 104 #define reg_CP_DIVREM_RESULT_L (*( REGType32v *) REG_DIVREM_RESULT_L_ADDR) 105 106 /* DIVREM_RESULT_H */ 107 108 #define REG_DIVREM_RESULT_H_OFFSET 0x2ac 109 #define REG_DIVREM_RESULT_H_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_H_OFFSET) 110 #define reg_CP_DIVREM_RESULT_H (*( REGType32v *) REG_DIVREM_RESULT_H_ADDR) 111 112 /* SQRTCNT */ 113 114 #define REG_SQRTCNT_OFFSET 0x2b0 115 #define REG_SQRTCNT_ADDR (HW_REG_BASE + REG_SQRTCNT_OFFSET) 116 #define reg_CP_SQRTCNT (*( REGType16v *) REG_SQRTCNT_ADDR) 117 118 /* SQRT_RESULT */ 119 120 #define REG_SQRT_RESULT_OFFSET 0x2b4 121 #define REG_SQRT_RESULT_ADDR (HW_REG_BASE + REG_SQRT_RESULT_OFFSET) 122 #define reg_CP_SQRT_RESULT (*( REGType32v *) REG_SQRT_RESULT_ADDR) 123 124 /* SQRT_PARAM */ 125 126 #define REG_SQRT_PARAM_OFFSET 0x2b8 127 #define REG_SQRT_PARAM_ADDR (HW_REG_BASE + REG_SQRT_PARAM_OFFSET) 128 #define reg_CP_SQRT_PARAM (*( REGType64v *) REG_SQRT_PARAM_ADDR) 129 130 /* SQRT_PARAM_L */ 131 132 #define REG_SQRT_PARAM_L_OFFSET 0x2b8 133 #define REG_SQRT_PARAM_L_ADDR (HW_REG_BASE + REG_SQRT_PARAM_L_OFFSET) 134 #define reg_CP_SQRT_PARAM_L (*( REGType32v *) REG_SQRT_PARAM_L_ADDR) 135 136 /* SQRT_PARAM_H */ 137 138 #define REG_SQRT_PARAM_H_OFFSET 0x2bc 139 #define REG_SQRT_PARAM_H_ADDR (HW_REG_BASE + REG_SQRT_PARAM_H_OFFSET) 140 #define reg_CP_SQRT_PARAM_H (*( REGType32v *) REG_SQRT_PARAM_H_ADDR) 141 142 143 /* 144 * Definitions of Register fields 145 */ 146 147 148 /* DIVCNT */ 149 150 #define REG_CP_DIVCNT_BUSY_SHIFT 15 151 #define REG_CP_DIVCNT_BUSY_SIZE 1 152 #define REG_CP_DIVCNT_BUSY_MASK 0x8000 153 154 #define REG_CP_DIVCNT_DIV0_SHIFT 14 155 #define REG_CP_DIVCNT_DIV0_SIZE 1 156 #define REG_CP_DIVCNT_DIV0_MASK 0x4000 157 158 #define REG_CP_DIVCNT_MODE_SHIFT 0 159 #define REG_CP_DIVCNT_MODE_SIZE 2 160 #define REG_CP_DIVCNT_MODE_MASK 0x0003 161 162 #ifndef SDK_ASM 163 #define REG_CP_DIVCNT_FIELD( busy, div0, mode ) \ 164 (u16)( \ 165 ((u32)(busy) << REG_CP_DIVCNT_BUSY_SHIFT) | \ 166 ((u32)(div0) << REG_CP_DIVCNT_DIV0_SHIFT) | \ 167 ((u32)(mode) << REG_CP_DIVCNT_MODE_SHIFT)) 168 #endif 169 170 171 /* DIV_NUMER */ 172 173 /* DIV_NUMER_L */ 174 175 /* DIV_NUMER_H */ 176 177 /* DIV_DENOM */ 178 179 /* DIV_DENOM_L */ 180 181 /* DIV_DENOM_H */ 182 183 /* DIV_RESULT */ 184 185 /* DIV_RESULT_L */ 186 187 /* DIV_RESULT_H */ 188 189 /* DIVREM_RESULT */ 190 191 /* DIVREM_RESULT_L */ 192 193 /* DIVREM_RESULT_H */ 194 195 /* SQRTCNT */ 196 197 #define REG_CP_SQRTCNT_BUSY_SHIFT 15 198 #define REG_CP_SQRTCNT_BUSY_SIZE 1 199 #define REG_CP_SQRTCNT_BUSY_MASK 0x8000 200 201 #define REG_CP_SQRTCNT_MODE_SHIFT 0 202 #define REG_CP_SQRTCNT_MODE_SIZE 1 203 #define REG_CP_SQRTCNT_MODE_MASK 0x0001 204 205 #ifndef SDK_ASM 206 #define REG_CP_SQRTCNT_FIELD( busy, mode ) \ 207 (u16)( \ 208 ((u32)(busy) << REG_CP_SQRTCNT_BUSY_SHIFT) | \ 209 ((u32)(mode) << REG_CP_SQRTCNT_MODE_SHIFT)) 210 #endif 211 212 213 /* SQRT_RESULT */ 214 215 /* SQRT_PARAM */ 216 217 /* SQRT_PARAM_L */ 218 219 /* SQRT_PARAM_H */ 220 221 #ifdef __cplusplus 222 } /* extern "C" */ 223 #endif 224 225 /* NITRO_HW_ARM9_IOREG_CP_H_ */ 226 #endif 227