1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_GX.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_GX_H_ 18 #define TWL_HW_ARM9_IOREG_GX_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DISPCNT */ 35 36 #define REG_DISPCNT_OFFSET 0x000 37 #define REG_DISPCNT_ADDR (HW_REG_BASE + REG_DISPCNT_OFFSET) 38 #define reg_GX_DISPCNT (*( REGType32v *) REG_DISPCNT_ADDR) 39 40 /* DISPSTAT */ 41 42 #define REG_DISPSTAT_OFFSET 0x004 43 #define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET) 44 #define reg_GX_DISPSTAT (*( REGType16v *) REG_DISPSTAT_ADDR) 45 46 /* VCOUNT */ 47 48 #define REG_VCOUNT_OFFSET 0x006 49 #define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) 50 #define reg_GX_VCOUNT (*( REGType16v *) REG_VCOUNT_ADDR) 51 52 /* DISPCAPCNT */ 53 54 #define REG_DISPCAPCNT_OFFSET 0x064 55 #define REG_DISPCAPCNT_ADDR (HW_REG_BASE + REG_DISPCAPCNT_OFFSET) 56 #define reg_GX_DISPCAPCNT (*( REGType32v *) REG_DISPCAPCNT_ADDR) 57 58 /* DISP_MMEM_FIFO */ 59 60 #define REG_DISP_MMEM_FIFO_OFFSET 0x068 61 #define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) 62 #define reg_GX_DISP_MMEM_FIFO (*( REGType32v *) REG_DISP_MMEM_FIFO_ADDR) 63 64 /* DISP_MMEM_FIFO_L */ 65 66 #define REG_DISP_MMEM_FIFO_L_OFFSET 0x068 67 #define REG_DISP_MMEM_FIFO_L_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_L_OFFSET) 68 #define reg_GX_DISP_MMEM_FIFO_L (*( REGType16v *) REG_DISP_MMEM_FIFO_L_ADDR) 69 70 /* DISP_MMEM_FIFO_H */ 71 72 #define REG_DISP_MMEM_FIFO_H_OFFSET 0x06a 73 #define REG_DISP_MMEM_FIFO_H_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_H_OFFSET) 74 #define reg_GX_DISP_MMEM_FIFO_H (*( REGType16v *) REG_DISP_MMEM_FIFO_H_ADDR) 75 76 /* MASTER_BRIGHT */ 77 78 #define REG_MASTER_BRIGHT_OFFSET 0x06c 79 #define REG_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_MASTER_BRIGHT_OFFSET) 80 #define reg_GX_MASTER_BRIGHT (*( REGType16v *) REG_MASTER_BRIGHT_ADDR) 81 82 /* TVOUTCNT */ 83 84 #define REG_TVOUTCNT_OFFSET 0x070 85 #define REG_TVOUTCNT_ADDR (HW_REG_BASE + REG_TVOUTCNT_OFFSET) 86 #define reg_GX_TVOUTCNT (*( REGType16v *) REG_TVOUTCNT_ADDR) 87 88 /* VRAMCNT */ 89 90 #define REG_VRAMCNT_OFFSET 0x240 91 #define REG_VRAMCNT_ADDR (HW_REG_BASE + REG_VRAMCNT_OFFSET) 92 #define reg_GX_VRAMCNT (*( REGType32v *) REG_VRAMCNT_ADDR) 93 94 /* VRAMCNT_A */ 95 96 #define REG_VRAMCNT_A_OFFSET 0x240 97 #define REG_VRAMCNT_A_ADDR (HW_REG_BASE + REG_VRAMCNT_A_OFFSET) 98 #define reg_GX_VRAMCNT_A (*( REGType8v *) REG_VRAMCNT_A_ADDR) 99 100 /* VRAMCNT_B */ 101 102 #define REG_VRAMCNT_B_OFFSET 0x241 103 #define REG_VRAMCNT_B_ADDR (HW_REG_BASE + REG_VRAMCNT_B_OFFSET) 104 #define reg_GX_VRAMCNT_B (*( REGType8v *) REG_VRAMCNT_B_ADDR) 105 106 /* VRAMCNT_C */ 107 108 #define REG_VRAMCNT_C_OFFSET 0x242 109 #define REG_VRAMCNT_C_ADDR (HW_REG_BASE + REG_VRAMCNT_C_OFFSET) 110 #define reg_GX_VRAMCNT_C (*( REGType8v *) REG_VRAMCNT_C_ADDR) 111 112 /* VRAMCNT_D */ 113 114 #define REG_VRAMCNT_D_OFFSET 0x243 115 #define REG_VRAMCNT_D_ADDR (HW_REG_BASE + REG_VRAMCNT_D_OFFSET) 116 #define reg_GX_VRAMCNT_D (*( REGType8v *) REG_VRAMCNT_D_ADDR) 117 118 /* WVRAMCNT */ 119 120 #define REG_WVRAMCNT_OFFSET 0x244 121 #define REG_WVRAMCNT_ADDR (HW_REG_BASE + REG_WVRAMCNT_OFFSET) 122 #define reg_GX_WVRAMCNT (*( REGType32v *) REG_WVRAMCNT_ADDR) 123 124 /* VRAMCNT_E */ 125 126 #define REG_VRAMCNT_E_OFFSET 0x244 127 #define REG_VRAMCNT_E_ADDR (HW_REG_BASE + REG_VRAMCNT_E_OFFSET) 128 #define reg_GX_VRAMCNT_E (*( REGType8v *) REG_VRAMCNT_E_ADDR) 129 130 /* VRAMCNT_F */ 131 132 #define REG_VRAMCNT_F_OFFSET 0x245 133 #define REG_VRAMCNT_F_ADDR (HW_REG_BASE + REG_VRAMCNT_F_OFFSET) 134 #define reg_GX_VRAMCNT_F (*( REGType8v *) REG_VRAMCNT_F_ADDR) 135 136 /* VRAMCNT_G */ 137 138 #define REG_VRAMCNT_G_OFFSET 0x246 139 #define REG_VRAMCNT_G_ADDR (HW_REG_BASE + REG_VRAMCNT_G_OFFSET) 140 #define reg_GX_VRAMCNT_G (*( REGType8v *) REG_VRAMCNT_G_ADDR) 141 142 /* VRAMCNT_WRAM */ 143 144 #define REG_VRAMCNT_WRAM_OFFSET 0x247 145 #define REG_VRAMCNT_WRAM_ADDR (HW_REG_BASE + REG_VRAMCNT_WRAM_OFFSET) 146 #define reg_GX_VRAMCNT_WRAM (*( REGType8v *) REG_VRAMCNT_WRAM_ADDR) 147 148 /* VRAM_HI_CNT */ 149 150 #define REG_VRAM_HI_CNT_OFFSET 0x248 151 #define REG_VRAM_HI_CNT_ADDR (HW_REG_BASE + REG_VRAM_HI_CNT_OFFSET) 152 #define reg_GX_VRAM_HI_CNT (*( REGType16v *) REG_VRAM_HI_CNT_ADDR) 153 154 /* VRAMCNT_H */ 155 156 #define REG_VRAMCNT_H_OFFSET 0x248 157 #define REG_VRAMCNT_H_ADDR (HW_REG_BASE + REG_VRAMCNT_H_OFFSET) 158 #define reg_GX_VRAMCNT_H (*( REGType8v *) REG_VRAMCNT_H_ADDR) 159 160 /* VRAMCNT_I */ 161 162 #define REG_VRAMCNT_I_OFFSET 0x249 163 #define REG_VRAMCNT_I_ADDR (HW_REG_BASE + REG_VRAMCNT_I_OFFSET) 164 #define reg_GX_VRAMCNT_I (*( REGType8v *) REG_VRAMCNT_I_ADDR) 165 166 /* POWCNT */ 167 168 #define REG_POWCNT_OFFSET 0x304 169 #define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) 170 #define reg_GX_POWCNT (*( REGType16v *) REG_POWCNT_ADDR) 171 172 173 /* 174 * Definitions of Register fields 175 */ 176 177 178 /* DISPCNT */ 179 180 #define REG_GX_DISPCNT_O_SHIFT 31 181 #define REG_GX_DISPCNT_O_SIZE 1 182 #define REG_GX_DISPCNT_O_MASK 0x80000000 183 184 #define REG_GX_DISPCNT_BG_SHIFT 30 185 #define REG_GX_DISPCNT_BG_SIZE 1 186 #define REG_GX_DISPCNT_BG_MASK 0x40000000 187 188 #define REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT 27 189 #define REG_GX_DISPCNT_BGSCREENOFFSET_SIZE 3 190 #define REG_GX_DISPCNT_BGSCREENOFFSET_MASK 0x38000000 191 192 #define REG_GX_DISPCNT_BGCHAROFFSET_SHIFT 24 193 #define REG_GX_DISPCNT_BGCHAROFFSET_SIZE 3 194 #define REG_GX_DISPCNT_BGCHAROFFSET_MASK 0x07000000 195 196 #define REG_GX_DISPCNT_OH_SHIFT 23 197 #define REG_GX_DISPCNT_OH_SIZE 1 198 #define REG_GX_DISPCNT_OH_MASK 0x00800000 199 200 #define REG_GX_DISPCNT_EXOBJ_SHIFT 20 201 #define REG_GX_DISPCNT_EXOBJ_SIZE 3 202 #define REG_GX_DISPCNT_EXOBJ_MASK 0x00700000 203 204 #define REG_GX_DISPCNT_VRAM_SHIFT 18 205 #define REG_GX_DISPCNT_VRAM_SIZE 2 206 #define REG_GX_DISPCNT_VRAM_MASK 0x000c0000 207 208 #define REG_GX_DISPCNT_MODE_SHIFT 16 209 #define REG_GX_DISPCNT_MODE_SIZE 2 210 #define REG_GX_DISPCNT_MODE_MASK 0x00030000 211 212 #define REG_GX_DISPCNT_OW_SHIFT 15 213 #define REG_GX_DISPCNT_OW_SIZE 1 214 #define REG_GX_DISPCNT_OW_MASK 0x00008000 215 216 #define REG_GX_DISPCNT_W1_SHIFT 14 217 #define REG_GX_DISPCNT_W1_SIZE 1 218 #define REG_GX_DISPCNT_W1_MASK 0x00004000 219 220 #define REG_GX_DISPCNT_W0_SHIFT 13 221 #define REG_GX_DISPCNT_W0_SIZE 1 222 #define REG_GX_DISPCNT_W0_MASK 0x00002000 223 224 #define REG_GX_DISPCNT_DISPLAY_SHIFT 8 225 #define REG_GX_DISPCNT_DISPLAY_SIZE 5 226 #define REG_GX_DISPCNT_DISPLAY_MASK 0x00001f00 227 228 #define REG_GX_DISPCNT_BLANK_SHIFT 7 229 #define REG_GX_DISPCNT_BLANK_SIZE 1 230 #define REG_GX_DISPCNT_BLANK_MASK 0x00000080 231 232 #define REG_GX_DISPCNT_OBJMAP_SHIFT 4 233 #define REG_GX_DISPCNT_OBJMAP_SIZE 3 234 #define REG_GX_DISPCNT_OBJMAP_MASK 0x00000070 235 236 #define REG_GX_DISPCNT_BG02D3D_SHIFT 3 237 #define REG_GX_DISPCNT_BG02D3D_SIZE 1 238 #define REG_GX_DISPCNT_BG02D3D_MASK 0x00000008 239 240 #define REG_GX_DISPCNT_BGMODE_SHIFT 0 241 #define REG_GX_DISPCNT_BGMODE_SIZE 3 242 #define REG_GX_DISPCNT_BGMODE_MASK 0x00000007 243 244 #define REG_GX_DISPCNT_OBJMAP_CH_SHIFT 4 245 #define REG_GX_DISPCNT_OBJMAP_CH_SIZE 1 246 #define REG_GX_DISPCNT_OBJMAP_CH_MASK 0x00000010 247 248 #define REG_GX_DISPCNT_OBJMAP_BM_SHIFT 5 249 #define REG_GX_DISPCNT_OBJMAP_BM_SIZE 2 250 #define REG_GX_DISPCNT_OBJMAP_BM_MASK 0x00000060 251 252 #define REG_GX_DISPCNT_EXOBJ_CH_SHIFT 20 253 #define REG_GX_DISPCNT_EXOBJ_CH_SIZE 2 254 #define REG_GX_DISPCNT_EXOBJ_CH_MASK 0x00300000 255 256 #define REG_GX_DISPCNT_EXOBJ_BM_SHIFT 22 257 #define REG_GX_DISPCNT_EXOBJ_BM_SIZE 1 258 #define REG_GX_DISPCNT_EXOBJ_BM_MASK 0x00400000 259 260 #ifndef SDK_ASM 261 #define REG_GX_DISPCNT_FIELD( o, bg, bgscreenoffset, bgcharoffset, oh, exobj, vram, mode, ow, w1, w0, display, blank, objmap, bg02d3d, bgmode, objmap_ch, objmap_bm, exobj_ch, exobj_bm ) \ 262 (u32)( \ 263 ((u32)(o) << REG_GX_DISPCNT_O_SHIFT) | \ 264 ((u32)(bg) << REG_GX_DISPCNT_BG_SHIFT) | \ 265 ((u32)(bgscreenoffset) << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT) | \ 266 ((u32)(bgcharoffset) << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT) | \ 267 ((u32)(oh) << REG_GX_DISPCNT_OH_SHIFT) | \ 268 ((u32)(exobj) << REG_GX_DISPCNT_EXOBJ_SHIFT) | \ 269 ((u32)(vram) << REG_GX_DISPCNT_VRAM_SHIFT) | \ 270 ((u32)(mode) << REG_GX_DISPCNT_MODE_SHIFT) | \ 271 ((u32)(ow) << REG_GX_DISPCNT_OW_SHIFT) | \ 272 ((u32)(w1) << REG_GX_DISPCNT_W1_SHIFT) | \ 273 ((u32)(w0) << REG_GX_DISPCNT_W0_SHIFT) | \ 274 ((u32)(display) << REG_GX_DISPCNT_DISPLAY_SHIFT) | \ 275 ((u32)(blank) << REG_GX_DISPCNT_BLANK_SHIFT) | \ 276 ((u32)(objmap) << REG_GX_DISPCNT_OBJMAP_SHIFT) | \ 277 ((u32)(bg02d3d) << REG_GX_DISPCNT_BG02D3D_SHIFT) | \ 278 ((u32)(bgmode) << REG_GX_DISPCNT_BGMODE_SHIFT) | \ 279 ((u32)(objmap_ch) << REG_GX_DISPCNT_OBJMAP_CH_SHIFT) | \ 280 ((u32)(objmap_bm) << REG_GX_DISPCNT_OBJMAP_BM_SHIFT) | \ 281 ((u32)(exobj_ch) << REG_GX_DISPCNT_EXOBJ_CH_SHIFT) | \ 282 ((u32)(exobj_bm) << REG_GX_DISPCNT_EXOBJ_BM_SHIFT)) 283 #endif 284 285 286 /* DISPSTAT */ 287 288 #define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 289 #define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 290 #define REG_GX_DISPSTAT_VCOUNTER_MASK 0xff80 291 292 #define REG_GX_DISPSTAT_INI_SHIFT 6 293 #define REG_GX_DISPSTAT_INI_SIZE 1 294 #define REG_GX_DISPSTAT_INI_MASK 0x0040 295 296 #define REG_GX_DISPSTAT_VQI_SHIFT 5 297 #define REG_GX_DISPSTAT_VQI_SIZE 1 298 #define REG_GX_DISPSTAT_VQI_MASK 0x0020 299 300 #define REG_GX_DISPSTAT_HBI_SHIFT 4 301 #define REG_GX_DISPSTAT_HBI_SIZE 1 302 #define REG_GX_DISPSTAT_HBI_MASK 0x0010 303 304 #define REG_GX_DISPSTAT_VBI_SHIFT 3 305 #define REG_GX_DISPSTAT_VBI_SIZE 1 306 #define REG_GX_DISPSTAT_VBI_MASK 0x0008 307 308 #define REG_GX_DISPSTAT_LYC_SHIFT 2 309 #define REG_GX_DISPSTAT_LYC_SIZE 1 310 #define REG_GX_DISPSTAT_LYC_MASK 0x0004 311 312 #define REG_GX_DISPSTAT_HBLK_SHIFT 1 313 #define REG_GX_DISPSTAT_HBLK_SIZE 1 314 #define REG_GX_DISPSTAT_HBLK_MASK 0x0002 315 316 #define REG_GX_DISPSTAT_VBLK_SHIFT 0 317 #define REG_GX_DISPSTAT_VBLK_SIZE 1 318 #define REG_GX_DISPSTAT_VBLK_MASK 0x0001 319 320 #ifndef SDK_ASM 321 #define REG_GX_DISPSTAT_FIELD( vcounter, ini, vqi, hbi, vbi, lyc, hblk, vblk ) \ 322 (u16)( \ 323 ((u32)(vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT) | \ 324 ((u32)(ini) << REG_GX_DISPSTAT_INI_SHIFT) | \ 325 ((u32)(vqi) << REG_GX_DISPSTAT_VQI_SHIFT) | \ 326 ((u32)(hbi) << REG_GX_DISPSTAT_HBI_SHIFT) | \ 327 ((u32)(vbi) << REG_GX_DISPSTAT_VBI_SHIFT) | \ 328 ((u32)(lyc) << REG_GX_DISPSTAT_LYC_SHIFT) | \ 329 ((u32)(hblk) << REG_GX_DISPSTAT_HBLK_SHIFT) | \ 330 ((u32)(vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) 331 #endif 332 333 334 /* VCOUNT */ 335 336 #define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 337 #define REG_GX_VCOUNT_VCOUNTER_SIZE 9 338 #define REG_GX_VCOUNT_VCOUNTER_MASK 0x01ff 339 340 #ifndef SDK_ASM 341 #define REG_GX_VCOUNT_FIELD( vcounter ) \ 342 (u16)( \ 343 ((u32)(vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) 344 #endif 345 346 347 /* DISPCAPCNT */ 348 349 #define REG_GX_DISPCAPCNT_E_SHIFT 31 350 #define REG_GX_DISPCAPCNT_E_SIZE 1 351 #define REG_GX_DISPCAPCNT_E_MASK 0x80000000 352 353 #define REG_GX_DISPCAPCNT_MOD_SHIFT 29 354 #define REG_GX_DISPCAPCNT_MOD_SIZE 2 355 #define REG_GX_DISPCAPCNT_MOD_MASK 0x60000000 356 357 #define REG_GX_DISPCAPCNT_COFS_SHIFT 26 358 #define REG_GX_DISPCAPCNT_COFS_SIZE 2 359 #define REG_GX_DISPCAPCNT_COFS_MASK 0x0c000000 360 361 #define REG_GX_DISPCAPCNT_SRCB_SHIFT 25 362 #define REG_GX_DISPCAPCNT_SRCB_SIZE 1 363 #define REG_GX_DISPCAPCNT_SRCB_MASK 0x02000000 364 365 #define REG_GX_DISPCAPCNT_SRCA_SHIFT 24 366 #define REG_GX_DISPCAPCNT_SRCA_SIZE 1 367 #define REG_GX_DISPCAPCNT_SRCA_MASK 0x01000000 368 369 #define REG_GX_DISPCAPCNT_WSIZE_SHIFT 20 370 #define REG_GX_DISPCAPCNT_WSIZE_SIZE 2 371 #define REG_GX_DISPCAPCNT_WSIZE_MASK 0x00300000 372 373 #define REG_GX_DISPCAPCNT_WOFS_SHIFT 18 374 #define REG_GX_DISPCAPCNT_WOFS_SIZE 2 375 #define REG_GX_DISPCAPCNT_WOFS_MASK 0x000c0000 376 377 #define REG_GX_DISPCAPCNT_DEST_SHIFT 16 378 #define REG_GX_DISPCAPCNT_DEST_SIZE 2 379 #define REG_GX_DISPCAPCNT_DEST_MASK 0x00030000 380 381 #define REG_GX_DISPCAPCNT_EVB_SHIFT 8 382 #define REG_GX_DISPCAPCNT_EVB_SIZE 5 383 #define REG_GX_DISPCAPCNT_EVB_MASK 0x00001f00 384 385 #define REG_GX_DISPCAPCNT_EVA_SHIFT 0 386 #define REG_GX_DISPCAPCNT_EVA_SIZE 5 387 #define REG_GX_DISPCAPCNT_EVA_MASK 0x0000001f 388 389 #ifndef SDK_ASM 390 #define REG_GX_DISPCAPCNT_FIELD( e, mod, cofs, srcb, srca, wsize, wofs, dest, evb, eva ) \ 391 (u32)( \ 392 ((u32)(e) << REG_GX_DISPCAPCNT_E_SHIFT) | \ 393 ((u32)(mod) << REG_GX_DISPCAPCNT_MOD_SHIFT) | \ 394 ((u32)(cofs) << REG_GX_DISPCAPCNT_COFS_SHIFT) | \ 395 ((u32)(srcb) << REG_GX_DISPCAPCNT_SRCB_SHIFT) | \ 396 ((u32)(srca) << REG_GX_DISPCAPCNT_SRCA_SHIFT) | \ 397 ((u32)(wsize) << REG_GX_DISPCAPCNT_WSIZE_SHIFT) | \ 398 ((u32)(wofs) << REG_GX_DISPCAPCNT_WOFS_SHIFT) | \ 399 ((u32)(dest) << REG_GX_DISPCAPCNT_DEST_SHIFT) | \ 400 ((u32)(evb) << REG_GX_DISPCAPCNT_EVB_SHIFT) | \ 401 ((u32)(eva) << REG_GX_DISPCAPCNT_EVA_SHIFT)) 402 #endif 403 404 405 /* DISP_MMEM_FIFO */ 406 407 #define REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT 0 408 #define REG_GX_DISP_MMEM_FIFO_EVEN_SIZE 16 409 #define REG_GX_DISP_MMEM_FIFO_EVEN_MASK 0x0000ffff 410 411 #define REG_GX_DISP_MMEM_FIFO_ODD_SHIFT 16 412 #define REG_GX_DISP_MMEM_FIFO_ODD_SIZE 16 413 #define REG_GX_DISP_MMEM_FIFO_ODD_MASK 0xffff0000 414 415 #ifndef SDK_ASM 416 #define REG_GX_DISP_MMEM_FIFO_FIELD( even, odd ) \ 417 (u32)( \ 418 ((u32)(even) << REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT) | \ 419 ((u32)(odd) << REG_GX_DISP_MMEM_FIFO_ODD_SHIFT)) 420 #endif 421 422 423 /* DISP_MMEM_FIFO_L */ 424 425 #define REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT 0 426 #define REG_GX_DISP_MMEM_FIFO_L_RED_SIZE 5 427 #define REG_GX_DISP_MMEM_FIFO_L_RED_MASK 0x001f 428 429 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT 5 430 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_SIZE 5 431 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_MASK 0x03e0 432 433 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT 10 434 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_SIZE 5 435 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_MASK 0x7c00 436 437 #ifndef SDK_ASM 438 #define REG_GX_DISP_MMEM_FIFO_L_FIELD( red, green, blue ) \ 439 (u16)( \ 440 ((u32)(red) << REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT) | \ 441 ((u32)(green) << REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT) | \ 442 ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT)) 443 #endif 444 445 446 /* DISP_MMEM_FIFO_H */ 447 448 #define REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT 0 449 #define REG_GX_DISP_MMEM_FIFO_H_RED_SIZE 5 450 #define REG_GX_DISP_MMEM_FIFO_H_RED_MASK 0x001f 451 452 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT 5 453 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_SIZE 5 454 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_MASK 0x03e0 455 456 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT 10 457 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_SIZE 5 458 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_MASK 0x7c00 459 460 #ifndef SDK_ASM 461 #define REG_GX_DISP_MMEM_FIFO_H_FIELD( red, green, blue ) \ 462 (u16)( \ 463 ((u32)(red) << REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT) | \ 464 ((u32)(green) << REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT) | \ 465 ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT)) 466 #endif 467 468 469 /* MASTER_BRIGHT */ 470 471 #define REG_GX_MASTER_BRIGHT_E_MOD_SHIFT 14 472 #define REG_GX_MASTER_BRIGHT_E_MOD_SIZE 2 473 #define REG_GX_MASTER_BRIGHT_E_MOD_MASK 0xc000 474 475 #define REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT 0 476 #define REG_GX_MASTER_BRIGHT_E_VALUE_SIZE 5 477 #define REG_GX_MASTER_BRIGHT_E_VALUE_MASK 0x001f 478 479 #ifndef SDK_ASM 480 #define REG_GX_MASTER_BRIGHT_FIELD( e_mod, e_value ) \ 481 (u16)( \ 482 ((u32)(e_mod) << REG_GX_MASTER_BRIGHT_E_MOD_SHIFT) | \ 483 ((u32)(e_value) << REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT)) 484 #endif 485 486 487 /* TVOUTCNT */ 488 489 #define REG_GX_TVOUTCNT_COMMAND3_SHIFT 8 490 #define REG_GX_TVOUTCNT_COMMAND3_SIZE 4 491 #define REG_GX_TVOUTCNT_COMMAND3_MASK 0x0f00 492 493 #define REG_GX_TVOUTCNT_COMMAND2_SHIFT 4 494 #define REG_GX_TVOUTCNT_COMMAND2_SIZE 4 495 #define REG_GX_TVOUTCNT_COMMAND2_MASK 0x00f0 496 497 #define REG_GX_TVOUTCNT_COMMAND_SHIFT 0 498 #define REG_GX_TVOUTCNT_COMMAND_SIZE 4 499 #define REG_GX_TVOUTCNT_COMMAND_MASK 0x000f 500 501 #ifndef SDK_ASM 502 #define REG_GX_TVOUTCNT_FIELD( command3, command2, command ) \ 503 (u16)( \ 504 ((u32)(command3) << REG_GX_TVOUTCNT_COMMAND3_SHIFT) | \ 505 ((u32)(command2) << REG_GX_TVOUTCNT_COMMAND2_SHIFT) | \ 506 ((u32)(command) << REG_GX_TVOUTCNT_COMMAND_SHIFT)) 507 #endif 508 509 510 /* VRAMCNT */ 511 512 /* VRAMCNT_A */ 513 514 #define REG_GX_VRAMCNT_A_E_SHIFT 7 515 #define REG_GX_VRAMCNT_A_E_SIZE 1 516 #define REG_GX_VRAMCNT_A_E_MASK 0x80 517 518 #define REG_GX_VRAMCNT_A_OFS_SHIFT 3 519 #define REG_GX_VRAMCNT_A_OFS_SIZE 2 520 #define REG_GX_VRAMCNT_A_OFS_MASK 0x18 521 522 #define REG_GX_VRAMCNT_A_MST_SHIFT 0 523 #define REG_GX_VRAMCNT_A_MST_SIZE 2 524 #define REG_GX_VRAMCNT_A_MST_MASK 0x03 525 526 #ifndef SDK_ASM 527 #define REG_GX_VRAMCNT_A_FIELD( e, ofs, mst ) \ 528 (u8)( \ 529 ((u32)(e) << REG_GX_VRAMCNT_A_E_SHIFT) | \ 530 ((u32)(ofs) << REG_GX_VRAMCNT_A_OFS_SHIFT) | \ 531 ((u32)(mst) << REG_GX_VRAMCNT_A_MST_SHIFT)) 532 #endif 533 534 535 /* VRAMCNT_B */ 536 537 #define REG_GX_VRAMCNT_B_E_SHIFT 7 538 #define REG_GX_VRAMCNT_B_E_SIZE 1 539 #define REG_GX_VRAMCNT_B_E_MASK 0x80 540 541 #define REG_GX_VRAMCNT_B_OFS_SHIFT 3 542 #define REG_GX_VRAMCNT_B_OFS_SIZE 2 543 #define REG_GX_VRAMCNT_B_OFS_MASK 0x18 544 545 #define REG_GX_VRAMCNT_B_MST_SHIFT 0 546 #define REG_GX_VRAMCNT_B_MST_SIZE 2 547 #define REG_GX_VRAMCNT_B_MST_MASK 0x03 548 549 #ifndef SDK_ASM 550 #define REG_GX_VRAMCNT_B_FIELD( e, ofs, mst ) \ 551 (u8)( \ 552 ((u32)(e) << REG_GX_VRAMCNT_B_E_SHIFT) | \ 553 ((u32)(ofs) << REG_GX_VRAMCNT_B_OFS_SHIFT) | \ 554 ((u32)(mst) << REG_GX_VRAMCNT_B_MST_SHIFT)) 555 #endif 556 557 558 /* VRAMCNT_C */ 559 560 #define REG_GX_VRAMCNT_C_E_SHIFT 7 561 #define REG_GX_VRAMCNT_C_E_SIZE 1 562 #define REG_GX_VRAMCNT_C_E_MASK 0x80 563 564 #define REG_GX_VRAMCNT_C_OFS_SHIFT 3 565 #define REG_GX_VRAMCNT_C_OFS_SIZE 2 566 #define REG_GX_VRAMCNT_C_OFS_MASK 0x18 567 568 #define REG_GX_VRAMCNT_C_MST_SHIFT 0 569 #define REG_GX_VRAMCNT_C_MST_SIZE 3 570 #define REG_GX_VRAMCNT_C_MST_MASK 0x07 571 572 #ifndef SDK_ASM 573 #define REG_GX_VRAMCNT_C_FIELD( e, ofs, mst ) \ 574 (u8)( \ 575 ((u32)(e) << REG_GX_VRAMCNT_C_E_SHIFT) | \ 576 ((u32)(ofs) << REG_GX_VRAMCNT_C_OFS_SHIFT) | \ 577 ((u32)(mst) << REG_GX_VRAMCNT_C_MST_SHIFT)) 578 #endif 579 580 581 /* VRAMCNT_D */ 582 583 #define REG_GX_VRAMCNT_D_E_SHIFT 7 584 #define REG_GX_VRAMCNT_D_E_SIZE 1 585 #define REG_GX_VRAMCNT_D_E_MASK 0x80 586 587 #define REG_GX_VRAMCNT_D_OFS_SHIFT 3 588 #define REG_GX_VRAMCNT_D_OFS_SIZE 2 589 #define REG_GX_VRAMCNT_D_OFS_MASK 0x18 590 591 #define REG_GX_VRAMCNT_D_MST_SHIFT 0 592 #define REG_GX_VRAMCNT_D_MST_SIZE 3 593 #define REG_GX_VRAMCNT_D_MST_MASK 0x07 594 595 #ifndef SDK_ASM 596 #define REG_GX_VRAMCNT_D_FIELD( e, ofs, mst ) \ 597 (u8)( \ 598 ((u32)(e) << REG_GX_VRAMCNT_D_E_SHIFT) | \ 599 ((u32)(ofs) << REG_GX_VRAMCNT_D_OFS_SHIFT) | \ 600 ((u32)(mst) << REG_GX_VRAMCNT_D_MST_SHIFT)) 601 #endif 602 603 604 /* WVRAMCNT */ 605 606 /* VRAMCNT_E */ 607 608 #define REG_GX_VRAMCNT_E_E_SHIFT 7 609 #define REG_GX_VRAMCNT_E_E_SIZE 1 610 #define REG_GX_VRAMCNT_E_E_MASK 0x80 611 612 #define REG_GX_VRAMCNT_E_MST_SHIFT 0 613 #define REG_GX_VRAMCNT_E_MST_SIZE 3 614 #define REG_GX_VRAMCNT_E_MST_MASK 0x07 615 616 #ifndef SDK_ASM 617 #define REG_GX_VRAMCNT_E_FIELD( e, mst ) \ 618 (u8)( \ 619 ((u32)(e) << REG_GX_VRAMCNT_E_E_SHIFT) | \ 620 ((u32)(mst) << REG_GX_VRAMCNT_E_MST_SHIFT)) 621 #endif 622 623 624 /* VRAMCNT_F */ 625 626 #define REG_GX_VRAMCNT_F_E_SHIFT 7 627 #define REG_GX_VRAMCNT_F_E_SIZE 1 628 #define REG_GX_VRAMCNT_F_E_MASK 0x80 629 630 #define REG_GX_VRAMCNT_F_OFS_SHIFT 3 631 #define REG_GX_VRAMCNT_F_OFS_SIZE 2 632 #define REG_GX_VRAMCNT_F_OFS_MASK 0x18 633 634 #define REG_GX_VRAMCNT_F_MST_SHIFT 0 635 #define REG_GX_VRAMCNT_F_MST_SIZE 3 636 #define REG_GX_VRAMCNT_F_MST_MASK 0x07 637 638 #ifndef SDK_ASM 639 #define REG_GX_VRAMCNT_F_FIELD( e, ofs, mst ) \ 640 (u8)( \ 641 ((u32)(e) << REG_GX_VRAMCNT_F_E_SHIFT) | \ 642 ((u32)(ofs) << REG_GX_VRAMCNT_F_OFS_SHIFT) | \ 643 ((u32)(mst) << REG_GX_VRAMCNT_F_MST_SHIFT)) 644 #endif 645 646 647 /* VRAMCNT_G */ 648 649 #define REG_GX_VRAMCNT_G_E_SHIFT 7 650 #define REG_GX_VRAMCNT_G_E_SIZE 1 651 #define REG_GX_VRAMCNT_G_E_MASK 0x80 652 653 #define REG_GX_VRAMCNT_G_OFS_SHIFT 3 654 #define REG_GX_VRAMCNT_G_OFS_SIZE 2 655 #define REG_GX_VRAMCNT_G_OFS_MASK 0x18 656 657 #define REG_GX_VRAMCNT_G_MST_SHIFT 0 658 #define REG_GX_VRAMCNT_G_MST_SIZE 3 659 #define REG_GX_VRAMCNT_G_MST_MASK 0x07 660 661 #ifndef SDK_ASM 662 #define REG_GX_VRAMCNT_G_FIELD( e, ofs, mst ) \ 663 (u8)( \ 664 ((u32)(e) << REG_GX_VRAMCNT_G_E_SHIFT) | \ 665 ((u32)(ofs) << REG_GX_VRAMCNT_G_OFS_SHIFT) | \ 666 ((u32)(mst) << REG_GX_VRAMCNT_G_MST_SHIFT)) 667 #endif 668 669 670 /* VRAMCNT_WRAM */ 671 672 #define REG_GX_VRAMCNT_WRAM_BANK_SHIFT 0 673 #define REG_GX_VRAMCNT_WRAM_BANK_SIZE 2 674 #define REG_GX_VRAMCNT_WRAM_BANK_MASK 0x03 675 676 #ifndef SDK_ASM 677 #define REG_GX_VRAMCNT_WRAM_FIELD( bank ) \ 678 (u8)( \ 679 ((u32)(bank) << REG_GX_VRAMCNT_WRAM_BANK_SHIFT)) 680 #endif 681 682 683 /* VRAM_HI_CNT */ 684 685 /* VRAMCNT_H */ 686 687 #define REG_GX_VRAMCNT_H_E_SHIFT 7 688 #define REG_GX_VRAMCNT_H_E_SIZE 1 689 #define REG_GX_VRAMCNT_H_E_MASK 0x80 690 691 #define REG_GX_VRAMCNT_H_MST_SHIFT 0 692 #define REG_GX_VRAMCNT_H_MST_SIZE 2 693 #define REG_GX_VRAMCNT_H_MST_MASK 0x03 694 695 #ifndef SDK_ASM 696 #define REG_GX_VRAMCNT_H_FIELD( e, mst ) \ 697 (u8)( \ 698 ((u32)(e) << REG_GX_VRAMCNT_H_E_SHIFT) | \ 699 ((u32)(mst) << REG_GX_VRAMCNT_H_MST_SHIFT)) 700 #endif 701 702 703 /* VRAMCNT_I */ 704 705 #define REG_GX_VRAMCNT_I_E_SHIFT 7 706 #define REG_GX_VRAMCNT_I_E_SIZE 1 707 #define REG_GX_VRAMCNT_I_E_MASK 0x80 708 709 #define REG_GX_VRAMCNT_I_MST_SHIFT 0 710 #define REG_GX_VRAMCNT_I_MST_SIZE 2 711 #define REG_GX_VRAMCNT_I_MST_MASK 0x03 712 713 #ifndef SDK_ASM 714 #define REG_GX_VRAMCNT_I_FIELD( e, mst ) \ 715 (u8)( \ 716 ((u32)(e) << REG_GX_VRAMCNT_I_E_SHIFT) | \ 717 ((u32)(mst) << REG_GX_VRAMCNT_I_MST_SHIFT)) 718 #endif 719 720 721 /* POWCNT */ 722 723 #define REG_GX_POWCNT_GE_SHIFT 3 724 #define REG_GX_POWCNT_GE_SIZE 1 725 #define REG_GX_POWCNT_GE_MASK 0x0008 726 727 #define REG_GX_POWCNT_RE_SHIFT 2 728 #define REG_GX_POWCNT_RE_SIZE 1 729 #define REG_GX_POWCNT_RE_MASK 0x0004 730 731 #define REG_GX_POWCNT_E2DG_SHIFT 1 732 #define REG_GX_POWCNT_E2DG_SIZE 1 733 #define REG_GX_POWCNT_E2DG_MASK 0x0002 734 735 #define REG_GX_POWCNT_LCD_SHIFT 0 736 #define REG_GX_POWCNT_LCD_SIZE 1 737 #define REG_GX_POWCNT_LCD_MASK 0x0001 738 739 #define REG_GX_POWCNT_LCDB_SHIFT 8 740 #define REG_GX_POWCNT_LCDB_SIZE 1 741 #define REG_GX_POWCNT_LCDB_MASK 0x0100 742 743 #define REG_GX_POWCNT_E2DGB_SHIFT 9 744 #define REG_GX_POWCNT_E2DGB_SIZE 1 745 #define REG_GX_POWCNT_E2DGB_MASK 0x0200 746 747 #define REG_GX_POWCNT_DSEL_SHIFT 15 748 #define REG_GX_POWCNT_DSEL_SIZE 1 749 #define REG_GX_POWCNT_DSEL_MASK 0x8000 750 751 #ifndef SDK_ASM 752 #define REG_GX_POWCNT_FIELD( ge, re, e2dg, lcd, lcdb, e2dgb, dsel ) \ 753 (u16)( \ 754 ((u32)(ge) << REG_GX_POWCNT_GE_SHIFT) | \ 755 ((u32)(re) << REG_GX_POWCNT_RE_SHIFT) | \ 756 ((u32)(e2dg) << REG_GX_POWCNT_E2DG_SHIFT) | \ 757 ((u32)(lcd) << REG_GX_POWCNT_LCD_SHIFT) | \ 758 ((u32)(lcdb) << REG_GX_POWCNT_LCDB_SHIFT) | \ 759 ((u32)(e2dgb) << REG_GX_POWCNT_E2DGB_SHIFT) | \ 760 ((u32)(dsel) << REG_GX_POWCNT_DSEL_SHIFT)) 761 #endif 762 763 764 #ifdef __cplusplus 765 } /* extern "C" */ 766 #endif 767 768 /* TWL_HW_ARM9_IOREG_GX_H_ */ 769 #endif 770