1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_G2.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_G2_H_ 18 #define TWL_HW_ARM9_IOREG_G2_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* BG0CNT */ 35 36 #define REG_BG0CNT_OFFSET 0x008 37 #define REG_BG0CNT_ADDR (HW_REG_BASE + REG_BG0CNT_OFFSET) 38 #define reg_G2_BG0CNT (*( REGType16v *) REG_BG0CNT_ADDR) 39 40 /* BG1CNT */ 41 42 #define REG_BG1CNT_OFFSET 0x00a 43 #define REG_BG1CNT_ADDR (HW_REG_BASE + REG_BG1CNT_OFFSET) 44 #define reg_G2_BG1CNT (*( REGType16v *) REG_BG1CNT_ADDR) 45 46 /* BG2CNT */ 47 48 #define REG_BG2CNT_OFFSET 0x00c 49 #define REG_BG2CNT_ADDR (HW_REG_BASE + REG_BG2CNT_OFFSET) 50 #define reg_G2_BG2CNT (*( REGType16v *) REG_BG2CNT_ADDR) 51 52 /* BG3CNT */ 53 54 #define REG_BG3CNT_OFFSET 0x00e 55 #define REG_BG3CNT_ADDR (HW_REG_BASE + REG_BG3CNT_OFFSET) 56 #define reg_G2_BG3CNT (*( REGType16v *) REG_BG3CNT_ADDR) 57 58 /* BG0OFS */ 59 60 #define REG_BG0OFS_OFFSET 0x010 61 #define REG_BG0OFS_ADDR (HW_REG_BASE + REG_BG0OFS_OFFSET) 62 #define reg_G2_BG0OFS (*( REGType32v *) REG_BG0OFS_ADDR) 63 64 /* BG0HOFS */ 65 66 #define REG_BG0HOFS_OFFSET 0x010 67 #define REG_BG0HOFS_ADDR (HW_REG_BASE + REG_BG0HOFS_OFFSET) 68 #define reg_G2_BG0HOFS (*( REGType16v *) REG_BG0HOFS_ADDR) 69 70 /* BG0VOFS */ 71 72 #define REG_BG0VOFS_OFFSET 0x012 73 #define REG_BG0VOFS_ADDR (HW_REG_BASE + REG_BG0VOFS_OFFSET) 74 #define reg_G2_BG0VOFS (*( REGType16v *) REG_BG0VOFS_ADDR) 75 76 /* BG1OFS */ 77 78 #define REG_BG1OFS_OFFSET 0x014 79 #define REG_BG1OFS_ADDR (HW_REG_BASE + REG_BG1OFS_OFFSET) 80 #define reg_G2_BG1OFS (*( REGType32v *) REG_BG1OFS_ADDR) 81 82 /* BG1HOFS */ 83 84 #define REG_BG1HOFS_OFFSET 0x014 85 #define REG_BG1HOFS_ADDR (HW_REG_BASE + REG_BG1HOFS_OFFSET) 86 #define reg_G2_BG1HOFS (*( REGType16v *) REG_BG1HOFS_ADDR) 87 88 /* BG1VOFS */ 89 90 #define REG_BG1VOFS_OFFSET 0x016 91 #define REG_BG1VOFS_ADDR (HW_REG_BASE + REG_BG1VOFS_OFFSET) 92 #define reg_G2_BG1VOFS (*( REGType16v *) REG_BG1VOFS_ADDR) 93 94 /* BG2OFS */ 95 96 #define REG_BG2OFS_OFFSET 0x018 97 #define REG_BG2OFS_ADDR (HW_REG_BASE + REG_BG2OFS_OFFSET) 98 #define reg_G2_BG2OFS (*( REGType32v *) REG_BG2OFS_ADDR) 99 100 /* BG2HOFS */ 101 102 #define REG_BG2HOFS_OFFSET 0x018 103 #define REG_BG2HOFS_ADDR (HW_REG_BASE + REG_BG2HOFS_OFFSET) 104 #define reg_G2_BG2HOFS (*( REGType16v *) REG_BG2HOFS_ADDR) 105 106 /* BG2VOFS */ 107 108 #define REG_BG2VOFS_OFFSET 0x01a 109 #define REG_BG2VOFS_ADDR (HW_REG_BASE + REG_BG2VOFS_OFFSET) 110 #define reg_G2_BG2VOFS (*( REGType16v *) REG_BG2VOFS_ADDR) 111 112 /* BG3OFS */ 113 114 #define REG_BG3OFS_OFFSET 0x01c 115 #define REG_BG3OFS_ADDR (HW_REG_BASE + REG_BG3OFS_OFFSET) 116 #define reg_G2_BG3OFS (*( REGType32v *) REG_BG3OFS_ADDR) 117 118 /* BG3HOFS */ 119 120 #define REG_BG3HOFS_OFFSET 0x01c 121 #define REG_BG3HOFS_ADDR (HW_REG_BASE + REG_BG3HOFS_OFFSET) 122 #define reg_G2_BG3HOFS (*( REGType16v *) REG_BG3HOFS_ADDR) 123 124 /* BG3VOFS */ 125 126 #define REG_BG3VOFS_OFFSET 0x01e 127 #define REG_BG3VOFS_ADDR (HW_REG_BASE + REG_BG3VOFS_OFFSET) 128 #define reg_G2_BG3VOFS (*( REGType16v *) REG_BG3VOFS_ADDR) 129 130 /* BG2PA */ 131 132 #define REG_BG2PA_OFFSET 0x020 133 #define REG_BG2PA_ADDR (HW_REG_BASE + REG_BG2PA_OFFSET) 134 #define reg_G2_BG2PA (*( REGType16v *) REG_BG2PA_ADDR) 135 136 /* BG2PB */ 137 138 #define REG_BG2PB_OFFSET 0x022 139 #define REG_BG2PB_ADDR (HW_REG_BASE + REG_BG2PB_OFFSET) 140 #define reg_G2_BG2PB (*( REGType16v *) REG_BG2PB_ADDR) 141 142 /* BG2PC */ 143 144 #define REG_BG2PC_OFFSET 0x024 145 #define REG_BG2PC_ADDR (HW_REG_BASE + REG_BG2PC_OFFSET) 146 #define reg_G2_BG2PC (*( REGType16v *) REG_BG2PC_ADDR) 147 148 /* BG2PD */ 149 150 #define REG_BG2PD_OFFSET 0x026 151 #define REG_BG2PD_ADDR (HW_REG_BASE + REG_BG2PD_OFFSET) 152 #define reg_G2_BG2PD (*( REGType16v *) REG_BG2PD_ADDR) 153 154 /* BG2X */ 155 156 #define REG_BG2X_OFFSET 0x028 157 #define REG_BG2X_ADDR (HW_REG_BASE + REG_BG2X_OFFSET) 158 #define reg_G2_BG2X (*( REGType32v *) REG_BG2X_ADDR) 159 160 /* BG2Y */ 161 162 #define REG_BG2Y_OFFSET 0x02c 163 #define REG_BG2Y_ADDR (HW_REG_BASE + REG_BG2Y_OFFSET) 164 #define reg_G2_BG2Y (*( REGType32v *) REG_BG2Y_ADDR) 165 166 /* BG3PA */ 167 168 #define REG_BG3PA_OFFSET 0x030 169 #define REG_BG3PA_ADDR (HW_REG_BASE + REG_BG3PA_OFFSET) 170 #define reg_G2_BG3PA (*( REGType16v *) REG_BG3PA_ADDR) 171 172 /* BG3PB */ 173 174 #define REG_BG3PB_OFFSET 0x032 175 #define REG_BG3PB_ADDR (HW_REG_BASE + REG_BG3PB_OFFSET) 176 #define reg_G2_BG3PB (*( REGType16v *) REG_BG3PB_ADDR) 177 178 /* BG3PC */ 179 180 #define REG_BG3PC_OFFSET 0x034 181 #define REG_BG3PC_ADDR (HW_REG_BASE + REG_BG3PC_OFFSET) 182 #define reg_G2_BG3PC (*( REGType16v *) REG_BG3PC_ADDR) 183 184 /* BG3PD */ 185 186 #define REG_BG3PD_OFFSET 0x036 187 #define REG_BG3PD_ADDR (HW_REG_BASE + REG_BG3PD_OFFSET) 188 #define reg_G2_BG3PD (*( REGType16v *) REG_BG3PD_ADDR) 189 190 /* BG3X */ 191 192 #define REG_BG3X_OFFSET 0x038 193 #define REG_BG3X_ADDR (HW_REG_BASE + REG_BG3X_OFFSET) 194 #define reg_G2_BG3X (*( REGType32v *) REG_BG3X_ADDR) 195 196 /* BG3Y */ 197 198 #define REG_BG3Y_OFFSET 0x03c 199 #define REG_BG3Y_ADDR (HW_REG_BASE + REG_BG3Y_OFFSET) 200 #define reg_G2_BG3Y (*( REGType32v *) REG_BG3Y_ADDR) 201 202 /* WIN0H */ 203 204 #define REG_WIN0H_OFFSET 0x040 205 #define REG_WIN0H_ADDR (HW_REG_BASE + REG_WIN0H_OFFSET) 206 #define reg_G2_WIN0H (*( REGType16v *) REG_WIN0H_ADDR) 207 208 /* WIN1H */ 209 210 #define REG_WIN1H_OFFSET 0x042 211 #define REG_WIN1H_ADDR (HW_REG_BASE + REG_WIN1H_OFFSET) 212 #define reg_G2_WIN1H (*( REGType16v *) REG_WIN1H_ADDR) 213 214 /* WIN0V */ 215 216 #define REG_WIN0V_OFFSET 0x044 217 #define REG_WIN0V_ADDR (HW_REG_BASE + REG_WIN0V_OFFSET) 218 #define reg_G2_WIN0V (*( REGType16v *) REG_WIN0V_ADDR) 219 220 /* WIN1V */ 221 222 #define REG_WIN1V_OFFSET 0x046 223 #define REG_WIN1V_ADDR (HW_REG_BASE + REG_WIN1V_OFFSET) 224 #define reg_G2_WIN1V (*( REGType16v *) REG_WIN1V_ADDR) 225 226 /* WININ */ 227 228 #define REG_WININ_OFFSET 0x048 229 #define REG_WININ_ADDR (HW_REG_BASE + REG_WININ_OFFSET) 230 #define reg_G2_WININ (*( REGType16v *) REG_WININ_ADDR) 231 232 /* WINOUT */ 233 234 #define REG_WINOUT_OFFSET 0x04a 235 #define REG_WINOUT_ADDR (HW_REG_BASE + REG_WINOUT_OFFSET) 236 #define reg_G2_WINOUT (*( REGType16v *) REG_WINOUT_ADDR) 237 238 /* MOSAIC */ 239 240 #define REG_MOSAIC_OFFSET 0x04c 241 #define REG_MOSAIC_ADDR (HW_REG_BASE + REG_MOSAIC_OFFSET) 242 #define reg_G2_MOSAIC (*( REGType16v *) REG_MOSAIC_ADDR) 243 244 /* BLDCNT */ 245 246 #define REG_BLDCNT_OFFSET 0x050 247 #define REG_BLDCNT_ADDR (HW_REG_BASE + REG_BLDCNT_OFFSET) 248 #define reg_G2_BLDCNT (*( REGType16v *) REG_BLDCNT_ADDR) 249 250 /* BLDALPHA */ 251 252 #define REG_BLDALPHA_OFFSET 0x052 253 #define REG_BLDALPHA_ADDR (HW_REG_BASE + REG_BLDALPHA_OFFSET) 254 #define reg_G2_BLDALPHA (*( REGType16v *) REG_BLDALPHA_ADDR) 255 256 /* BLDY */ 257 258 #define REG_BLDY_OFFSET 0x054 259 #define REG_BLDY_ADDR (HW_REG_BASE + REG_BLDY_OFFSET) 260 #define reg_G2_BLDY (*( REGType16v *) REG_BLDY_ADDR) 261 262 263 /* 264 * Definitions of Register fields 265 */ 266 267 268 /* BG0CNT */ 269 270 #define REG_G2_BG0CNT_SCREENSIZE_SHIFT 14 271 #define REG_G2_BG0CNT_SCREENSIZE_SIZE 2 272 #define REG_G2_BG0CNT_SCREENSIZE_MASK 0xc000 273 274 #define REG_G2_BG0CNT_BGPLTTSLOT_SHIFT 13 275 #define REG_G2_BG0CNT_BGPLTTSLOT_SIZE 1 276 #define REG_G2_BG0CNT_BGPLTTSLOT_MASK 0x2000 277 278 #define REG_G2_BG0CNT_SCREENBASE_SHIFT 8 279 #define REG_G2_BG0CNT_SCREENBASE_SIZE 5 280 #define REG_G2_BG0CNT_SCREENBASE_MASK 0x1f00 281 282 #define REG_G2_BG0CNT_COLORMODE_SHIFT 7 283 #define REG_G2_BG0CNT_COLORMODE_SIZE 1 284 #define REG_G2_BG0CNT_COLORMODE_MASK 0x0080 285 286 #define REG_G2_BG0CNT_MOSAIC_SHIFT 6 287 #define REG_G2_BG0CNT_MOSAIC_SIZE 1 288 #define REG_G2_BG0CNT_MOSAIC_MASK 0x0040 289 290 #define REG_G2_BG0CNT_CHARBASE_SHIFT 2 291 #define REG_G2_BG0CNT_CHARBASE_SIZE 4 292 #define REG_G2_BG0CNT_CHARBASE_MASK 0x003c 293 294 #define REG_G2_BG0CNT_PRIORITY_SHIFT 0 295 #define REG_G2_BG0CNT_PRIORITY_SIZE 2 296 #define REG_G2_BG0CNT_PRIORITY_MASK 0x0003 297 298 #ifndef SDK_ASM 299 #define REG_G2_BG0CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ 300 (u16)( \ 301 ((u32)(screensize) << REG_G2_BG0CNT_SCREENSIZE_SHIFT) | \ 302 ((u32)(bgplttslot) << REG_G2_BG0CNT_BGPLTTSLOT_SHIFT) | \ 303 ((u32)(screenbase) << REG_G2_BG0CNT_SCREENBASE_SHIFT) | \ 304 ((u32)(colormode) << REG_G2_BG0CNT_COLORMODE_SHIFT) | \ 305 ((u32)(mosaic) << REG_G2_BG0CNT_MOSAIC_SHIFT) | \ 306 ((u32)(charbase) << REG_G2_BG0CNT_CHARBASE_SHIFT) | \ 307 ((u32)(priority) << REG_G2_BG0CNT_PRIORITY_SHIFT)) 308 #endif 309 310 311 /* BG1CNT */ 312 313 #define REG_G2_BG1CNT_SCREENSIZE_SHIFT 14 314 #define REG_G2_BG1CNT_SCREENSIZE_SIZE 2 315 #define REG_G2_BG1CNT_SCREENSIZE_MASK 0xc000 316 317 #define REG_G2_BG1CNT_BGPLTTSLOT_SHIFT 13 318 #define REG_G2_BG1CNT_BGPLTTSLOT_SIZE 1 319 #define REG_G2_BG1CNT_BGPLTTSLOT_MASK 0x2000 320 321 #define REG_G2_BG1CNT_SCREENBASE_SHIFT 8 322 #define REG_G2_BG1CNT_SCREENBASE_SIZE 5 323 #define REG_G2_BG1CNT_SCREENBASE_MASK 0x1f00 324 325 #define REG_G2_BG1CNT_COLORMODE_SHIFT 7 326 #define REG_G2_BG1CNT_COLORMODE_SIZE 1 327 #define REG_G2_BG1CNT_COLORMODE_MASK 0x0080 328 329 #define REG_G2_BG1CNT_MOSAIC_SHIFT 6 330 #define REG_G2_BG1CNT_MOSAIC_SIZE 1 331 #define REG_G2_BG1CNT_MOSAIC_MASK 0x0040 332 333 #define REG_G2_BG1CNT_CHARBASE_SHIFT 2 334 #define REG_G2_BG1CNT_CHARBASE_SIZE 4 335 #define REG_G2_BG1CNT_CHARBASE_MASK 0x003c 336 337 #define REG_G2_BG1CNT_PRIORITY_SHIFT 0 338 #define REG_G2_BG1CNT_PRIORITY_SIZE 2 339 #define REG_G2_BG1CNT_PRIORITY_MASK 0x0003 340 341 #ifndef SDK_ASM 342 #define REG_G2_BG1CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ 343 (u16)( \ 344 ((u32)(screensize) << REG_G2_BG1CNT_SCREENSIZE_SHIFT) | \ 345 ((u32)(bgplttslot) << REG_G2_BG1CNT_BGPLTTSLOT_SHIFT) | \ 346 ((u32)(screenbase) << REG_G2_BG1CNT_SCREENBASE_SHIFT) | \ 347 ((u32)(colormode) << REG_G2_BG1CNT_COLORMODE_SHIFT) | \ 348 ((u32)(mosaic) << REG_G2_BG1CNT_MOSAIC_SHIFT) | \ 349 ((u32)(charbase) << REG_G2_BG1CNT_CHARBASE_SHIFT) | \ 350 ((u32)(priority) << REG_G2_BG1CNT_PRIORITY_SHIFT)) 351 #endif 352 353 354 /* BG2CNT */ 355 356 #define REG_G2_BG2CNT_SCREENSIZE_SHIFT 14 357 #define REG_G2_BG2CNT_SCREENSIZE_SIZE 2 358 #define REG_G2_BG2CNT_SCREENSIZE_MASK 0xc000 359 360 #define REG_G2_BG2CNT_AREAOVER_SHIFT 13 361 #define REG_G2_BG2CNT_AREAOVER_SIZE 1 362 #define REG_G2_BG2CNT_AREAOVER_MASK 0x2000 363 364 #define REG_G2_BG2CNT_SCREENBASE_SHIFT 8 365 #define REG_G2_BG2CNT_SCREENBASE_SIZE 5 366 #define REG_G2_BG2CNT_SCREENBASE_MASK 0x1f00 367 368 #define REG_G2_BG2CNT_COLORMODE_SHIFT 7 369 #define REG_G2_BG2CNT_COLORMODE_SIZE 1 370 #define REG_G2_BG2CNT_COLORMODE_MASK 0x0080 371 372 #define REG_G2_BG2CNT_MOSAIC_SHIFT 6 373 #define REG_G2_BG2CNT_MOSAIC_SIZE 1 374 #define REG_G2_BG2CNT_MOSAIC_MASK 0x0040 375 376 #define REG_G2_BG2CNT_CHARBASE_SHIFT 2 377 #define REG_G2_BG2CNT_CHARBASE_SIZE 4 378 #define REG_G2_BG2CNT_CHARBASE_MASK 0x003c 379 380 #define REG_G2_BG2CNT_PRIORITY_SHIFT 0 381 #define REG_G2_BG2CNT_PRIORITY_SIZE 2 382 #define REG_G2_BG2CNT_PRIORITY_MASK 0x0003 383 384 #ifndef SDK_ASM 385 #define REG_G2_BG2CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ 386 (u16)( \ 387 ((u32)(screensize) << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | \ 388 ((u32)(areaover) << REG_G2_BG2CNT_AREAOVER_SHIFT) | \ 389 ((u32)(screenbase) << REG_G2_BG2CNT_SCREENBASE_SHIFT) | \ 390 ((u32)(colormode) << REG_G2_BG2CNT_COLORMODE_SHIFT) | \ 391 ((u32)(mosaic) << REG_G2_BG2CNT_MOSAIC_SHIFT) | \ 392 ((u32)(charbase) << REG_G2_BG2CNT_CHARBASE_SHIFT) | \ 393 ((u32)(priority) << REG_G2_BG2CNT_PRIORITY_SHIFT)) 394 #endif 395 396 397 /* BG3CNT */ 398 399 #define REG_G2_BG3CNT_SCREENSIZE_SHIFT 14 400 #define REG_G2_BG3CNT_SCREENSIZE_SIZE 2 401 #define REG_G2_BG3CNT_SCREENSIZE_MASK 0xc000 402 403 #define REG_G2_BG3CNT_AREAOVER_SHIFT 13 404 #define REG_G2_BG3CNT_AREAOVER_SIZE 1 405 #define REG_G2_BG3CNT_AREAOVER_MASK 0x2000 406 407 #define REG_G2_BG3CNT_SCREENBASE_SHIFT 8 408 #define REG_G2_BG3CNT_SCREENBASE_SIZE 5 409 #define REG_G2_BG3CNT_SCREENBASE_MASK 0x1f00 410 411 #define REG_G2_BG3CNT_COLORMODE_SHIFT 7 412 #define REG_G2_BG3CNT_COLORMODE_SIZE 1 413 #define REG_G2_BG3CNT_COLORMODE_MASK 0x0080 414 415 #define REG_G2_BG3CNT_MOSAIC_SHIFT 6 416 #define REG_G2_BG3CNT_MOSAIC_SIZE 1 417 #define REG_G2_BG3CNT_MOSAIC_MASK 0x0040 418 419 #define REG_G2_BG3CNT_CHARBASE_SHIFT 2 420 #define REG_G2_BG3CNT_CHARBASE_SIZE 4 421 #define REG_G2_BG3CNT_CHARBASE_MASK 0x003c 422 423 #define REG_G2_BG3CNT_PRIORITY_SHIFT 0 424 #define REG_G2_BG3CNT_PRIORITY_SIZE 2 425 #define REG_G2_BG3CNT_PRIORITY_MASK 0x0003 426 427 #ifndef SDK_ASM 428 #define REG_G2_BG3CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ 429 (u16)( \ 430 ((u32)(screensize) << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | \ 431 ((u32)(areaover) << REG_G2_BG3CNT_AREAOVER_SHIFT) | \ 432 ((u32)(screenbase) << REG_G2_BG3CNT_SCREENBASE_SHIFT) | \ 433 ((u32)(colormode) << REG_G2_BG3CNT_COLORMODE_SHIFT) | \ 434 ((u32)(mosaic) << REG_G2_BG3CNT_MOSAIC_SHIFT) | \ 435 ((u32)(charbase) << REG_G2_BG3CNT_CHARBASE_SHIFT) | \ 436 ((u32)(priority) << REG_G2_BG3CNT_PRIORITY_SHIFT)) 437 #endif 438 439 440 /* BG0OFS */ 441 442 #define REG_G2_BG0OFS_VOFFSET_SHIFT 16 443 #define REG_G2_BG0OFS_VOFFSET_SIZE 9 444 #define REG_G2_BG0OFS_VOFFSET_MASK 0x01ff0000 445 446 #define REG_G2_BG0OFS_HOFFSET_SHIFT 0 447 #define REG_G2_BG0OFS_HOFFSET_SIZE 9 448 #define REG_G2_BG0OFS_HOFFSET_MASK 0x000001ff 449 450 #ifndef SDK_ASM 451 #define REG_G2_BG0OFS_FIELD( voffset, hoffset ) \ 452 (u32)( \ 453 ((u32)(voffset) << REG_G2_BG0OFS_VOFFSET_SHIFT) | \ 454 ((u32)(hoffset) << REG_G2_BG0OFS_HOFFSET_SHIFT)) 455 #endif 456 457 458 /* BG0HOFS */ 459 460 #define REG_G2_BG0HOFS_OFFSET_SHIFT 0 461 #define REG_G2_BG0HOFS_OFFSET_SIZE 9 462 #define REG_G2_BG0HOFS_OFFSET_MASK 0x01ff 463 464 #ifndef SDK_ASM 465 #define REG_G2_BG0HOFS_FIELD( offset ) \ 466 (u16)( \ 467 ((u32)(offset) << REG_G2_BG0HOFS_OFFSET_SHIFT)) 468 #endif 469 470 471 /* BG0VOFS */ 472 473 #define REG_G2_BG0VOFS_OFFSET_SHIFT 0 474 #define REG_G2_BG0VOFS_OFFSET_SIZE 9 475 #define REG_G2_BG0VOFS_OFFSET_MASK 0x01ff 476 477 #ifndef SDK_ASM 478 #define REG_G2_BG0VOFS_FIELD( offset ) \ 479 (u16)( \ 480 ((u32)(offset) << REG_G2_BG0VOFS_OFFSET_SHIFT)) 481 #endif 482 483 484 /* BG1OFS */ 485 486 #define REG_G2_BG1OFS_VOFFSET_SHIFT 16 487 #define REG_G2_BG1OFS_VOFFSET_SIZE 9 488 #define REG_G2_BG1OFS_VOFFSET_MASK 0x01ff0000 489 490 #define REG_G2_BG1OFS_HOFFSET_SHIFT 0 491 #define REG_G2_BG1OFS_HOFFSET_SIZE 9 492 #define REG_G2_BG1OFS_HOFFSET_MASK 0x000001ff 493 494 #ifndef SDK_ASM 495 #define REG_G2_BG1OFS_FIELD( voffset, hoffset ) \ 496 (u32)( \ 497 ((u32)(voffset) << REG_G2_BG1OFS_VOFFSET_SHIFT) | \ 498 ((u32)(hoffset) << REG_G2_BG1OFS_HOFFSET_SHIFT)) 499 #endif 500 501 502 /* BG1HOFS */ 503 504 #define REG_G2_BG1HOFS_OFFSET_SHIFT 0 505 #define REG_G2_BG1HOFS_OFFSET_SIZE 9 506 #define REG_G2_BG1HOFS_OFFSET_MASK 0x01ff 507 508 #ifndef SDK_ASM 509 #define REG_G2_BG1HOFS_FIELD( offset ) \ 510 (u16)( \ 511 ((u32)(offset) << REG_G2_BG1HOFS_OFFSET_SHIFT)) 512 #endif 513 514 515 /* BG1VOFS */ 516 517 #define REG_G2_BG1VOFS_OFFSET_SHIFT 0 518 #define REG_G2_BG1VOFS_OFFSET_SIZE 9 519 #define REG_G2_BG1VOFS_OFFSET_MASK 0x01ff 520 521 #ifndef SDK_ASM 522 #define REG_G2_BG1VOFS_FIELD( offset ) \ 523 (u16)( \ 524 ((u32)(offset) << REG_G2_BG1VOFS_OFFSET_SHIFT)) 525 #endif 526 527 528 /* BG2OFS */ 529 530 #define REG_G2_BG2OFS_VOFFSET_SHIFT 16 531 #define REG_G2_BG2OFS_VOFFSET_SIZE 9 532 #define REG_G2_BG2OFS_VOFFSET_MASK 0x01ff0000 533 534 #define REG_G2_BG2OFS_HOFFSET_SHIFT 0 535 #define REG_G2_BG2OFS_HOFFSET_SIZE 9 536 #define REG_G2_BG2OFS_HOFFSET_MASK 0x000001ff 537 538 #ifndef SDK_ASM 539 #define REG_G2_BG2OFS_FIELD( voffset, hoffset ) \ 540 (u32)( \ 541 ((u32)(voffset) << REG_G2_BG2OFS_VOFFSET_SHIFT) | \ 542 ((u32)(hoffset) << REG_G2_BG2OFS_HOFFSET_SHIFT)) 543 #endif 544 545 546 /* BG2HOFS */ 547 548 #define REG_G2_BG2HOFS_OFFSET_SHIFT 0 549 #define REG_G2_BG2HOFS_OFFSET_SIZE 9 550 #define REG_G2_BG2HOFS_OFFSET_MASK 0x01ff 551 552 #ifndef SDK_ASM 553 #define REG_G2_BG2HOFS_FIELD( offset ) \ 554 (u16)( \ 555 ((u32)(offset) << REG_G2_BG2HOFS_OFFSET_SHIFT)) 556 #endif 557 558 559 /* BG2VOFS */ 560 561 #define REG_G2_BG2VOFS_OFFSET_SHIFT 0 562 #define REG_G2_BG2VOFS_OFFSET_SIZE 9 563 #define REG_G2_BG2VOFS_OFFSET_MASK 0x01ff 564 565 #ifndef SDK_ASM 566 #define REG_G2_BG2VOFS_FIELD( offset ) \ 567 (u16)( \ 568 ((u32)(offset) << REG_G2_BG2VOFS_OFFSET_SHIFT)) 569 #endif 570 571 572 /* BG3OFS */ 573 574 #define REG_G2_BG3OFS_VOFFSET_SHIFT 16 575 #define REG_G2_BG3OFS_VOFFSET_SIZE 9 576 #define REG_G2_BG3OFS_VOFFSET_MASK 0x01ff0000 577 578 #define REG_G2_BG3OFS_HOFFSET_SHIFT 0 579 #define REG_G2_BG3OFS_HOFFSET_SIZE 9 580 #define REG_G2_BG3OFS_HOFFSET_MASK 0x000001ff 581 582 #ifndef SDK_ASM 583 #define REG_G2_BG3OFS_FIELD( voffset, hoffset ) \ 584 (u32)( \ 585 ((u32)(voffset) << REG_G2_BG3OFS_VOFFSET_SHIFT) | \ 586 ((u32)(hoffset) << REG_G2_BG3OFS_HOFFSET_SHIFT)) 587 #endif 588 589 590 /* BG3HOFS */ 591 592 #define REG_G2_BG3HOFS_OFFSET_SHIFT 0 593 #define REG_G2_BG3HOFS_OFFSET_SIZE 9 594 #define REG_G2_BG3HOFS_OFFSET_MASK 0x01ff 595 596 #ifndef SDK_ASM 597 #define REG_G2_BG3HOFS_FIELD( offset ) \ 598 (u16)( \ 599 ((u32)(offset) << REG_G2_BG3HOFS_OFFSET_SHIFT)) 600 #endif 601 602 603 /* BG3VOFS */ 604 605 #define REG_G2_BG3VOFS_OFFSET_SHIFT 0 606 #define REG_G2_BG3VOFS_OFFSET_SIZE 9 607 #define REG_G2_BG3VOFS_OFFSET_MASK 0x01ff 608 609 #ifndef SDK_ASM 610 #define REG_G2_BG3VOFS_FIELD( offset ) \ 611 (u16)( \ 612 ((u32)(offset) << REG_G2_BG3VOFS_OFFSET_SHIFT)) 613 #endif 614 615 616 /* BG2PA */ 617 618 #define REG_G2_BG2PA_S_SHIFT 15 619 #define REG_G2_BG2PA_S_SIZE 1 620 #define REG_G2_BG2PA_S_MASK 0x8000 621 622 #define REG_G2_BG2PA_INTEGER_DX_SHIFT 8 623 #define REG_G2_BG2PA_INTEGER_DX_SIZE 7 624 #define REG_G2_BG2PA_INTEGER_DX_MASK 0x7f00 625 626 #define REG_G2_BG2PA_DECIMAL_DX_SHIFT 0 627 #define REG_G2_BG2PA_DECIMAL_DX_SIZE 8 628 #define REG_G2_BG2PA_DECIMAL_DX_MASK 0x00ff 629 630 #ifndef SDK_ASM 631 #define REG_G2_BG2PA_FIELD( s, integer_dx, decimal_dx ) \ 632 (u16)( \ 633 ((u32)(s) << REG_G2_BG2PA_S_SHIFT) | \ 634 ((u32)(integer_dx) << REG_G2_BG2PA_INTEGER_DX_SHIFT) | \ 635 ((u32)(decimal_dx) << REG_G2_BG2PA_DECIMAL_DX_SHIFT)) 636 #endif 637 638 639 /* BG2PB */ 640 641 #define REG_G2_BG2PB_S_SHIFT 15 642 #define REG_G2_BG2PB_S_SIZE 1 643 #define REG_G2_BG2PB_S_MASK 0x8000 644 645 #define REG_G2_BG2PB_INTEGER_DMX_SHIFT 8 646 #define REG_G2_BG2PB_INTEGER_DMX_SIZE 7 647 #define REG_G2_BG2PB_INTEGER_DMX_MASK 0x7f00 648 649 #define REG_G2_BG2PB_DECIMAL_DMX_SHIFT 0 650 #define REG_G2_BG2PB_DECIMAL_DMX_SIZE 8 651 #define REG_G2_BG2PB_DECIMAL_DMX_MASK 0x00ff 652 653 #ifndef SDK_ASM 654 #define REG_G2_BG2PB_FIELD( s, integer_dmx, decimal_dmx ) \ 655 (u16)( \ 656 ((u32)(s) << REG_G2_BG2PB_S_SHIFT) | \ 657 ((u32)(integer_dmx) << REG_G2_BG2PB_INTEGER_DMX_SHIFT) | \ 658 ((u32)(decimal_dmx) << REG_G2_BG2PB_DECIMAL_DMX_SHIFT)) 659 #endif 660 661 662 /* BG2PC */ 663 664 #define REG_G2_BG2PC_S_SHIFT 15 665 #define REG_G2_BG2PC_S_SIZE 1 666 #define REG_G2_BG2PC_S_MASK 0x8000 667 668 #define REG_G2_BG2PC_INTEGER_DY_SHIFT 8 669 #define REG_G2_BG2PC_INTEGER_DY_SIZE 7 670 #define REG_G2_BG2PC_INTEGER_DY_MASK 0x7f00 671 672 #define REG_G2_BG2PC_DECIMAL_DY_SHIFT 0 673 #define REG_G2_BG2PC_DECIMAL_DY_SIZE 8 674 #define REG_G2_BG2PC_DECIMAL_DY_MASK 0x00ff 675 676 #ifndef SDK_ASM 677 #define REG_G2_BG2PC_FIELD( s, integer_dy, decimal_dy ) \ 678 (u16)( \ 679 ((u32)(s) << REG_G2_BG2PC_S_SHIFT) | \ 680 ((u32)(integer_dy) << REG_G2_BG2PC_INTEGER_DY_SHIFT) | \ 681 ((u32)(decimal_dy) << REG_G2_BG2PC_DECIMAL_DY_SHIFT)) 682 #endif 683 684 685 /* BG2PD */ 686 687 #define REG_G2_BG2PD_S_SHIFT 15 688 #define REG_G2_BG2PD_S_SIZE 1 689 #define REG_G2_BG2PD_S_MASK 0x8000 690 691 #define REG_G2_BG2PD_INTEGER_DMY_SHIFT 8 692 #define REG_G2_BG2PD_INTEGER_DMY_SIZE 7 693 #define REG_G2_BG2PD_INTEGER_DMY_MASK 0x7f00 694 695 #define REG_G2_BG2PD_DECIMAL_DMY_SHIFT 0 696 #define REG_G2_BG2PD_DECIMAL_DMY_SIZE 8 697 #define REG_G2_BG2PD_DECIMAL_DMY_MASK 0x00ff 698 699 #ifndef SDK_ASM 700 #define REG_G2_BG2PD_FIELD( s, integer_dmy, decimal_dmy ) \ 701 (u16)( \ 702 ((u32)(s) << REG_G2_BG2PD_S_SHIFT) | \ 703 ((u32)(integer_dmy) << REG_G2_BG2PD_INTEGER_DMY_SHIFT) | \ 704 ((u32)(decimal_dmy) << REG_G2_BG2PD_DECIMAL_DMY_SHIFT)) 705 #endif 706 707 708 /* BG2X */ 709 710 #define REG_G2_BG2X_S_SHIFT 27 711 #define REG_G2_BG2X_S_SIZE 1 712 #define REG_G2_BG2X_S_MASK 0x08000000 713 714 #define REG_G2_BG2X_INTEGER_SX_SHIFT 8 715 #define REG_G2_BG2X_INTEGER_SX_SIZE 19 716 #define REG_G2_BG2X_INTEGER_SX_MASK 0x07ffff00 717 718 #define REG_G2_BG2X_DECIMAL_SX_SHIFT 0 719 #define REG_G2_BG2X_DECIMAL_SX_SIZE 8 720 #define REG_G2_BG2X_DECIMAL_SX_MASK 0x000000ff 721 722 #ifndef SDK_ASM 723 #define REG_G2_BG2X_FIELD( s, integer_sx, decimal_sx ) \ 724 (u32)( \ 725 ((u32)(s) << REG_G2_BG2X_S_SHIFT) | \ 726 ((u32)(integer_sx) << REG_G2_BG2X_INTEGER_SX_SHIFT) | \ 727 ((u32)(decimal_sx) << REG_G2_BG2X_DECIMAL_SX_SHIFT)) 728 #endif 729 730 731 /* BG2Y */ 732 733 #define REG_G2_BG2Y_S_SHIFT 27 734 #define REG_G2_BG2Y_S_SIZE 1 735 #define REG_G2_BG2Y_S_MASK 0x08000000 736 737 #define REG_G2_BG2Y_INTEGER_SY_SHIFT 8 738 #define REG_G2_BG2Y_INTEGER_SY_SIZE 19 739 #define REG_G2_BG2Y_INTEGER_SY_MASK 0x07ffff00 740 741 #define REG_G2_BG2Y_DECIMAL_SY_SHIFT 0 742 #define REG_G2_BG2Y_DECIMAL_SY_SIZE 8 743 #define REG_G2_BG2Y_DECIMAL_SY_MASK 0x000000ff 744 745 #ifndef SDK_ASM 746 #define REG_G2_BG2Y_FIELD( s, integer_sy, decimal_sy ) \ 747 (u32)( \ 748 ((u32)(s) << REG_G2_BG2Y_S_SHIFT) | \ 749 ((u32)(integer_sy) << REG_G2_BG2Y_INTEGER_SY_SHIFT) | \ 750 ((u32)(decimal_sy) << REG_G2_BG2Y_DECIMAL_SY_SHIFT)) 751 #endif 752 753 754 /* BG3PA */ 755 756 #define REG_G2_BG3PA_S_SHIFT 15 757 #define REG_G2_BG3PA_S_SIZE 1 758 #define REG_G2_BG3PA_S_MASK 0x8000 759 760 #define REG_G2_BG3PA_INTEGER_DX_SHIFT 8 761 #define REG_G2_BG3PA_INTEGER_DX_SIZE 7 762 #define REG_G2_BG3PA_INTEGER_DX_MASK 0x7f00 763 764 #define REG_G2_BG3PA_DECIMAL_DX_SHIFT 0 765 #define REG_G2_BG3PA_DECIMAL_DX_SIZE 8 766 #define REG_G2_BG3PA_DECIMAL_DX_MASK 0x00ff 767 768 #ifndef SDK_ASM 769 #define REG_G2_BG3PA_FIELD( s, integer_dx, decimal_dx ) \ 770 (u16)( \ 771 ((u32)(s) << REG_G2_BG3PA_S_SHIFT) | \ 772 ((u32)(integer_dx) << REG_G2_BG3PA_INTEGER_DX_SHIFT) | \ 773 ((u32)(decimal_dx) << REG_G2_BG3PA_DECIMAL_DX_SHIFT)) 774 #endif 775 776 777 /* BG3PB */ 778 779 #define REG_G2_BG3PB_S_SHIFT 15 780 #define REG_G2_BG3PB_S_SIZE 1 781 #define REG_G2_BG3PB_S_MASK 0x8000 782 783 #define REG_G2_BG3PB_INTEGER_DMX_SHIFT 8 784 #define REG_G2_BG3PB_INTEGER_DMX_SIZE 7 785 #define REG_G2_BG3PB_INTEGER_DMX_MASK 0x7f00 786 787 #define REG_G2_BG3PB_DECIMAL_DMX_SHIFT 0 788 #define REG_G2_BG3PB_DECIMAL_DMX_SIZE 8 789 #define REG_G2_BG3PB_DECIMAL_DMX_MASK 0x00ff 790 791 #ifndef SDK_ASM 792 #define REG_G2_BG3PB_FIELD( s, integer_dmx, decimal_dmx ) \ 793 (u16)( \ 794 ((u32)(s) << REG_G2_BG3PB_S_SHIFT) | \ 795 ((u32)(integer_dmx) << REG_G2_BG3PB_INTEGER_DMX_SHIFT) | \ 796 ((u32)(decimal_dmx) << REG_G2_BG3PB_DECIMAL_DMX_SHIFT)) 797 #endif 798 799 800 /* BG3PC */ 801 802 #define REG_G2_BG3PC_S_SHIFT 15 803 #define REG_G2_BG3PC_S_SIZE 1 804 #define REG_G2_BG3PC_S_MASK 0x8000 805 806 #define REG_G2_BG3PC_INTEGER_DY_SHIFT 8 807 #define REG_G2_BG3PC_INTEGER_DY_SIZE 7 808 #define REG_G2_BG3PC_INTEGER_DY_MASK 0x7f00 809 810 #define REG_G2_BG3PC_DECIMAL_DY_SHIFT 0 811 #define REG_G2_BG3PC_DECIMAL_DY_SIZE 8 812 #define REG_G2_BG3PC_DECIMAL_DY_MASK 0x00ff 813 814 #ifndef SDK_ASM 815 #define REG_G2_BG3PC_FIELD( s, integer_dy, decimal_dy ) \ 816 (u16)( \ 817 ((u32)(s) << REG_G2_BG3PC_S_SHIFT) | \ 818 ((u32)(integer_dy) << REG_G2_BG3PC_INTEGER_DY_SHIFT) | \ 819 ((u32)(decimal_dy) << REG_G2_BG3PC_DECIMAL_DY_SHIFT)) 820 #endif 821 822 823 /* BG3PD */ 824 825 #define REG_G2_BG3PD_S_SHIFT 15 826 #define REG_G2_BG3PD_S_SIZE 1 827 #define REG_G2_BG3PD_S_MASK 0x8000 828 829 #define REG_G2_BG3PD_INTEGER_DMY_SHIFT 8 830 #define REG_G2_BG3PD_INTEGER_DMY_SIZE 7 831 #define REG_G2_BG3PD_INTEGER_DMY_MASK 0x7f00 832 833 #define REG_G2_BG3PD_DECIMAL_DMY_SHIFT 0 834 #define REG_G2_BG3PD_DECIMAL_DMY_SIZE 8 835 #define REG_G2_BG3PD_DECIMAL_DMY_MASK 0x00ff 836 837 #ifndef SDK_ASM 838 #define REG_G2_BG3PD_FIELD( s, integer_dmy, decimal_dmy ) \ 839 (u16)( \ 840 ((u32)(s) << REG_G2_BG3PD_S_SHIFT) | \ 841 ((u32)(integer_dmy) << REG_G2_BG3PD_INTEGER_DMY_SHIFT) | \ 842 ((u32)(decimal_dmy) << REG_G2_BG3PD_DECIMAL_DMY_SHIFT)) 843 #endif 844 845 846 /* BG3X */ 847 848 #define REG_G2_BG3X_S_SHIFT 27 849 #define REG_G2_BG3X_S_SIZE 1 850 #define REG_G2_BG3X_S_MASK 0x08000000 851 852 #define REG_G2_BG3X_INTEGER_SX_SHIFT 8 853 #define REG_G2_BG3X_INTEGER_SX_SIZE 19 854 #define REG_G2_BG3X_INTEGER_SX_MASK 0x07ffff00 855 856 #define REG_G2_BG3X_DECIMAL_SX_SHIFT 0 857 #define REG_G2_BG3X_DECIMAL_SX_SIZE 8 858 #define REG_G2_BG3X_DECIMAL_SX_MASK 0x000000ff 859 860 #ifndef SDK_ASM 861 #define REG_G2_BG3X_FIELD( s, integer_sx, decimal_sx ) \ 862 (u32)( \ 863 ((u32)(s) << REG_G2_BG3X_S_SHIFT) | \ 864 ((u32)(integer_sx) << REG_G2_BG3X_INTEGER_SX_SHIFT) | \ 865 ((u32)(decimal_sx) << REG_G2_BG3X_DECIMAL_SX_SHIFT)) 866 #endif 867 868 869 /* BG3Y */ 870 871 #define REG_G2_BG3Y_S_SHIFT 27 872 #define REG_G2_BG3Y_S_SIZE 1 873 #define REG_G2_BG3Y_S_MASK 0x08000000 874 875 #define REG_G2_BG3Y_INTEGER_SY_SHIFT 8 876 #define REG_G2_BG3Y_INTEGER_SY_SIZE 19 877 #define REG_G2_BG3Y_INTEGER_SY_MASK 0x07ffff00 878 879 #define REG_G2_BG3Y_DECIMAL_SY_SHIFT 0 880 #define REG_G2_BG3Y_DECIMAL_SY_SIZE 8 881 #define REG_G2_BG3Y_DECIMAL_SY_MASK 0x000000ff 882 883 #ifndef SDK_ASM 884 #define REG_G2_BG3Y_FIELD( s, integer_sy, decimal_sy ) \ 885 (u32)( \ 886 ((u32)(s) << REG_G2_BG3Y_S_SHIFT) | \ 887 ((u32)(integer_sy) << REG_G2_BG3Y_INTEGER_SY_SHIFT) | \ 888 ((u32)(decimal_sy) << REG_G2_BG3Y_DECIMAL_SY_SHIFT)) 889 #endif 890 891 892 /* WIN0H */ 893 894 #define REG_G2_WIN0H_LEFTX_SHIFT 8 895 #define REG_G2_WIN0H_LEFTX_SIZE 8 896 #define REG_G2_WIN0H_LEFTX_MASK 0xff00 897 898 #define REG_G2_WIN0H_RIGHTX_SHIFT 0 899 #define REG_G2_WIN0H_RIGHTX_SIZE 8 900 #define REG_G2_WIN0H_RIGHTX_MASK 0x00ff 901 902 #ifndef SDK_ASM 903 #define REG_G2_WIN0H_FIELD( leftx, rightx ) \ 904 (u16)( \ 905 ((u32)(leftx) << REG_G2_WIN0H_LEFTX_SHIFT) | \ 906 ((u32)(rightx) << REG_G2_WIN0H_RIGHTX_SHIFT)) 907 #endif 908 909 910 /* WIN1H */ 911 912 #define REG_G2_WIN1H_LEFTX_SHIFT 8 913 #define REG_G2_WIN1H_LEFTX_SIZE 8 914 #define REG_G2_WIN1H_LEFTX_MASK 0xff00 915 916 #define REG_G2_WIN1H_RIGHTX_SHIFT 0 917 #define REG_G2_WIN1H_RIGHTX_SIZE 8 918 #define REG_G2_WIN1H_RIGHTX_MASK 0x00ff 919 920 #ifndef SDK_ASM 921 #define REG_G2_WIN1H_FIELD( leftx, rightx ) \ 922 (u16)( \ 923 ((u32)(leftx) << REG_G2_WIN1H_LEFTX_SHIFT) | \ 924 ((u32)(rightx) << REG_G2_WIN1H_RIGHTX_SHIFT)) 925 #endif 926 927 928 /* WIN0V */ 929 930 #define REG_G2_WIN0V_UPY_SHIFT 8 931 #define REG_G2_WIN0V_UPY_SIZE 8 932 #define REG_G2_WIN0V_UPY_MASK 0xff00 933 934 #define REG_G2_WIN0V_DOWNY_SHIFT 0 935 #define REG_G2_WIN0V_DOWNY_SIZE 8 936 #define REG_G2_WIN0V_DOWNY_MASK 0x00ff 937 938 #ifndef SDK_ASM 939 #define REG_G2_WIN0V_FIELD( upy, downy ) \ 940 (u16)( \ 941 ((u32)(upy) << REG_G2_WIN0V_UPY_SHIFT) | \ 942 ((u32)(downy) << REG_G2_WIN0V_DOWNY_SHIFT)) 943 #endif 944 945 946 /* WIN1V */ 947 948 #define REG_G2_WIN1V_UPY_SHIFT 8 949 #define REG_G2_WIN1V_UPY_SIZE 8 950 #define REG_G2_WIN1V_UPY_MASK 0xff00 951 952 #define REG_G2_WIN1V_DOWNY_SHIFT 0 953 #define REG_G2_WIN1V_DOWNY_SIZE 8 954 #define REG_G2_WIN1V_DOWNY_MASK 0x00ff 955 956 #ifndef SDK_ASM 957 #define REG_G2_WIN1V_FIELD( upy, downy ) \ 958 (u16)( \ 959 ((u32)(upy) << REG_G2_WIN1V_UPY_SHIFT) | \ 960 ((u32)(downy) << REG_G2_WIN1V_DOWNY_SHIFT)) 961 #endif 962 963 964 /* WININ */ 965 966 #define REG_G2_WININ_WIN1IN_SHIFT 8 967 #define REG_G2_WININ_WIN1IN_SIZE 6 968 #define REG_G2_WININ_WIN1IN_MASK 0x3f00 969 970 #define REG_G2_WININ_WIN0IN_SHIFT 0 971 #define REG_G2_WININ_WIN0IN_SIZE 6 972 #define REG_G2_WININ_WIN0IN_MASK 0x003f 973 974 #ifndef SDK_ASM 975 #define REG_G2_WININ_FIELD( win1in, win0in ) \ 976 (u16)( \ 977 ((u32)(win1in) << REG_G2_WININ_WIN1IN_SHIFT) | \ 978 ((u32)(win0in) << REG_G2_WININ_WIN0IN_SHIFT)) 979 #endif 980 981 982 /* WINOUT */ 983 984 #define REG_G2_WINOUT_OBJWININ_SHIFT 8 985 #define REG_G2_WINOUT_OBJWININ_SIZE 6 986 #define REG_G2_WINOUT_OBJWININ_MASK 0x3f00 987 988 #define REG_G2_WINOUT_WINOUT_SHIFT 0 989 #define REG_G2_WINOUT_WINOUT_SIZE 6 990 #define REG_G2_WINOUT_WINOUT_MASK 0x003f 991 992 #ifndef SDK_ASM 993 #define REG_G2_WINOUT_FIELD( objwinin, winout ) \ 994 (u16)( \ 995 ((u32)(objwinin) << REG_G2_WINOUT_OBJWININ_SHIFT) | \ 996 ((u32)(winout) << REG_G2_WINOUT_WINOUT_SHIFT)) 997 #endif 998 999 1000 /* MOSAIC */ 1001 1002 #define REG_G2_MOSAIC_OBJVSIZE_SHIFT 12 1003 #define REG_G2_MOSAIC_OBJVSIZE_SIZE 4 1004 #define REG_G2_MOSAIC_OBJVSIZE_MASK 0xf000 1005 1006 #define REG_G2_MOSAIC_OBJHSIZE_SHIFT 8 1007 #define REG_G2_MOSAIC_OBJHSIZE_SIZE 4 1008 #define REG_G2_MOSAIC_OBJHSIZE_MASK 0x0f00 1009 1010 #define REG_G2_MOSAIC_BGVSIZE_SHIFT 4 1011 #define REG_G2_MOSAIC_BGVSIZE_SIZE 4 1012 #define REG_G2_MOSAIC_BGVSIZE_MASK 0x00f0 1013 1014 #define REG_G2_MOSAIC_BGHSIZE_SHIFT 0 1015 #define REG_G2_MOSAIC_BGHSIZE_SIZE 4 1016 #define REG_G2_MOSAIC_BGHSIZE_MASK 0x000f 1017 1018 #ifndef SDK_ASM 1019 #define REG_G2_MOSAIC_FIELD( objvsize, objhsize, bgvsize, bghsize ) \ 1020 (u16)( \ 1021 ((u32)(objvsize) << REG_G2_MOSAIC_OBJVSIZE_SHIFT) | \ 1022 ((u32)(objhsize) << REG_G2_MOSAIC_OBJHSIZE_SHIFT) | \ 1023 ((u32)(bgvsize) << REG_G2_MOSAIC_BGVSIZE_SHIFT) | \ 1024 ((u32)(bghsize) << REG_G2_MOSAIC_BGHSIZE_SHIFT)) 1025 #endif 1026 1027 1028 /* BLDCNT */ 1029 1030 #define REG_G2_BLDCNT_PLANE2_SHIFT 8 1031 #define REG_G2_BLDCNT_PLANE2_SIZE 6 1032 #define REG_G2_BLDCNT_PLANE2_MASK 0x3f00 1033 1034 #define REG_G2_BLDCNT_EFFECT_SHIFT 6 1035 #define REG_G2_BLDCNT_EFFECT_SIZE 2 1036 #define REG_G2_BLDCNT_EFFECT_MASK 0x00c0 1037 1038 #define REG_G2_BLDCNT_PLANE1_SHIFT 0 1039 #define REG_G2_BLDCNT_PLANE1_SIZE 6 1040 #define REG_G2_BLDCNT_PLANE1_MASK 0x003f 1041 1042 #ifndef SDK_ASM 1043 #define REG_G2_BLDCNT_FIELD( plane2, effect, plane1 ) \ 1044 (u16)( \ 1045 ((u32)(plane2) << REG_G2_BLDCNT_PLANE2_SHIFT) | \ 1046 ((u32)(effect) << REG_G2_BLDCNT_EFFECT_SHIFT) | \ 1047 ((u32)(plane1) << REG_G2_BLDCNT_PLANE1_SHIFT)) 1048 #endif 1049 1050 1051 /* BLDALPHA */ 1052 1053 #define REG_G2_BLDALPHA_EVB_SHIFT 8 1054 #define REG_G2_BLDALPHA_EVB_SIZE 5 1055 #define REG_G2_BLDALPHA_EVB_MASK 0x1f00 1056 1057 #define REG_G2_BLDALPHA_EVA_SHIFT 0 1058 #define REG_G2_BLDALPHA_EVA_SIZE 5 1059 #define REG_G2_BLDALPHA_EVA_MASK 0x001f 1060 1061 #ifndef SDK_ASM 1062 #define REG_G2_BLDALPHA_FIELD( evb, eva ) \ 1063 (u16)( \ 1064 ((u32)(evb) << REG_G2_BLDALPHA_EVB_SHIFT) | \ 1065 ((u32)(eva) << REG_G2_BLDALPHA_EVA_SHIFT)) 1066 #endif 1067 1068 1069 /* BLDY */ 1070 1071 #define REG_G2_BLDY_EVY_SHIFT 0 1072 #define REG_G2_BLDY_EVY_SIZE 5 1073 #define REG_G2_BLDY_EVY_MASK 0x001f 1074 1075 #ifndef SDK_ASM 1076 #define REG_G2_BLDY_FIELD( evy ) \ 1077 (u16)( \ 1078 ((u32)(evy) << REG_G2_BLDY_EVY_SHIFT)) 1079 #endif 1080 1081 1082 #ifdef __cplusplus 1083 } /* extern "C" */ 1084 #endif 1085 1086 /* TWL_HW_ARM9_IOREG_G2_H_ */ 1087 #endif 1088