1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_PXI.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_PXI_H_ 18 #define NITRO_HW_ARM9_IOREG_PXI_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* SUBPINTF */ 35 36 #define REG_SUBPINTF_OFFSET 0x180 37 #define REG_SUBPINTF_ADDR (HW_REG_BASE + REG_SUBPINTF_OFFSET) 38 #define reg_PXI_SUBPINTF (*( REGType16v *) REG_SUBPINTF_ADDR) 39 40 /* SUBP_FIFO_CNT */ 41 42 #define REG_SUBP_FIFO_CNT_OFFSET 0x184 43 #define REG_SUBP_FIFO_CNT_ADDR (HW_REG_BASE + REG_SUBP_FIFO_CNT_OFFSET) 44 #define reg_PXI_SUBP_FIFO_CNT (*( REGType16v *) REG_SUBP_FIFO_CNT_ADDR) 45 46 /* SEND_FIFO */ 47 48 #define REG_SEND_FIFO_OFFSET 0x188 49 #define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET) 50 #define reg_PXI_SEND_FIFO (*( REGType32v *) REG_SEND_FIFO_ADDR) 51 52 /* RECV_FIFO */ 53 54 #define REG_RECV_FIFO_OFFSET 0x100000 55 #define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET) 56 #define reg_PXI_RECV_FIFO (*( REGType32v *) REG_RECV_FIFO_ADDR) 57 58 59 /* 60 * Definitions of Register fields 61 */ 62 63 64 /* SUBPINTF */ 65 66 #define REG_PXI_SUBPINTF_I_SHIFT 14 67 #define REG_PXI_SUBPINTF_I_SIZE 1 68 #define REG_PXI_SUBPINTF_I_MASK 0x4000 69 70 #define REG_PXI_SUBPINTF_IREQ_SHIFT 13 71 #define REG_PXI_SUBPINTF_IREQ_SIZE 1 72 #define REG_PXI_SUBPINTF_IREQ_MASK 0x2000 73 74 #define REG_PXI_SUBPINTF_A9STATUS_SHIFT 8 75 #define REG_PXI_SUBPINTF_A9STATUS_SIZE 4 76 #define REG_PXI_SUBPINTF_A9STATUS_MASK 0x0f00 77 78 #define REG_PXI_SUBPINTF_A7STATUS_SHIFT 0 79 #define REG_PXI_SUBPINTF_A7STATUS_SIZE 4 80 #define REG_PXI_SUBPINTF_A7STATUS_MASK 0x000f 81 82 #ifndef SDK_ASM 83 #define REG_PXI_SUBPINTF_FIELD( i, ireq, a9status, a7status ) \ 84 (u16)( \ 85 ((u32)(i) << REG_PXI_SUBPINTF_I_SHIFT) | \ 86 ((u32)(ireq) << REG_PXI_SUBPINTF_IREQ_SHIFT) | \ 87 ((u32)(a9status) << REG_PXI_SUBPINTF_A9STATUS_SHIFT) | \ 88 ((u32)(a7status) << REG_PXI_SUBPINTF_A7STATUS_SHIFT)) 89 #endif 90 91 92 /* SUBP_FIFO_CNT */ 93 94 #define REG_PXI_SUBP_FIFO_CNT_E_SHIFT 15 95 #define REG_PXI_SUBP_FIFO_CNT_E_SIZE 1 96 #define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000 97 98 #define REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT 14 99 #define REG_PXI_SUBP_FIFO_CNT_ERR_SIZE 1 100 #define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000 101 102 #define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT 10 103 #define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SIZE 1 104 #define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x0400 105 106 #define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT 9 107 #define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SIZE 1 108 #define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_MASK 0x0200 109 110 #define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT 8 111 #define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SIZE 1 112 #define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x0100 113 114 #define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT 3 115 #define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SIZE 1 116 #define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x0008 117 118 #define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT 2 119 #define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SIZE 1 120 #define REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK 0x0004 121 122 #define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT 1 123 #define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SIZE 1 124 #define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x0002 125 126 #define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT 0 127 #define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SIZE 1 128 #define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_MASK 0x0001 129 130 #ifndef SDK_ASM 131 #define REG_PXI_SUBP_FIFO_CNT_FIELD( e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp ) \ 132 (u16)( \ 133 ((u32)(e) << REG_PXI_SUBP_FIFO_CNT_E_SHIFT) | \ 134 ((u32)(err) << REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT) | \ 135 ((u32)(recv_ri) << REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT) | \ 136 ((u32)(recv_full) << REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT) | \ 137 ((u32)(recv_emp) << REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT) | \ 138 ((u32)(send_cl) << REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT) | \ 139 ((u32)(send_ti) << REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT) | \ 140 ((u32)(send_full) << REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT) | \ 141 ((u32)(send_emp) << REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT)) 142 #endif 143 144 145 /* SEND_FIFO */ 146 147 /* RECV_FIFO */ 148 149 #ifdef __cplusplus 150 } /* extern "C" */ 151 #endif 152 153 /* NITRO_HW_ARM9_IOREG_PXI_H_ */ 154 #endif 155