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8<TITLE>Memory Interface (MI) Function List</TITLE>
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11<BODY>
12<H1>Memory Interface (MI) Function List</H1>
13
14<H3><A name="init">Initialization</A></H3>
15<TABLE border="1" width="100%">
16  <TBODY>
17    <TR>
18<TH width="25%"><A href="init/MI_Init.html" target="_self">MI_Init</A></TH>
19      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
20<TD>Initializes the MI library.</TD>
21    </TR>
22  </TBODY>
23</TABLE>
24
25
26<H3><A name="memory">CPU Memory Operations</A></H3>
27<TABLE border="1" width="100%">
28  <TBODY>
29    <TR>
30<TH nowrap width="25%"><A href="memory/MI_CpuCopy.html" target="_self">MI_CpuCopy*</A></TH>
31      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
32<TD>Copies data.</TD>
33    </TR>
34    <TR>
35<TH width="25%"><A href="memory/MI_CpuMove.html" target="_self">MI_CpuMove*</A></TH>
36      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
37<TD>Moves data.</TD>
38    </TR>
39    <TR>
40<TH nowrap width="25%"><A href="memory/MI_CpuFill.html" target="_self">MI_CpuFill*</A></TH>
41      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
42<TD>Fills memory with specified data.</TD>
43    </TR>
44    <TR>
45<TH width="25%"><A href="memory/MI_CpuClear.html" target="_self">MI_CpuClear*</A></TH>
46      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
47<TD>Zero-clears memory.</TD>
48    </TR>
49    <TR>
50<TH width="25%"><A href="memory/MI_CpuSend.html" target="_self">MI_CpuSend*</A></TH>
51      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
52<TD>Sends data with fixed address.</TD>
53    </TR>
54    <TR>
55<TH width="25%"><A href="memory/MI_CpuRecv.html" target="_self">MI_CpuRecv*</A></TH>
56      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
57<TD>Reads data from a fixed address.</TD>
58    </TR>
59    <TR>
60<TH width="25%"><A href="memory/MI_CpuPipe.html" target="_self">MI_CpuPipe*</A></TH>
61      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
62<TD>Sends data from a fixed address to a fixed address.</TD>
63    </TR>
64    <TR>
65<TH width="25%"><A href="memory/MI_CpuFind.html" target="_self">MI_CpuFind*</A></TH>
66      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
67<TD>Searches through memory for the specified data.</TD>
68    </TR>
69    <TR>
70<TH width="25%"><A href="memory/MI_CpuComp.html" target="_self">MI_CpuComp*</A></TH>
71      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
72<TD>Compares data.</TD>
73    </TR>
74  </TBODY>
75</TABLE>
76
77
78<H3><A name="dma">DMA Memory Operations</A></H3>
79<TABLE border="1" width="100%">
80  <TBODY>
81    <TR>
82<TH width="25%"><A href="dma/MI_DmaCopy.html" target="_self">MI_DmaCopy*</A></TH>
83      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
84<TD>Copies data.</TD>
85    </TR>
86    <TR>
87<TH width="25%"><A href="ndma/MI_NDmaCopy.html" target="_self">MI_NDmaCopy*</A></TH>
88      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
89<TD>Copies data.</TD>
90    </TR>
91    <TR>
92<TH width="25%"><A href="dma/MI_DmaFill.html" target="_self">MI_DmaFill*</A></TH>
93      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
94<TD>Fills memory with specified data.</TD>
95    </TR>
96    <TR>
97<TH width="25%"><A href="ndma/MI_NDmaFill.html" target="_self">MI_NDmaFill*</A></TH>
98      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
99<TD>Fills memory with specified data.</TD>
100    </TR>
101    <TR>
102<TH width="25%"><A href="dma/MI_DmaClear.html" target="_self">MI_DmaClear*</A></TH>
103      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
104<TD>Zero-clears memory.</TD>
105    </TR>
106    <TR>
107<TH width="25%"><A href="ndma/MI_NDmaClear.html" target="_self">MI_NDmaClear*</A></TH>
108      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
109<TD>Zero-clears memory.</TD>
110    </TR>
111    <TR>
112<TH width="25%"><A href="dma/MI_DmaSend.html" target="_self">MI_DmaSend*</A></TH>
113      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
114<TD>Sends data with fixed address.</TD>
115    </TR>
116    <TR>
117<TH width="25%"><A href="ndma/MI_NDmaSend.html" target="_self">MI_NDmaSend*</A></TH>
118      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
119<TD>Sends data with fixed address.</TD>
120    </TR>
121    <TR>
122<TH width="25%"><A href="dma/MI_DmaRecv.html" target="_self">MI_DmaRecv*</A></TH>
123      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
124<TD>Reads data from a fixed address.</TD>
125    </TR>
126    <TR>
127<TH width="25%"><A href="ndma/MI_NDmaRecv.html" target="_self">MI_NDmaRecv*</A></TH>
128      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
129<TD>Reads data from a fixed address.</TD>
130    </TR>
131    <TR>
132<TH width="25%"><A href="dma/MI_DmaPipe.html" target="_self">MI_DmaPipe*</A></TH>
133      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
134<TD>Sends data from a fixed address to a fixed address.</TD>
135    </TR>
136    <TR>
137<TH width="25%"><A href="ndma/MI_NDmaPipe.html" target="_self">MI_NDmaPipe*</A></TH>
138      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
139<TD>Sends data from a fixed address to a fixed address.</TD>
140    </TR>
141    <TR>
142<TH width="25%"><A href="dma/MI_DmaRestart.html" target="_self">MI_DmaRestart</A></TH>
143      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
144<TD>Starts DMA once it has been configured.</TD>
145    </TR>
146    <TR>
147<TH width="25%"><A href="ndma/MI_NDmaRestart.html" target="_self">MI_NDmaRestart</A></TH>
148      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
149<TD>Starts DMA once it has been configured.</TD>
150    </TR>
151 <TR><TD class="separator" colspan=3></TD></TR>
152    <TR>
153<TH width="25%"><A href="dma/MI_HBlankDmaCopy.html" target="_self">MI_HBlankDmaCopy*</A></TH>
154      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
155<TD>Uses H-Blank DMA to copy data.</TD>
156    </TR>
157    <TR>
158<TH width="25%"><A href="ndma/MI_HBlankNDmaCopy.html" target="_self">MI_HBlankNDmaCopy*</A></TH>
159      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
160<TD>Uses H-Blank DMA to copy data.</TD>
161    </TR>
162    <TR>
163<TH width="25%"><A href="dma/MI_VBlankDmaCopy.html" target="_self">MI_VBlankDmaCopy*</A></TH>
164      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
165<TD>Uses V-Blank DMA to copy data.</TD>
166    </TR>
167    <TR>
168<TH width="25%"><A href="ndma/MI_VBlankNDmaCopy.html" target="_self">MI_VBlankNDmaCopy*</A></TH>
169      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
170<TD>Uses V-Blank DMA to copy data.</TD>
171    </TR>
172    <TR>
173<TH width="25%"><A href="dma/MI_DispMemDmaCopy.html" target="_self">MI_DispMemDmaCopy</A></TH>
174      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
175<TD>Sets main memory display DMA copies.</TD>
176    </TR>
177    <TR>
178<TH width="25%"><A href="dma/MI_SendGXCommand.html" target="_self">MI_SendGXCommand*</A></TH>
179      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
180<TD>Uses DMA to send geometry commands to command FIFO.</TD>
181    </TR>
182    <TR>
183<TH width="25%"><A href="ndma/MI_SendNDmaGXCommand.html" target="_self">MI_SendNDmaGXCommand*</A></TH>
184      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
185<TD>Uses DMA to send geometry commands to command FIFO.</TD>
186    </TR>
187
188    <TR>
189<TH width="25%"><A href="ndma/MI_TimerNDmaCopy.html" target="_self">MI_TimerNDmaCopy</A></TH>
190      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
191<TD>Sets up a DMA copy based on a timer startup.</TD>
192    </TR>
193    <TR>
194<TH width="25%"><A href="ndma/MI_Card_NDmaCopy.html" target="_self">MI_Card_NDmaCopy</A></TH>
195      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
196<TD>Sets up a DMA copy based on memory card transfer startup.</TD>
197    </TR>
198 <TR><TD class="separator" colspan=3></TD></TR>
199    <TR>
200<TH width="25%"><A href="dma/MI_IsDmaBusy.html" target="_self">MI_IsDmaBusy</A></TH>
201      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
202<TD>Checks whether the specified DMA channel is being used.</TD>
203    </TR>
204    <TR>
205<TH width="25%"><A href="ndma/MI_IsNDmaBusy.html" target="_self">MI_IsNDmaBusy</A></TH>
206      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
207<TD>Checks whether the specified DMA channel is being used.</TD>
208    </TR>
209    <TR>
210<TH width="25%"><A href="dma/MI_WaitDma.html" target="_self">MI_WaitDma</A></TH>
211      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
212<TD>Waits for the specified end of DMA.</TD>
213    </TR>
214    <TR>
215<TH width="25%"><A href="ndma/MI_WaitNDma.html" target="_self">MI_WaitNDma</A></TH>
216      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
217<TD>Waits for the specified end of DMA.</TD>
218    </TR>
219    <TR>
220<TH width="25%"><A href="dma/MI_StopDma.html" target="_self">MI_StopDma</A></TH>
221      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
222<TD>Stops specified DMA.</TD>
223    </TR>
224    <TR>
225<TH width="25%"><A href="ndma/MI_StopNDma.html" target="_self">MI_StopNDma</A></TH>
226      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
227<TD>Stops specified DMA.</TD>
228    </TR>
229    <TR>
230<TH width="25%"><A href="dma/MI_StopAllDma.html" target="_self">MI_StopAllDma</A></TH>
231      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
232<TD>Stops all DMA channels. (Legacy DMA)</TD>
233    </TR>
234    <TR>
235<TH width="25%"><A href="ndma/MI_StopAllNDma.html" target="_self">MI_StopAllNDma</A></TH>
236      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
237<TD>Stops all DMA channels. (New DMA)</TD>
238    </TR>
239 <TR><TD class="separator" colspan=3></TD></TR>
240    <TR>
241<TH width="25%"><A href="ndma/MI_SetNDmaArbitrament.html" target="_self">MI_SetNDmaArbitrament</A></TH>
242      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
243<TD>Sets the arbitration method for the new DMA.</TD>
244    </TR>
245    <TR>
246<TH width="25%"><A href="ndma/MI_GetNDmaArbitrament.html" target="_self">MI_GetNDmaArbitramentMode</A></TH>
247      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
248<TD>Gets the arbitration method for the new DMA.</TD>
249    </TR>
250    <TR>
251<TH width="25%"><A href="ndma/MI_GetNDmaArbitramentRoundRobinCycle.html" target="_self">MI_GetNDmaArbitramentRoundRobinCycle</A></TH>
252      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
253<TD>Gets the number of cycles that can be run on the ARM7 when the arbitration method for the new DMA is set to round-robin.</TD>
254    </TR>
255 <TR><TD class="separator" colspan=3></TD></TR>
256    <TR>
257<TH width="25%"><A href="ndma/MI_InitNDmaConfig.html" target="_self">MI_InitNDmaConfig</A></TH>
258      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
259<TD>Initializes the config structure that controls the behavior of the new DMA.</TD>
260    </TR>
261    <TR>
262<TH width="25%"><A href="ndma/MI_GetNDmaConfig.html" target="_self">MI_GetNDmaConfig</A></TH>
263      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
264<TD>Gets the config structure for the new DMA.</TD>
265    </TR>
266    <TR>
267<TH width="25%"><A href="ndma/MI_SetNDmaConfig.html" target="_self">MI_SetNDmaConfig</A></TH>
268      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
269<TD>Sets the config structure for the new DMA.</TD>
270    </TR>
271    <TR>
272<TH width="25%"><A href="ndma/MI_SetNDmaInterval.html" target="_self">MI_SetNDmaInterval</A></TH>
273      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
274<TD>Sets the Interval information for the specified config structure.</TD>
275    </TR>
276    <TR>
277<TH width="25%"><A href="ndma/MI_GetNDmaIntervalTimer.html" target="_self">MI_GetNDmaIntervalTimer</A></TH>
278      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
279<TD>Gets the IntervalTimer information for the specified config structure.</TD>
280    </TR>
281    <TR>
282<TH width="25%"><A href="ndma/MI_GetNDmaIntervalPrescaler.html" target="_self">MI_GetNDmaIntervalPrescaler</A></TH>
283      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
284<TD>Gets the IntervalPrescaler information for the specified config structure.</TD>
285    </TR>
286    <TR>
287<TH width="25%"><A href="ndma/MI_SetNDmaBlockWord.html" target="_self">MI_SetNDmaBlockWord</A></TH>
288      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
289<TD>Gets the BlockWord information for the specified config structure.</TD>
290    </TR>
291    <TR>
292<TH width="25%"><A href="ndma/MI_GetNDmaBlockWord.html" target="_self">MI_GetNDmaBlockWord</A></TH>
293      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
294<TD>Gets the BlockWord information for the specified config structure.</TD>
295    </TR>
296    <TR>
297<TH width="25%"><A href="ndma/MI_SetNDmaWordCount.html" target="_self">MI_SetNDmaWordCount</A></TH>
298      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
299<TD>Sets the WordCount information for the specified config structure.</TD>
300    </TR>
301    <TR>
302<TH width="25%"><A href="ndma/MI_GetNDmaWordCount.html" target="_self">MI_GetNDmaWordCount</A></TH>
303      <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
304<TD>Gets the WordCount information for the specified config structure.</TD>
305    </TR>
306  </TBODY>
307</TABLE>
308
309<H3><A name="exMemory">External Memory Control</A></H3>
310<TABLE border="1" width="100%">
311  <TBODY>
312    <TR>
313<TH width="25%"><A href="exmemory/MI_SetMainMemoryPriority.html" target="_self">MI_SetMainMemoryPriority</A></TH>
314      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
315<TD>Sets access priority to main memory.</TD>
316    </TR>
317    <TR>
318<TH width="25%"><A href="exmemory/MI_GetMainMemoryPriority.html" target="_self">MI_GetMainMemoryPriority</A></TH>
319      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
320<TD>Gets settings for access priority to main memory.</TD>
321    </TR>
322
323    <TR>
324<TH width="25%"><A href="exmemory/MI_GetCardProcessor.html" target="_self">MI_GetCardProcessor</A></TH>
325      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
326<TD>Gets settings for access rights to card.</TD>
327    </TR>
328
329    <TR>
330<TH width="25%"><A href="exmemory/MI_GetCartridgeProcessor.html" target="_self">MI_GetCartridgeProcessor</A></TH>
331      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
332<TD>Gets settings for access rights to Game Pak.</TD>
333    </TR>
334    <TR>
335<TH width="25%"><A href="exmemory/MI_SetCartridgeRomCycle1st.html" target="_self">MI_SetCartridgeRomCycle1st</A></TH>
336      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
337<TD>Sets the first access cycle to the Game Pak ROM region.</TD>
338    </TR>
339    <TR>
340<TH width="25%"><A href="exmemory/MI_GetCartridgeRomCycle1st.html" target="_self">MI_GetCartridgeRomCycle1st</A></TH>
341      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
342<TD>Gets the settings for the first access cycle to the Game Pak ROM region.</TD>
343    </TR>
344    <TR>
345<TH width="25%"><A href="exmemory/MI_SetCartridgeRomCycle2nd.html" target="_self">MI_SetCartridgeRomCycle2nd</A></TH>
346      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
347<TD>Sets the second access cycle to the Game Pak ROM region.</TD>
348    </TR>
349    <TR>
350<TH width="25%"><A href="exmemory/MI_GetCartridgeRomCycle2nd.html" target="_self">MI_GetCartridgeRomCycle2nd</A></TH>
351      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
352<TD>Gets the setting for the second access cycle to access the Game Pak's ROM region.</TD>
353    </TR>
354    <TR>
355<TH width="25%"><A href="exmemory/MI_SetCartridgeRamCycle.html" target="_self">MI_SetCartridgeRamCycle</A></TH>
356      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
357<TD>Sets the access cycle to the Game Pak RAM region.</TD>
358    </TR>
359    <TR>
360<TH width="25%"><A href="exmemory/MI_GetCartridgeRamCycle.html" target="_self">MI_GetCartridgeRamCycle</A></TH>
361      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
362<TD>Gets the settings for the access cycle to the Game Pak RAM region.</TD>
363    </TR>
364    <TR>
365<TH width="25%"><A href="exmemory/MI_SetAgbCartridgeFastestRomCycle.html" target="_self">MI_SetAgbCartridgeFastestRomCycle</A></TH>
366      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
367<TD>Sets the high-speed access cycle to the AGB Game Pak ROM region.</TD>
368    </TR>
369  </TBODY>
370</TABLE>
371
372
373<H3><A name="wram">Work RAM Settings</A></H3>
374<TABLE border="1" width="100%">
375  <TBODY>
376    <TR>
377<TH width="25%"><A href="wram/MI_SetWramBank.html" target="_self"><font color="#808080">MI_SetWramBank</font></A></TH>
378      <TD width="48"><img src="../image/BPT.gif"><img src="../image/BPT.gif"></TD>
379
380<TD><font color="#808080">This function is only used by the system.</font></TD>
381    </TR>
382    <TR>
383      <TD class="separator" colspan=3></TD>
384    </TR>
385    <TR>
386<TH width="25%"><A href="wram/MI_GetWramBankMaster.html" target="_self">MI_GetWramBankMaster*</A></TH>
387      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
388<TD>Gets the master processor assigned to the shared WRAM (256 KB x 3).</TD>
389    </TR>
390    <TR>
391<TH width="25%"><A href="wram/MI_GetWramBankOffset.html" target="_self">MI_GetWramBankOffset*</A></TH>
392      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
393<TD>Gets the offset position of the shared WRAM (256 KB x 3) banks.</TD>
394    </TR>
395    <TR>
396<TH width="25%"><A href="wram/MI_GetWramBankEnable.html" target="_self">MI_GetWramBankEnable*</A></TH>
397      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
398<TD>Gets whether the banks in the shared WRAM (256 KB x 3) can be used.</TD>
399    </TR>
400    <TR>
401<TH width="25%"><A href="wram/MI_GetWramMapStart.html" target="_self">MI_GetWramMapStart*</A></TH>
402      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
403<TD>Gets the starting address of the shared WRAM (256 KB x 3).</TD>
404    </TR>
405    <TR>
406<TH width="25%"><A href="wram/MI_GetWramMapEnd.html" target="_self">MI_GetWramMapEnd*</A></TH>
407      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
408<TD>Gets the ending address of the shared WRAM (256 KB x 3).</TD>
409    </TR>
410    <TR>
411<TH width="25%"><A href="wram/MI_GetWramMapImage.html" target="_self">MI_GetWramMapImage*</A></TH>
412      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
413<TD>Gets the image occurrence setting of the shared WRAM (256 KB x 3).</TD>
414    </TR>
415    <TR>
416<TH width="25%"><A href="wram/MI_IsWramSlotLocked.html" target="_self">MI_IsWramSlotLocked*</A></TH>
417      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
418<TD>Determines whether the shared WRAM (256 KB x 3) slots are locked.</TD>
419    </TR>
420    <TR>
421      <TD class="separator" colspan=3></TD>
422    </TR>
423    <TR>
424<TH width="25%"><A href="wram/MI_GetAllocatableWramSlot.html" target="_self">MI_GetAllocatableWramSlot*</A></TH>
425      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
426<TD>Gets which slots in the shared WRAM (256 KB x 3) can be allocated by the specified processor.</TD>
427    </TR>
428    <TR>
429<TH width="25%"><A href="wram/MI_GetFreeWramSlot.html" target="_self">MI_GetFreeWramSlot*</A></TH>
430      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
431<TD>Gets which slots in the shared WRAM (256 KB x 3) are neither reserved nor assigned.</TD>
432    </TR>
433    <TR>
434<TH width="25%"><A href="wram/MI_GetUsedWramSlot.html" target="_self">MI_GetUsedWramSlot*</A></TH>
435      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
436<TD>Gets which slots in the shared WRAM (256 KB x 3) are assigned.</TD>
437    </TR>
438    <TR>
439<TH width="25%"><A href="wram/MI_GetWramReservation.html" target="_self">MI_GetWramReservation*</A></TH>
440      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
441<TD>Gets the processor that has reserved the shared WRAM (256 KB x 3) slot.</TD>
442    </TR>
443    <TR>
444<TH width="25%"><A href="wram/MI_IsWramSlotUsed.html" target="_self">MI_IsWramSlotUsed*</A></TH>
445      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
446<TD>Gets whether the shared WRAM (256 KB x 3) slots are assigned.</TD>
447    </TR>
448    <TR>
449 <TD class="separator" colspan=3></TD>
450    </TR>
451    <TR>
452<TH width="25%"><A href="wram/MI_InitWramManager.html" target="_self">MI_InitWramManager</A></TH>
453      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
454<TD>Initializes the shared WRAM (256 KB x 3) manager.</TD>
455    </TR>
456    <TR>
457<TH width="25%"><A href="wram/MI_AllocWram.html" target="_self">MI_AllocWram*</A></TH>
458      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
459<TD>Makes a request for WRAM assignment to the shared WRAM (256 KB x 3) manager.</TD>
460    </TR>
461    <TR>
462<TH width="25%"><A href="wram/MI_FreeWram.html" target="_self">MI_FreeWram*</A></TH>
463      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
464<TD>Sends a request to the shared WRAM (256 KB x 3) manager to free some WRAM.</TD>
465    </TR>
466    <TR>
467<TH width="25%"><A href="wram/MI_SwitchWram.html" target="_self">MI_SwitchWram*</A></TH>
468      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
469<TD>Notifies the shared WRAM (256 KB x 3) manager of changes to the assigned WRAM master.</TD>
470    </TR>
471    <TR>
472<TH width="25%"><A href="wram/MI_ReserveWram.html" target="_self">MI_ReserveWram*</A></TH>
473      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
474<TD>Notifies the shared WRAM manager (256 KB x 3) of a reservation of WRAM by a processor.</TD>
475    </TR>
476    <TR>
477<TH width="25%"><A href="wram/MI_CancelWram.html" target="_self">MI_CancelWram*</A></TH>
478      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
479<TD>Notifies the shared WRAM manager (256 KB x 3) of a cancelled reservation of WRAM by a processor.</TD>
480    </TR>
481    <TR>
482      <TD class="separator" colspan=3></TD>
483    </TR>
484    <TR>
485<TH width="25%"><A href="wram/MI_DumpWramList.html" target="_self">MI_DumpWramList*</A></TH>
486      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
487<TD>Displays the WRAM assignment status maintained by the WRAM (256 KB x 3) manager for a given WRAM region.</TD>
488    </TR>
489    <TR>
490<TH width="25%"><A href="wram/MI_DumpWramList.html" target="_self">MI_DumpWramListAll</A></TH>
491      <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
492<TD>Displays the WRAM assignment status maintained by the WRAM (256 KB x 3) manager for all WRAM regions.</TD>
493    </TR>
494  </TBODY>
495</TABLE>
496
497
498<H3><A name="swap">Memory Swap</A></H3>
499
500<TABLE border="1" width="100%">
501  <TBODY>
502    <TR>
503<TH width="25%"><A href="swap/MI_Swap.html" target="_self">MI_SwapByte</A></TH>
504      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
505<TD>Swaps specified byte data and memory data.</TD>
506    </TR>
507    <TR>
508<TH width="25%"><A href="swap/MI_Swap.html" target="_self">MI_SwapWord</A></TH>
509      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
510<TD>Swaps specified word data and memory data.</TD>
511    </TR>
512  </TBODY>
513</TABLE>
514
515
516<H3><A name="uncompress">Expanding Compressed Data</A></H3>
517<TABLE border="1" width="100%">
518  <TBODY>
519    <TR>
520<TH width="25%"><A href="uncompress/MI_UnpackBits.html" target="_self">MI_UnpackBits</A></TH>
521      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
522<TD>Expands the data filled with fixed 0.</TD>
523    </TR>
524    <TR>
525<TH width="25%"><A href="uncompress/MI_UncompressLZ.html" target="_self">MI_UncompressLZ8</A></TH>
526      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
527<TD>Expands the LZ77-compressed data in 8-bit units.</TD>
528    </TR>
529    <TR>
530<TH width="25%"><A href="uncompress/MI_UncompressLZ.html" target="_self">MI_UncompressLZ16</A></TH>
531      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
532<TD>Expands the LZ77-compressed data in 16-bit units.</TD>
533    </TR>
534    <TR>
535<TH width="25%"><A href="uncompress/MI_UncompressHuffman.html" target="_self">MI_UncompressHuffman</A></TH>
536      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
537<TD>Expands Huffman-compressed data in 32-bit units.</TD>
538    </TR>
539    <TR>
540<TH width="25%"><A href="uncompress/MI_UncompressRL.html" target="_self">MI_UncompressRL8</A></TH>
541      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
542<TD>Expands run-length compressed data in 8-bit units.</TD>
543    </TR>
544    <TR>
545<TH width="25%"><A href="uncompress/MI_UncompressRL.html" target="_self">MI_UncompressRL16</A></TH>
546      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
547<TD>Expands run-length compressed data in 16-bit units.</TD>
548    </TR>
549    <TR>
550<TH width="25%"><A href="uncompress/MI_UncompressRL.html" target="_self">MI_UncompressRL32</A></TH>
551      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
552<TD>Expands run-length compressed data in 32-bit units.</TD>
553    </TR>
554    <TR>
555<TH><A href="uncompress/MI_UnfilterDiff.html" target="_self">MI_UnfilterDiff8</A></TH>
556      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
557<TD>Expands the data that the difference filter was applied to in 8-bit units.</TD>
558    </TR>
559    <TR>
560<TH><A href="uncompress/MI_UnfilterDiff.html" target="_self">MI_UnfilterDiff16</A></TH>
561      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
562<TD>Expands the data that the difference filter was applied to in 16-bit units.</TD>
563    </TR>
564    <TR>
565<TH><A href="uncompress/MI_UnfilterDiff.html" target="_self">MI_UnfilterDiff32</A></TH>
566      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
567<TD>Expands the data that the difference filter was applied to in 32-bit units.</TD>
568    </TR>
569    <TR>
570<TH><A href="uncompress/MI_SecureUncompressAny.html" target="_self">MI_SecureUncompressAny</A></TH>
571      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
572<TD>Detects the compression format from the data header and executes the appropriate decompression process. (Includes buffer overrun check.)</TD>
573    </TR>
574    <TR>
575<TH><A href="uncompress/MI_SecureUncompressRL.html" target="_self">MI_SecureUncompressRL</A></TH>
576      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
577<TD>Decompresses run-length compressed data once. (Includes buffer overrun check.)</TD>
578    </TR>
579    <TR>
580<TH><A href="uncompress/MI_SecureUncompressLZ.html" target="_self">MI_SecureUncompressLZ</A></TH>
581      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
582<TD>Decompresses LZ77-compressed data once. (Includes buffer overrun check.)</TD>
583    </TR>
584    <TR>
585<TH><A href="uncompress/MI_SecureUncompressBLZ.html" target="_self">MI_SecureUncompressBLZ</A></TH>
586      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
587<TD>Decompresses BLZ-compressed data once. (Includes buffer overrun check.)</TD>
588    </TR>
589    <TR>
590<TH><A href="uncompress/MI_SecureUncompressHuffman.html" target="_self">MI_SecureUncompressHuffman</A></TH>
591      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
592<TD>Decompresses Huffman-compressed data once. (Includes buffer overrun check.)</TD>
593    </TR>
594    <TR>
595<TH><A href="uncompress/MI_SecureUnfilterDiff.html" target="_self">MI_SecureUnfilterDiff</A></TH>
596      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
597<TD>Decompresses data that a difference filter has been applied to. (Includes buffer overrun check.)</TD>
598    </TR>
599    <TR>
600<TH><A href="uncompress/MI_GetUncompressedSize.html" target="_self">MI_GetUncompressedSize</A></TH>
601      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
602<TD>Gets the size of the expanded data.</TD>
603    </TR>
604    <TR>
605<TH><A href="uncompress/MI_GetCompressionType.html" target="_self">MI_GetCompressionType</A></TH>
606      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
607<TD>Gets the compression format of the compressed data.</TD>
608    </TR>
609    <TR>
610<TH><A href="uncompress/MI_InitUncompContextRL.html" target="_self">MI_InitUncompContextRL</A></TH>
611      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
612<TD>Initializes run-length compression streaming decode context.</TD>
613    </TR>
614    <TR>
615<TH><A href="uncompress/MI_InitUncompContextLZ.html" target="_self">MI_InitUncompContextLZ</A></TH>
616      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
617<TD>Initializes LZ77 compression streaming decode context.</TD>
618    </TR>
619    <TR>
620<TH><A href="uncompress/MI_InitUncompContextHuffman.html" target="_self">MI_InitUncompContextHuffman</A></TH>
621      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
622<TD>Initializes the Huffman compression streaming decode context.</TD>
623    </TR>
624    <TR>
625<TH><A href="uncompress/MI_ReadUncompRL.html" target="_self">MI_ReadUncompRL*</A></TH>
626      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
627<TD>Runs run-length compression streaming decoding.</TD>
628    </TR>
629    <TR>
630<TH><A href="uncompress/MI_ReadUncompLZ.html" target="_self">MI_ReadUncompLZ*</A></TH>
631      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
632<TD>Runs LZ77-compression streaming decoding.</TD>
633    </TR>
634    <TR>
635<TH><A href="uncompress/MI_ReadUncompHuffman.html" target="_self">MI_ReadUncompHuffman</A></TH>
636      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
637<TD>Runs Huffman compression streaming decoding.</TD>
638    </TR>
639    <TR>
640<TH><A href="uncompress/MI_CompressRL.html" target="_self">MI_CompressRL</A></TH>
641      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
642<TD>Performs run-length compression on the data.</TD>
643    </TR>
644    <TR>
645<TH><A href="uncompress/MI_CompressLZ.html" target="_self">MI_CompressLZ</A></TH>
646      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
647<TD>Performs LZ77 compression on the data.</TD>
648    </TR>
649    <TR>
650<TH><A href="uncompress/MI_CompressLZ.html" target="_self">MI_CompressLZFast</A></TH>
651      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
652<TD>Performs LZ77 compression on the data. Processing is performed rather quickly in exchange for requiring a work buffer.</TD>
653    </TR>
654    <TR>
655<TH><A href="uncompress/MI_CompressHuffman.html" target="_self">MI_CompressHuffman</A></TH>
656      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
657<TD>Performs Huffman compression on the data.</TD>
658    </TR>
659    <TR>
660<TH><A href="uncompress/MI_FilterDiff.html" target="_self">MI_FilterDiff*</A></TH>
661      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
662<TD>Creates data that a difference filter has been applied to.</TD>
663    </TR>
664  </TBODY>
665</TABLE>
666
667
668
669<H3><A name="byteAccess">Byte Access</A></H3>
670<TABLE border="1" width="100%">
671  <TBODY>
672    <TR>
673<TH width="25%"><font color="gray">MI_ReadByte</font></TH>
674      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
675<TD><font color="gray">Reads the byte data from the memory.<BR>This function has been kept for compatibility. Do not use it.</font></TD>
676    </TR>
677    <TR>
678<TH width="25%"><font color="gray">MI_WriteByte</font></TH>
679      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
680<TD><font color="gray">Writes the byte data to the memory.<BR>This function has been kept for compatibility. Do not use it.</font></TD>
681    </TR>
682  </TBODY>
683</TABLE>
684
685<H3><A name="endian">Endian-Aware Memory Access</A></H3>
686<TABLE border="1" width="100%">
687  <TBODY>
688    <TR>
689<TH width="25%"><A href="endian/MI_SwapEndian.html" target="_self">MI_SwapEndian8</A></TH>
690      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
691<TD>Reverses the endian of a 8-bit value.<br><font color="gray">These 8-bit versions do not actually perform any conversions, but they have been included for uniform source code visibility.</font></TD>
692    </TR>
693    <TR>
694<TH width="25%"><A href="endian/MI_SwapEndian.html" target="_self">MI_SwapEndian16</A></TH>
695      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
696<TD>Reverses the endian of a 16-bit value.</TD>
697    </TR>
698    <TR>
699<TH width="25%"><A href="endian/MI_SwapEndian.html" target="_self">MI_SwapEndian32</A></TH>
700      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
701<TD>Reverses the endian of a 32-bit value.</TD>
702    </TR>
703    <TR>
704<TH width="25%"><A href="endian/MI_SwapEndian.html" target="_self">MI_SwapEndian64</A></TH>
705      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
706<TD>Reverses the endian of a 64-bit value.</TD>
707    </TR>
708    <TR>
709      <TD class="separator" colspan=3></TD>
710    </TR>
711    <TR>
712<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToLE8</A></TH>
713      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
714<TD>Converts a 8-bit value from the current environment to little-endian.<br><font color="gray">These 8-bit versions do not actually perform any conversions, but they have been included for uniform source code visibility.</font></TD>
715    </TR>
716    <TR>
717<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToLE16</A></TH>
718      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
719<TD>Converts a 16-bit value from the current environment to little-endian.</TD>
720    </TR>
721    <TR>
722<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToLE32</A></TH>
723      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
724<TD>Converts a 32-bit value from the current environment to little-endian.</TD>
725    </TR>
726    <TR>
727<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToLE64</A></TH>
728      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
729<TD>Converts a 64-bit value from the current environment to little-endian.</TD>
730    </TR>
731    <TR>
732      <TD class="separator" colspan=3></TD>
733    </TR>
734    <TR>
735<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToBE8</A></TH>
736      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
737<TD>Converts a 8-bit value from the current environment to big-endian.<br><font color="gray">These 8-bit versions do not actually perform any conversions, but they have been included for uniform source code visibility.</font></TD>
738    </TR>
739    <TR>
740<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToBE16</A></TH>
741      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
742<TD>Converts a 16-bit value from the current environment to big-endian.</TD>
743    </TR>
744    <TR>
745<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToBE32</A></TH>
746      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
747<TD>Converts a 32-bit value from the current environment to big-endian.</TD>
748    </TR>
749    <TR>
750<TH width="25%"><A href="endian/MI_HTo.html" target="_self">MI_HToBE64</A></TH>
751      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
752<TD>Converts a 64-bit value from the current environment to big-endian.</TD>
753    </TR>
754    <TR>
755      <TD class="separator" colspan=3></TD>
756    </TR>
757    <TR>
758<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_LEToH8</A></TH>
759      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
760<TD>Converts a 8-bit value from little-endian to the current environment.<br><font color="gray">These 8-bit versions do not actually perform any conversions, but they have been included for uniform source code visibility.</font></TD>
761    </TR>
762    <TR>
763<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_LEToH16</A></TH>
764      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
765<TD>Converts a 16-bit value from little-endian to the current environment.</TD>
766    </TR>
767    <TR>
768<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_LEToH32</A></TH>
769      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
770<TD>Converts a 32-bit value from little-endian to the current environment.</TD>
771    </TR>
772    <TR>
773<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_LEToH64</A></TH>
774      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
775<TD>Converts a 64-bit value from little-endian to the current environment.</TD>
776    </TR>
777    <TR>
778      <TD class="separator" colspan=3></TD>
779    </TR>
780    <TR>
781<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_BEToH8</A></TH>
782      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
783<TD>Converts a 8-bit value from big-endian to the current environment.<br><font color="gray">These 8-bit versions do not actually perform any conversions, but they have been included for uniform source code visibility.</font></TD>
784    </TR>
785    <TR>
786<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_BEToH16</A></TH>
787      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
788<TD>Converts a 16-bit value from big-endian to the current environment.</TD>
789    </TR>
790    <TR>
791<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_BEToH32</A></TH>
792      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
793<TD>Converts a 32-bit value from big-endian to the current environment.</TD>
794    </TR>
795    <TR>
796<TH width="25%"><A href="endian/MI_ToH.html" target="_self">MI_BEToH64</A></TH>
797      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
798<TD>Converts a 64-bit value from big-endian to the current environment.</TD>
799    </TR>
800    <TR>
801      <TD class="separator" colspan=3></TD>
802    </TR>
803    <TR>
804<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadLE8</A></TH>
805      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
806<TD>Reads a 8-bit value from the specified address as little-endian.</TD>
807    </TR>
808    <TR>
809<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadLE16</A></TH>
810      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
811<TD>Reads a 16-bit value from the specified address as little-endian.</TD>
812    </TR>
813    <TR>
814<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadLE32</A></TH>
815      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
816<TD>Reads a 32-bit value from the specified address as little-endian.</TD>
817    </TR>
818    <TR>
819<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadLE64</A></TH>
820      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
821<TD>Reads a 64-bit value from the specified address as little-endian.</TD>
822    </TR>
823    <TR>
824      <TD class="separator" colspan=3></TD>
825    </TR>
826    <TR>
827<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadBE8</A></TH>
828      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
829<TD>Reads a 8-bit value from the specified address as big-endian.</TD>
830    </TR>
831    <TR>
832<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadBE16</A></TH>
833      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
834<TD>Reads a 16-bit value from the specified address as big-endian.</TD>
835    </TR>
836    <TR>
837<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadBE32</A></TH>
838      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
839<TD>Reads a 32-bit value from the specified address as big-endian.</TD>
840    </TR>
841    <TR>
842<TH width="25%"><A href="endian/MI_Load.html" target="_self">MI_LoadBE64</A></TH>
843      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
844<TD>Reads a 64-bit value from the specified address as big-endian.</TD>
845    </TR>
846    <TR>
847      <TD class="separator" colspan=3></TD>
848    </TR>
849    <TR>
850<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreLE8</A></TH>
851      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
852<TD>Writes a 8-bit value to the specified address as little-endian.</TD>
853    </TR>
854    <TR>
855<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreLE16</A></TH>
856      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
857<TD>Writes a 16-bit value to the specified address as little-endian.</TD>
858    </TR>
859    <TR>
860<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreLE32</A></TH>
861      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
862<TD>Writes a 32-bit value to the specified address as little-endian.</TD>
863    </TR>
864    <TR>
865<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreLE64</A></TH>
866      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
867<TD>Writes a 64-bit value to the specified address as little-endian.</TD>
868    </TR>
869    <TR>
870      <TD class="separator" colspan=3></TD>
871    </TR>
872    <TR>
873<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreBE8</A></TH>
874      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
875<TD>Writes a 8-bit value to the specified address as big-endian.</TD>
876    </TR>
877    <TR>
878<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreBE16</A></TH>
879      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
880<TD>Writes a 16-bit value to the specified address as big-endian.</TD>
881    </TR>
882    <TR>
883<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreBE32</A></TH>
884      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
885<TD>Writes a 32-bit value to the specified address as big-endian.</TD>
886    </TR>
887    <TR>
888<TH width="25%"><A href="endian/MI_Store.html" target="_self">MI_StoreBE64</A></TH>
889      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
890<TD>Writes a 64-bit value to the specified address as big-endian.</TD>
891    </TR>
892
893  </TBODY>
894</TABLE>
895
896<H3><A name="utility">Utilities</A></H3>
897<TABLE border="1" width="100%">
898  <TBODY>
899
900    <TR>
901<TH width="25%"><A href="allocator/MI_InitAllocator.html" target="_self">MI_InitAllocator</A></TH>
902      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
903<TD>Initializes the memory allocator structure.</TD>
904    </TR>
905    <TR>
906<TH width="25%"><A href="allocator/MI_CallAlloc.html" target="_self">MI_CallAlloc</A></TH>
907      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
908<TD>Allocates memory from the allocator.</TD>
909    </TR>
910    <TR>
911<TH width="25%"><A href="allocator/MI_CallFree.html" target="_self">MI_CallFree</A></TH>
912      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
913<TD>Deallocates memory back to the allocator.</TD>
914    </TR>
915    <TR>
916      <TD class="separator" colspan=3></TD>
917    </TR>
918    <TR>
919<TH width="25%"><A href="device/MI_InitDevice.html" target="_self">MI_InitDevice</A></TH>
920      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
921<TD>Initializes the device interface structure.</TD>
922    </TR>
923    <TR>
924<TH width="25%"><A href="device/MI_ReadDevice.html" target="_self">MI_ReadDevice</A></TH>
925      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
926<TD>Reads data from the device.</TD>
927    </TR>
928    <TR>
929<TH width="25%"><A href="device/MI_WriteDevice.html" target="_self">MI_WriteDevice</A></TH>
930      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
931<TD>Writes data to the device.</TD>
932    </TR>
933    <TR>
934      <TD class="separator" colspan=3></TD>
935    </TR>
936    <TR>
937<TH width="25%"><A href="cache/MI_InitCache.html" target="_self">MI_InitCache</A></TH>
938      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
939<TD>Initializes the cache structure.</TD>
940    </TR>
941    <TR>
942<TH width="25%"><A href="cache/MI_ReadCache.html" target="_self">MI_ReadCache</A></TH>
943      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
944<TD>Reads data from the cache page list.</TD>
945    </TR>
946    <TR>
947<TH width="25%"><A href="cache/MI_LoadCache.html" target="_self">MI_LoadCache</A></TH>
948      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
949<TD>Loads all pages that are in the load-wait state.</TD>
950    </TR>
951    <TR>
952<TH width="25%"><A href="cache/MI_IsCacheLoading.html" target="_self">MI_IsCacheLoading</A></TH>
953      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
954<TD>Determines whether there are any pages in the load-wait state.</TD>
955    </TR>
956
957  </TBODY>
958</TABLE>
959
960<BR>
961<H3><A name="struct">Types and Structures</A></H3>
962<TABLE border="1" width="100%">
963  <TBODY>
964    <TR>
965<TH width="25%"><A href="uncompress/MICompressionHeader.html">MICompressionHeader</A></TH>
966      <TD width="48"><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
967<TD>Compression data header information structure.</TD>
968    </TR>
969    <TR>
970<TH width="25%"><A href="uncompress/MIUncompContextRL.html" target="_self">MIUncompContextRL</A></TH>
971      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
972<TD>Context structure when using run-length compression streaming decoding.</TD>
973    </TR>
974    <TR>
975<TH><A href="uncompress/MIUncompContextLZ.html" target="_self">MIUncompContextLZ</A></TH>
976      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
977<TD>Context structure when using LZ77 compression streaming decoding.</TD>
978    </TR>
979    <TR>
980<TH><A href="uncompress/MIUncompContextHuffman.html" target="_self">MIUncompContextHuffman</A></TH>
981      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
982<TD>Context structure when using Huffman compression streaming decoding.</TD>
983    </TR>
984
985    <TR>
986<TH><A href="allocator/MIAllocator.html" target="_self">MIAllocator</A></TH>
987      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
988<TD>Initializes the memory allocator interface.</TD>
989    </TR>
990    <TR>
991<TH><A href="allocator/MIAllocatorAllocFunction.html" target="_self">MIAllocatorAllocFunction</A></TH>
992      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
993<TD>Function prototype for the memory allocation callback.</TD>
994    </TR>
995    <TR>
996<TH><A href="allocator/MIAllocatorFreeFunction.html" target="_self">MIAllocatorFreeFunction</A></TH>
997      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
998<TD>Function prototype for the memory deallocation callback.</TD>
999    </TR>
1000
1001
1002    <TR>
1003<TH><A href="device/MIDevice.html" target="_self">MIDevice</A></TH>
1004      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
1005<TD>The interface structure for wrapping device control.</TD>
1006    </TR>
1007    <TR>
1008<TH><A href="device/MIDeviceReadFunction.html" target="_self">MIDeviceReadFunction</A></TH>
1009      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
1010<TD>The function prototype for the callback for reading from the device.</TD>
1011    </TR>
1012    <TR>
1013<TH><A href="device/MIDeviceWriteFunction.html" target="_self">MIDeviceWriteFunction</A></TH>
1014      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
1015<TD>The function prototype for the callback for writing to the device.</TD>
1016    </TR>
1017    <TR>
1018<TH><A href="cache/MICache.html" target="_self">MICache</A></TH>
1019      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
1020<TD>The structure used to implement the memory cache.</TD>
1021    </TR>
1022    <TR>
1023<TH><A href="ndma/MINDmaConfig.html" target="_self">MINDmaConfig</A></TH>
1024      <TD><img src="../image/NTR.gif"><img src="../image/TWL.gif"></TD>
1025<TD>The structure used to specify the new DMA operation.</TD>
1026    </TR>
1027
1028
1029  </TBODY>
1030</TABLE>
1031
1032<table border="0" height="100%"><tr><td style="background-color : white;"></td></tr></table>
1033
1034<hr><p>CONFIDENTIAL</p></body>
1035</HTML>
1036