1 /*---------------------------------------------------------------------------* 2 Project: Dolphin GD library 3 File: GDTEV.h 4 5 Copyright 2001 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Log: GDTev.h,v $ 14 Revision 1.2 2006/02/04 11:56:46 hashida 15 (none) 16 17 Revision 1.1.1.1 2005/05/12 02:41:07 yasuh-to 18 Ported from dolphin source tree. 19 20 21 2 2001/09/21 1:48p Carl 22 Changed order of args for GDSetKonstantSel. 23 24 1 2001/09/12 1:55p Carl 25 Initial revision of GD: Graphics Display List Library. 26 27 $NoKeywords: $ 28 *---------------------------------------------------------------------------*/ 29 30 #ifndef __GDTEV_H__ 31 #define __GDTEV_H__ 32 33 /*---------------------------------------------------------------------------*/ 34 #include <revolution/types.h> 35 #include <revolution/gx/GXEnum.h> 36 #include <revolution/gx/GXStruct.h> 37 /*---------------------------------------------------------------------------*/ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /*---------------------------------------------------------------------------*/ 44 45 46 /*---------------------------------------------------------------------------*/ 47 48 void GDSetTevOp(GXTevStageID stage, GXTevMode mode); 49 50 void GDSetTevColorCalc( 51 GXTevStageID stage, 52 GXTevColorArg a, 53 GXTevColorArg b, 54 GXTevColorArg c, 55 GXTevColorArg d, 56 GXTevOp op, 57 GXTevBias bias, 58 GXTevScale scale, 59 GXBool clamp, 60 GXTevRegID out_reg ); 61 62 void GDSetTevAlphaCalcAndSwap( 63 GXTevStageID stage, 64 GXTevAlphaArg a, 65 GXTevAlphaArg b, 66 GXTevAlphaArg c, 67 GXTevAlphaArg d, 68 GXTevOp op, 69 GXTevBias bias, 70 GXTevScale scale, 71 GXBool clamp, 72 GXTevRegID out_reg, 73 GXTevSwapSel ras_sel, 74 GXTevSwapSel tex_sel ); 75 76 void GDSetTevColor ( GXTevRegID reg, GXColor color ); 77 void GDSetTevColorS10( GXTevRegID reg, GXColorS10 color ); 78 void GDSetTevKColor ( GXTevKColorID reg, GXColor color ); 79 80 // This function sets two stages at once: the one you specify 81 // must be an even stage number. 82 void GDSetTevKonstantSel( GXTevStageID evenStage, 83 GXTevKColorSel kcsel0, GXTevKAlphaSel kasel0, 84 GXTevKColorSel kcsel1, GXTevKAlphaSel kasel1 ); 85 86 void GDSetTevSwapModeTable( 87 GXTevSwapSel table, 88 GXTevColorChan red, 89 GXTevColorChan green, 90 GXTevColorChan blue, 91 GXTevColorChan alpha ); 92 93 // Alpha compare and Z texture select are part of the TEV unit 94 void GDSetAlphaCompare( 95 GXCompare comp0, 96 u8 ref0, 97 GXAlphaOp op, 98 GXCompare comp1, 99 u8 ref1 ); 100 101 void GDSetZTexture ( GXZTexOp op, GXTexFmt fmt, u32 bias ); 102 103 // This function sets two stages at once: the one you specify 104 // must be an even stage number. 105 void GDSetTevOrder( 106 GXTevStageID evenStage, 107 GXTexCoordID coord0, 108 GXTexMapID map0, 109 GXChannelID color0, 110 GXTexCoordID coord1, 111 GXTexMapID map1, 112 GXChannelID color1 ); 113 114 /*---------------------------------------------------------------------------*/ 115 116 // Defines for setting TEV registers... 117 118 /* 119 * tev_color_env struct 120 */ 121 #define TEV_COLOR_ENV_SELD_SHIFT 0 122 #define TEV_COLOR_ENV_SELC_SHIFT 4 123 #define TEV_COLOR_ENV_SELB_SHIFT 8 124 #define TEV_COLOR_ENV_SELA_SHIFT 12 125 #define TEV_COLOR_ENV_BIAS_SHIFT 16 126 #define TEV_COLOR_ENV_SUB_SHIFT 18 127 #define TEV_COLOR_ENV_CLAMP_SHIFT 19 128 #define TEV_COLOR_ENV_SHIFT_SHIFT 20 129 #define TEV_COLOR_ENV_DEST_SHIFT 22 130 #define TEV_COLOR_ENV_RID_SHIFT 24 131 #define TEV_COLOR_ENV(seld, selc, selb, sela, bias, sub, clamp, shift, dest, rid) \ 132 ((((unsigned long)(seld)) << TEV_COLOR_ENV_SELD_SHIFT) | \ 133 (((unsigned long)(selc)) << TEV_COLOR_ENV_SELC_SHIFT) | \ 134 (((unsigned long)(selb)) << TEV_COLOR_ENV_SELB_SHIFT) | \ 135 (((unsigned long)(sela)) << TEV_COLOR_ENV_SELA_SHIFT) | \ 136 (((unsigned long)(bias)) << TEV_COLOR_ENV_BIAS_SHIFT) | \ 137 (((unsigned long)(sub)) << TEV_COLOR_ENV_SUB_SHIFT) | \ 138 (((unsigned long)(clamp)) << TEV_COLOR_ENV_CLAMP_SHIFT) | \ 139 (((unsigned long)(shift)) << TEV_COLOR_ENV_SHIFT_SHIFT) | \ 140 (((unsigned long)(dest)) << TEV_COLOR_ENV_DEST_SHIFT) | \ 141 (((unsigned long)(rid)) << TEV_COLOR_ENV_RID_SHIFT)) 142 143 /* 144 * tev_alpha_env struct 145 */ 146 #define TEV_ALPHA_ENV_RSWAP_SHIFT 0 147 #define TEV_ALPHA_ENV_TSWAP_SHIFT 2 148 #define TEV_ALPHA_ENV_SELD_SHIFT 4 149 #define TEV_ALPHA_ENV_SELC_SHIFT 7 150 #define TEV_ALPHA_ENV_SELB_SHIFT 10 151 #define TEV_ALPHA_ENV_SELA_SHIFT 13 152 #define TEV_ALPHA_ENV_BIAS_SHIFT 16 153 #define TEV_ALPHA_ENV_SUB_SHIFT 18 154 #define TEV_ALPHA_ENV_CLAMP_SHIFT 19 155 #define TEV_ALPHA_ENV_SHIFT_SHIFT 20 156 #define TEV_ALPHA_ENV_DEST_SHIFT 22 157 #define TEV_ALPHA_ENV_RID_SHIFT 24 158 #define TEV_ALPHA_ENV(rswap, tswap, seld, selc, selb, sela, bias, sub, clamp, shift, dest, rid) \ 159 ((((unsigned long)(rswap)) << TEV_ALPHA_ENV_RSWAP_SHIFT) | \ 160 (((unsigned long)(tswap)) << TEV_ALPHA_ENV_TSWAP_SHIFT) | \ 161 (((unsigned long)(seld)) << TEV_ALPHA_ENV_SELD_SHIFT) | \ 162 (((unsigned long)(selc)) << TEV_ALPHA_ENV_SELC_SHIFT) | \ 163 (((unsigned long)(selb)) << TEV_ALPHA_ENV_SELB_SHIFT) | \ 164 (((unsigned long)(sela)) << TEV_ALPHA_ENV_SELA_SHIFT) | \ 165 (((unsigned long)(bias)) << TEV_ALPHA_ENV_BIAS_SHIFT) | \ 166 (((unsigned long)(sub)) << TEV_ALPHA_ENV_SUB_SHIFT) | \ 167 (((unsigned long)(clamp)) << TEV_ALPHA_ENV_CLAMP_SHIFT) | \ 168 (((unsigned long)(shift)) << TEV_ALPHA_ENV_SHIFT_SHIFT) | \ 169 (((unsigned long)(dest)) << TEV_ALPHA_ENV_DEST_SHIFT) | \ 170 (((unsigned long)(rid)) << TEV_ALPHA_ENV_RID_SHIFT)) 171 172 /* 173 * tev_registerl struct 174 */ 175 #define TEV_REGISTERL_R_SHIFT 0 176 #define TEV_REGISTERL_A_SHIFT 12 177 #define TEV_REGISTERL_TYPE_SHIFT 23 178 #define TEV_REGISTERL_RID_SHIFT 24 179 #define TEV_REGISTERL(r, a, t, rid) \ 180 ((((unsigned long)(r)) << TEV_REGISTERL_R_SHIFT) | \ 181 (((unsigned long)(a)) << TEV_REGISTERL_A_SHIFT) | \ 182 (((unsigned long)(t)) << TEV_REGISTERL_TYPE_SHIFT) | \ 183 (((unsigned long)(rid)) << TEV_REGISTERL_RID_SHIFT)) 184 185 /* 186 * tev_registerh struct 187 */ 188 #define TEV_REGISTERH_B_SHIFT 0 189 #define TEV_REGISTERH_G_SHIFT 12 190 #define TEV_REGISTERH_TYPE_SHIFT 23 191 #define TEV_REGISTERH_RID_SHIFT 24 192 #define TEV_REGISTERH(b, g, t, rid) \ 193 ((((unsigned long)(b)) << TEV_REGISTERH_B_SHIFT) | \ 194 (((unsigned long)(g)) << TEV_REGISTERH_G_SHIFT) | \ 195 (((unsigned long)(t)) << TEV_REGISTERH_TYPE_SHIFT) | \ 196 (((unsigned long)(rid)) << TEV_REGISTERH_RID_SHIFT)) 197 198 /* 199 * tev_alphafunc struct 200 */ 201 #define TEV_ALPHAFUNC_A0_SHIFT 0 202 #define TEV_ALPHAFUNC_A1_SHIFT 8 203 #define TEV_ALPHAFUNC_OP0_SHIFT 16 204 #define TEV_ALPHAFUNC_OP1_SHIFT 19 205 #define TEV_ALPHAFUNC_LOGIC_SHIFT 22 206 #define TEV_ALPHAFUNC_RID_SHIFT 24 207 #define TEV_ALPHAFUNC(a0, a1, op0, op1, logic, rid) \ 208 ((((unsigned long)(a0)) << TEV_ALPHAFUNC_A0_SHIFT) | \ 209 (((unsigned long)(a1)) << TEV_ALPHAFUNC_A1_SHIFT) | \ 210 (((unsigned long)(op0)) << TEV_ALPHAFUNC_OP0_SHIFT) | \ 211 (((unsigned long)(op1)) << TEV_ALPHAFUNC_OP1_SHIFT) | \ 212 (((unsigned long)(logic)) << TEV_ALPHAFUNC_LOGIC_SHIFT) | \ 213 (((unsigned long)(rid)) << TEV_ALPHAFUNC_RID_SHIFT)) 214 215 /* 216 * tev_z_env_0 struct 217 */ 218 #define TEV_Z_ENV_0_ZOFF_SHIFT 0 219 #define TEV_Z_ENV_0_RID_SHIFT 24 220 #define TEV_Z_ENV_0(zoff, rid) \ 221 ((((unsigned long)(zoff)) << TEV_Z_ENV_0_ZOFF_SHIFT) | \ 222 (((unsigned long)(rid)) << TEV_Z_ENV_0_RID_SHIFT)) 223 224 /* 225 * tev_z_env_1 struct 226 */ 227 #define TEV_Z_ENV_1_TYPE_SHIFT 0 228 #define TEV_Z_ENV_1_OP_SHIFT 2 229 #define TEV_Z_ENV_1_RID_SHIFT 24 230 #define TEV_Z_ENV_1(type, op, rid) \ 231 ((((unsigned long)(type)) << TEV_Z_ENV_1_TYPE_SHIFT) | \ 232 (((unsigned long)(op)) << TEV_Z_ENV_1_OP_SHIFT) | \ 233 (((unsigned long)(rid)) << TEV_Z_ENV_1_RID_SHIFT)) 234 235 /* 236 * tev_ksel struct 237 */ 238 #define TEV_KSEL_XRB_SHIFT 0 239 #define TEV_KSEL_XGA_SHIFT 2 240 #define TEV_KSEL_KCSEL0_SHIFT 4 241 #define TEV_KSEL_KASEL0_SHIFT 9 242 #define TEV_KSEL_KCSEL1_SHIFT 14 243 #define TEV_KSEL_KASEL1_SHIFT 19 244 #define TEV_KSEL_RID_SHIFT 24 245 #define TEV_KSEL(xrb, xga, kcsel0, kasel0, kcsel1, kasel1, rid) \ 246 ((((unsigned long)(xrb)) << TEV_KSEL_XRB_SHIFT) | \ 247 (((unsigned long)(xga)) << TEV_KSEL_XGA_SHIFT) | \ 248 (((unsigned long)(kcsel0)) << TEV_KSEL_KCSEL0_SHIFT) | \ 249 (((unsigned long)(kasel0)) << TEV_KSEL_KASEL0_SHIFT) | \ 250 (((unsigned long)(kcsel1)) << TEV_KSEL_KCSEL1_SHIFT) | \ 251 (((unsigned long)(kasel1)) << TEV_KSEL_KASEL1_SHIFT) | \ 252 (((unsigned long)(rid)) << TEV_KSEL_RID_SHIFT)) 253 254 /* 255 * ras1_tref struct 256 */ 257 #define RAS1_TREF_TI0_SHIFT 0 258 #define RAS1_TREF_TC0_SHIFT 3 259 #define RAS1_TREF_TE0_SHIFT 6 260 #define RAS1_TREF_CC0_SHIFT 7 261 #define RAS1_TREF_PAD0_SHIFT 10 262 #define RAS1_TREF_TI1_SHIFT 12 263 #define RAS1_TREF_TC1_SHIFT 15 264 #define RAS1_TREF_TE1_SHIFT 18 265 #define RAS1_TREF_CC1_SHIFT 19 266 #define RAS1_TREF_PAD1_SHIFT 22 267 #define RAS1_TREF_RID_SHIFT 24 268 #define RAS1_TREF(ti0, tc0, te0, cc0, ti1, tc1, te1, cc1, rid) \ 269 ((((unsigned long)(ti0)) << RAS1_TREF_TI0_SHIFT) | \ 270 (((unsigned long)(tc0)) << RAS1_TREF_TC0_SHIFT) | \ 271 (((unsigned long)(te0)) << RAS1_TREF_TE0_SHIFT) | \ 272 (((unsigned long)(cc0)) << RAS1_TREF_CC0_SHIFT) | \ 273 (((unsigned long)(ti1)) << RAS1_TREF_TI1_SHIFT) | \ 274 (((unsigned long)(tc1)) << RAS1_TREF_TC1_SHIFT) | \ 275 (((unsigned long)(te1)) << RAS1_TREF_TE1_SHIFT) | \ 276 (((unsigned long)(cc1)) << RAS1_TREF_CC1_SHIFT) | \ 277 (((unsigned long)(rid)) << RAS1_TREF_RID_SHIFT)) 278 279 /* 280 * TEV register addresses (BP address space) 281 */ 282 #define TEV_COLOR_ENV_0_ID 0x000000c0 283 #define TEV_ALPHA_ENV_0_ID 0x000000c1 284 #define TEV_COLOR_ENV_1_ID 0x000000c2 285 #define TEV_ALPHA_ENV_1_ID 0x000000c3 286 #define TEV_COLOR_ENV_2_ID 0x000000c4 287 #define TEV_ALPHA_ENV_2_ID 0x000000c5 288 #define TEV_COLOR_ENV_3_ID 0x000000c6 289 #define TEV_ALPHA_ENV_3_ID 0x000000c7 290 #define TEV_COLOR_ENV_4_ID 0x000000c8 291 #define TEV_ALPHA_ENV_4_ID 0x000000c9 292 #define TEV_COLOR_ENV_5_ID 0x000000ca 293 #define TEV_ALPHA_ENV_5_ID 0x000000cb 294 #define TEV_COLOR_ENV_6_ID 0x000000cc 295 #define TEV_ALPHA_ENV_6_ID 0x000000cd 296 #define TEV_COLOR_ENV_7_ID 0x000000ce 297 #define TEV_ALPHA_ENV_7_ID 0x000000cf 298 #define TEV_COLOR_ENV_8_ID 0x000000d0 299 #define TEV_ALPHA_ENV_8_ID 0x000000d1 300 #define TEV_COLOR_ENV_9_ID 0x000000d2 301 #define TEV_ALPHA_ENV_9_ID 0x000000d3 302 #define TEV_COLOR_ENV_A_ID 0x000000d4 303 #define TEV_ALPHA_ENV_A_ID 0x000000d5 304 #define TEV_COLOR_ENV_B_ID 0x000000d6 305 #define TEV_ALPHA_ENV_B_ID 0x000000d7 306 #define TEV_COLOR_ENV_C_ID 0x000000d8 307 #define TEV_ALPHA_ENV_C_ID 0x000000d9 308 #define TEV_COLOR_ENV_D_ID 0x000000da 309 #define TEV_ALPHA_ENV_D_ID 0x000000db 310 #define TEV_COLOR_ENV_E_ID 0x000000dc 311 #define TEV_ALPHA_ENV_E_ID 0x000000dd 312 #define TEV_COLOR_ENV_F_ID 0x000000de 313 #define TEV_ALPHA_ENV_F_ID 0x000000df 314 #define TEV_REGISTERL_0_ID 0x000000e0 315 #define TEV_REGISTERH_0_ID 0x000000e1 316 #define TEV_REGISTERL_1_ID 0x000000e2 317 #define TEV_REGISTERH_1_ID 0x000000e3 318 #define TEV_REGISTERL_2_ID 0x000000e4 319 #define TEV_REGISTERH_2_ID 0x000000e5 320 #define TEV_REGISTERL_3_ID 0x000000e6 321 #define TEV_REGISTERH_3_ID 0x000000e7 322 // Fog registers are in GDPixel.h 323 #define TEV_ALPHAFUNC_ID 0x000000f3 324 #define TEV_Z_ENV_0_ID 0x000000f4 325 #define TEV_Z_ENV_1_ID 0x000000f5 326 #define TEV_KSEL_0_ID 0x000000f6 327 #define TEV_KSEL_1_ID 0x000000f7 328 #define TEV_KSEL_2_ID 0x000000f8 329 #define TEV_KSEL_3_ID 0x000000f9 330 #define TEV_KSEL_4_ID 0x000000fa 331 #define TEV_KSEL_5_ID 0x000000fb 332 #define TEV_KSEL_6_ID 0x000000fc 333 #define TEV_KSEL_7_ID 0x000000fd 334 335 #define RAS1_TREF0_ID 0x00000028 336 #define RAS1_TREF1_ID 0x00000029 337 #define RAS1_TREF2_ID 0x0000002a 338 #define RAS1_TREF3_ID 0x0000002b 339 #define RAS1_TREF4_ID 0x0000002c 340 #define RAS1_TREF5_ID 0x0000002d 341 #define RAS1_TREF6_ID 0x0000002e 342 #define RAS1_TREF7_ID 0x0000002f 343 344 /* 345 * TEV register field definitions 346 */ 347 348 // TEV register type field 349 #define TEV_COLOR_REG 0 350 #define TEV_KONSTANT_REG 1 351 352 // Z-texture types (formats) 353 #define TEV_Z_TYPE_U8 0x00000000 354 #define TEV_Z_TYPE_U16 0x00000001 355 #define TEV_Z_TYPE_U24 0x00000002 356 357 // Rasterized color selections 358 #define RAS1_CC_0 0x00000000 /* Color channel 0 */ 359 #define RAS1_CC_1 0x00000001 /* Color channel 1 */ 360 #define RAS1_CC_B 0x00000005 /* Indirect texture bump alpha */ 361 #define RAS1_CC_BN 0x00000006 /* ind tex bump alpha, normalized 0-255 */ 362 #define RAS1_CC_Z 0x00000007 /* Set color value to zero */ 363 364 /*---------------------------------------------------------------------------*/ 365 #ifdef __cplusplus 366 } 367 #endif 368 369 #endif // __GDTEV_H__ 370