1 /*---------------------------------------------------------------------------*
2   Project:  Dolphin GD library
3   File:     GDIndirect.h
4 
5   Copyright 2003 Nintendo. All rights reserved.
6 
7   These coded instructions, statements, and computer programs contain
8   proprietary information of Nintendo of America Inc. and/or Nintendo
9   Company Ltd., and are protected by Federal copyright law.  They may
10   not be disclosed to third parties or copied or duplicated in any form,
11   in whole or in part, without the prior written consent of Nintendo.
12 
13   $Log: GDIndirect.h,v $
14   Revision 1.2  2006/02/04 11:56:46  hashida
15   (none)
16 
17   Revision 1.1.1.1  2005/05/12 02:41:07  yasuh-to
18   Ported from dolphin source tree.
19 
20 
21     2     2003/02/19 17:37 Hirose
22 
23     1     2003/02/03 14:04 Hirose
24     Initial check in.
25 
26   $NoKeywords: $
27  *---------------------------------------------------------------------------*/
28 
29 #ifndef __GDINDIRECT_H__
30 #define __GDINDIRECT_H__
31 
32 /*---------------------------------------------------------------------------*/
33 #include <revolution/types.h>
34 #include <revolution/gx/GXEnum.h>
35 #include <revolution/gx/GXStruct.h>
36 /*---------------------------------------------------------------------------*/
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 /*---------------------------------------------------------------------------*/
43 
44 
45 /*---------------------------------------------------------------------------*/
46 void GDSetTevIndirect (
47     GXTevStageID        tev_stage,
48     GXIndTexStageID     ind_stage,
49     GXIndTexFormat      format,
50     GXIndTexBiasSel     bias_sel,
51     GXIndTexMtxID       matrix_sel,
52     GXIndTexWrap        wrap_s,
53     GXIndTexWrap        wrap_t,
54     GXBool              add_prev,
55     GXBool              utc_lod,
56     GXIndTexAlphaSel    alpha_sel );
57 
58 void GDSetIndTexMtx (
59     GXIndTexMtxID       mtx_id,
60     const f32           offset[2][3],
61     s8                  scale_exp );
62 
63 void GDSetIndTexCoordScale (
64     GXIndTexStageID     indStageEven,
65     GXIndTexScale       scaleS0,
66     GXIndTexScale       scaleT0,
67     GXIndTexScale       scaleS1,
68     GXIndTexScale       scaleT1 );
69 
70 void GDSetIndTexOrder (
71     GXTexCoordID        texCoord0,
72     GXTexMapID          texMap0,
73     GXTexCoordID        texCoord1,
74     GXTexMapID          texMap1,
75     GXTexCoordID        texCoord2,
76     GXTexMapID          texMap2,
77     GXTexCoordID        texCoord3,
78     GXTexMapID          texMap3 );
79 
80 /*---------------------------------------------------------------------------*/
81 void GDSetTevDirect ( GXTevStageID tev_stage );
82 
83 void GDSetTevIndWarp (
84     GXTevStageID        tev_stage,
85     GXIndTexStageID     ind_stage,
86     GXBool              signed_offset,
87     GXBool              replace_mode,
88     GXIndTexMtxID       matrix_sel );
89 
90 void GDSetTevIndTile (
91     GXTevStageID        tev_stage,
92     GXIndTexStageID     ind_stage,
93     u16                 tilesize_s,
94     u16                 tilesize_t,
95     u16                 tilespacing_s,
96     u16                 tilespacing_t,
97     GXIndTexFormat      format,
98     GXIndTexMtxID       matrix_sel,
99     GXIndTexBiasSel     bias_sel,
100     GXIndTexAlphaSel    alpha_sel );
101 
102 void GDSetTevIndBumpST (
103     GXTevStageID        tev_stage,
104     GXIndTexStageID     ind_stage,
105     GXIndTexMtxID       matrix_sel );
106 
107 void GDSetTevIndBumpXYZ (
108     GXTevStageID        tev_stage,
109     GXIndTexStageID     ind_stage,
110     GXIndTexMtxID       matrix_sel );
111 
112 void GDSetTevIndRepeat ( GXTevStageID tev_stage );
113 
114 /*---------------------------------------------------------------------------*/
115 void __GDSetIndTexMask ( u32 mask );
116 
117 /*---------------------------------------------------------------------------*/
118 
119 // Defines for setting BUMP(Indirect Texture) registers...
120 
121 /*
122  *  ind_mtxa struct
123  */
124 #define IND_MTXA_MA_SHIFT	0
125 #define IND_MTXA_MB_SHIFT	11
126 #define IND_MTXA_S_SHIFT	22
127 #define IND_MTXA_RID_SHIFT	24
128 #define IND_MTXA(ma, mb, s, rid) \
129 	((((unsigned long)(ma)) << IND_MTXA_MA_SHIFT) | \
130 	 (((unsigned long)(mb)) << IND_MTXA_MB_SHIFT) | \
131 	 (((unsigned long)(s)) << IND_MTXA_S_SHIFT) | \
132 	 (((unsigned long)(rid)) << IND_MTXA_RID_SHIFT))
133 
134 /*
135  *  ind_mtxb struct
136  */
137 #define IND_MTXB_MC_SHIFT	0
138 #define IND_MTXB_MD_SHIFT	11
139 #define IND_MTXB_S_SHIFT	22
140 #define IND_MTXB_RID_SHIFT	24
141 #define IND_MTXB(mc, md, s, rid) \
142 	((((unsigned long)(mc)) << IND_MTXB_MC_SHIFT) | \
143 	 (((unsigned long)(md)) << IND_MTXB_MD_SHIFT) | \
144 	 (((unsigned long)(s)) << IND_MTXB_S_SHIFT) | \
145 	 (((unsigned long)(rid)) << IND_MTXB_RID_SHIFT))
146 
147 /*
148  *  ind_mtxc struct
149  */
150 #define IND_MTXC_ME_SHIFT	0
151 #define IND_MTXC_MF_SHIFT	11
152 #define IND_MTXC_S_SHIFT	22
153 #define IND_MTXC_RID_SHIFT	24
154 #define IND_MTXC(me, mf, s, rid) \
155 	((((unsigned long)(me)) << IND_MTXC_ME_SHIFT) | \
156 	 (((unsigned long)(mf)) << IND_MTXC_MF_SHIFT) | \
157 	 (((unsigned long)(s)) << IND_MTXC_S_SHIFT) | \
158 	 (((unsigned long)(rid)) << IND_MTXC_RID_SHIFT))
159 
160 /*
161  *  ind_cmd struct
162  */
163 #define IND_CMD_BT_SHIFT	0
164 #define IND_CMD_FMT_SHIFT	2
165 #define IND_CMD_BIAS_SHIFT	4
166 #define IND_CMD_BS_SHIFT	7
167 #define IND_CMD_M_SHIFT	9
168 #define IND_CMD_SW_SHIFT	13
169 #define IND_CMD_TW_SHIFT	16
170 #define IND_CMD_LB_SHIFT	19
171 #define IND_CMD_FB_SHIFT	20
172 #define IND_CMD_PAD0_SHIFT	21
173 #define IND_CMD_RID_SHIFT	24
174 #define IND_CMD(bt, fmt, bias, bs, m, sw, tw, lb, fb, rid) \
175 	((((unsigned long)(bt)) << IND_CMD_BT_SHIFT) | \
176 	 (((unsigned long)(fmt)) << IND_CMD_FMT_SHIFT) | \
177 	 (((unsigned long)(bias)) << IND_CMD_BIAS_SHIFT) | \
178 	 (((unsigned long)(bs)) << IND_CMD_BS_SHIFT) | \
179 	 (((unsigned long)(m)) << IND_CMD_M_SHIFT) | \
180 	 (((unsigned long)(sw)) << IND_CMD_SW_SHIFT) | \
181 	 (((unsigned long)(tw)) << IND_CMD_TW_SHIFT) | \
182 	 (((unsigned long)(lb)) << IND_CMD_LB_SHIFT) | \
183 	 (((unsigned long)(fb)) << IND_CMD_FB_SHIFT) | \
184 	 (((unsigned long)(rid)) << IND_CMD_RID_SHIFT))
185 
186 /*
187  *  ind_imask struct
188  */
189 #define IND_IMASK_IMASK_SHIFT	0
190 #define IND_IMASK_RID_SHIFT	24
191 #define IND_IMASK(imask, rid) \
192 	((((unsigned long)(imask)) << IND_IMASK_IMASK_SHIFT) | \
193 	 (((unsigned long)(rid)) << IND_IMASK_RID_SHIFT))
194 
195 /*
196  *  ras1_ss struct
197  */
198 #define RAS1_SS_SS0_SHIFT	0
199 #define RAS1_SS_TS0_SHIFT	4
200 #define RAS1_SS_SS1_SHIFT	8
201 #define RAS1_SS_TS1_SHIFT	12
202 #define RAS1_SS_RID_SHIFT	24
203 #define RAS1_SS(ss0, ts0, ss1, ts1, rid) \
204 	((((unsigned long)(ss0)) << RAS1_SS_SS0_SHIFT) | \
205 	 (((unsigned long)(ts0)) << RAS1_SS_TS0_SHIFT) | \
206 	 (((unsigned long)(ss1)) << RAS1_SS_SS1_SHIFT) | \
207 	 (((unsigned long)(ts1)) << RAS1_SS_TS1_SHIFT) | \
208 	 (((unsigned long)(rid)) << RAS1_SS_RID_SHIFT))
209 
210 /*
211  *  ras1_iref struct
212  */
213 #define RAS1_IREF_BI0_SHIFT	0
214 #define RAS1_IREF_BC0_SHIFT	3
215 #define RAS1_IREF_BI1_SHIFT	6
216 #define RAS1_IREF_BC1_SHIFT	9
217 #define RAS1_IREF_BI2_SHIFT	12
218 #define RAS1_IREF_BC2_SHIFT	15
219 #define RAS1_IREF_BI3_SHIFT	18
220 #define RAS1_IREF_BC3_SHIFT	21
221 #define RAS1_IREF_RID_SHIFT	24
222 #define RAS1_IREF(bi0, bc0, bi1, bc1, bi2, bc2, bi3, bc3, rid) \
223 	((((unsigned long)(bi0)) << RAS1_IREF_BI0_SHIFT) | \
224 	 (((unsigned long)(bc0)) << RAS1_IREF_BC0_SHIFT) | \
225 	 (((unsigned long)(bi1)) << RAS1_IREF_BI1_SHIFT) | \
226 	 (((unsigned long)(bc1)) << RAS1_IREF_BC1_SHIFT) | \
227 	 (((unsigned long)(bi2)) << RAS1_IREF_BI2_SHIFT) | \
228 	 (((unsigned long)(bc2)) << RAS1_IREF_BC2_SHIFT) | \
229 	 (((unsigned long)(bi3)) << RAS1_IREF_BI3_SHIFT) | \
230 	 (((unsigned long)(bc3)) << RAS1_IREF_BC3_SHIFT) | \
231 	 (((unsigned long)(rid)) << RAS1_IREF_RID_SHIFT))
232 
233 /*
234  *  BUMP(Indirect Texture) register addresses (BP address space)
235  */
236 
237 #define IND_MTXA0_ID    0x00000006
238 #define IND_MTXB0_ID    0x00000007
239 #define IND_MTXC0_ID    0x00000008
240 #define IND_MTXA1_ID    0x00000009
241 #define IND_MTXB1_ID    0x0000000a
242 #define IND_MTXC1_ID    0x0000000b
243 #define IND_MTXA2_ID    0x0000000c
244 #define IND_MTXB2_ID    0x0000000d
245 #define IND_MTXC2_ID    0x0000000e
246 #define IND_IMASK_ID    0x0000000f
247 #define IND_CMD0_ID     0x00000010
248 #define IND_CMD1_ID     0x00000011
249 #define IND_CMD2_ID     0x00000012
250 #define IND_CMD3_ID     0x00000013
251 #define IND_CMD4_ID     0x00000014
252 #define IND_CMD5_ID     0x00000015
253 #define IND_CMD6_ID     0x00000016
254 #define IND_CMD7_ID     0x00000017
255 #define IND_CMD8_ID     0x00000018
256 #define IND_CMD9_ID     0x00000019
257 #define IND_CMDA_ID     0x0000001a
258 #define IND_CMDB_ID     0x0000001b
259 #define IND_CMDC_ID     0x0000001c
260 #define IND_CMDD_ID     0x0000001d
261 #define IND_CMDE_ID     0x0000001e
262 #define IND_CMDF_ID     0x0000001f
263 
264 #define RAS1_SS0_ID     0x00000025
265 #define RAS1_SS1_ID     0x00000026
266 #define RAS1_IREF_ID    0x00000027
267 
268 
269 /*---------------------------------------------------------------------------*/
270 #ifdef __cplusplus
271 }
272 #endif
273 
274 #endif // __GDINDIRECT_H__
275