1 /*---------------------------------------------------------------------------* 2 Project: Horizon 3 File: ARMv6_reg.h 4 5 Copyright (C)2009-2012 Nintendo Co., Ltd. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Rev: 46347 $ 14 *---------------------------------------------------------------------------*/ 15 16 #ifndef NN_HW_ARM_ARMV6_REG_H_ 17 #define NN_HW_ARM_ARMV6_REG_H_ 18 19 #include <nn/hw/ARM/reg_common.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #ifndef SDK_MG20EMU 26 #ifndef SDK_NE1EMU 27 #define HW_CPU_CLOCK_ARM11 ((67028 * 1000) * 4) // A typical value is 67027964 * 4 [1/2,000,000 = an error of 1 sec in 23 days] 28 #else // SDK_NE1EMU 29 #define HW_CPU_CLOCK_ARM11 (400 * 1000 * 1000) 30 #endif // SDK_NE1EMU 31 #else // SDK_MG20EMU 32 #define HW_CPU_CLOCK_ARM11 (302 * 1000 * 1000) 33 #endif // SDK_MG20EMU 34 #define HW_CPU_CLOCK HW_CPU_CLOCK_ARM11 35 36 #if !defined(SDK_MG20EMU) && !defined(SDK_NE1EMU) 37 #define HW_ARM11_IC_SIZE 0x4000 // Inst Cache 38 #define HW_ARM11_DC_SIZE 0x4000 // Data Cache 39 #else // SDK_MG20EMU || SDK_NE1EMU 40 #define HW_ARM11_IC_SIZE 0x8000 // Inst Cache 41 #define HW_ARM11_DC_SIZE 0x8000 // Data Cache 42 #endif // SDK_MG20EMU || SDK_NE1EMU 43 #define HW_ARM11_CACHE_LINE_SIZE 32 44 45 #define HW_IC_SIZE HW_ARM11_IC_SIZE 46 #define HW_DC_SIZE HW_ARM11_DC_SIZE 47 #define HW_CACHE_LINE_SIZE HW_ARM11_CACHE_LINE_SIZE 48 49 //********************************************************************** 50 // Coprocessor Control Bits 51 //********************************************************************** 52 53 //---------------------------------------------------------------------- 54 // System Control Coprocessor 55 //---------------------------------------------------------------------- 56 57 // Register 0.0 : ID Code 58 // Register 0.1 : Cache Type 59 // Register 0.3 : TLB Type 60 61 // Register 0.5 : CPU ID 62 63 #define HW_C0_AP_CLUSTER_ID_MASK 0x00000f00 // Cluster ID 64 #define HW_C0_AP_CPU_ID_MASK 0x00000003 // CPU ID 65 66 #define HW_C0_AP_CLUSTER_ID_SFT 8 67 #define HW_C0_AP_CPU_ID_SFT 0 68 69 // Register 1.0 : Master Control 70 71 #ifdef SDK_ARMULATOR 72 #define HW_C1_0_SB1 0x00004078 // Should be 1 73 #else 74 #define HW_C1_0_SB1 0x000040f8 // Should be 1 75 #endif 76 77 #define HW_C1_FORCE_AP_BIT 0x20000000 // AP[0] used as Access Bit 78 #define HW_C1_TEX_CB_REMAP 0x10000000 // Remap registers are used for remapping 79 #define HW_C1_NMFI_FIQ 0x08000000 // FIQs behave as NMFIs 80 #define HW_C1_EXCEPT_LITTLE_ENDIAN 0x00000000 // CPSR E bit is set to 0 on taking an exception 81 #define HW_C1_EXCEPT_BIG_ENDIAN 0x02000000 // CPSR E bit is set to 1 on taking an exception 82 #define HW_C1_MMU_V6 0x00800000 // MMUv6 selected (Subpage AP bits disabled) 83 #define HW_C1_MMU_V5 0x00000000 // MMUv5 selected (Subpage AP bits enabled) 84 #define HW_C1_UNALIGN_ACCESS_ENABLE 0x00400000 // Unaligned data and mixed-endian data access enable 85 86 #define HW_C1_LD_INTERWORK_DISABLE 0x00008000 // Loads to PC do not set the T bit (ARMv4 behavior) 87 #define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // High exception vectors selected 88 #define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // Low exception vectors selected 89 #define HW_C1_IC_ENABLE 0x00001000 // Instruction Cache enabled 90 #define HW_C1_DC_ENABLE 0x00000004 // Data Cache enabled 91 92 #define HW_C1_BR_PREDICT_ENABLE 0x00000800 // Branch prediction enable 93 #define HW_C1_ROM_PROTECT_ENABLE 0x00000200 // ROM protection enable (Deprecated) 94 #define HW_C1_MMU_PROTECT_ENABLE 0x00000100 // MMU System protection enable (Deprecated) 95 #define HW_C1_ALIGN_FAULT_ENABLE 0x00000002 // Strict alignment fault checking enabled (Higher than UNALIGN) 96 #define HW_C1_MMU_ENABLE 0x00000001 // MMU enable 97 98 #define HW_C1_IC_ENABLE_SFT 12 99 #define HW_C1_DC_ENABLE_SFT 2 100 101 102 // Register 1.1 : Auxiliary Control 103 104 #define HW_C1_SMP_MODE 0x00000020 // Symmetric Multi Processing mode 105 #define HW_C1_AMP_MODE 0x00000000 // Asymmetric Multi Processing mode 106 #define HW_C1_EXCLUSIVE_L1C_L2C 0x00000010 // L1 and L2 caches are exclusive (Invalid for CTR) 107 #define HW_C1_BR_FOLDING_ENABLE 0x00000008 // Branch instruction folding enable 108 #define HW_C1_SBR_PREDICT_ENABLE 0x00000004 // Static branch prediction enable 109 #define HW_C1_DBR_PREDICT_ENABLE 0x00000002 // Dynamic branch prediction enable 110 #define HW_C1_RETURN_STACK_ENABLE 0x00000001 // Return stack enable 111 112 113 // Register 1.2 : VFP Access Permission Control 114 115 #define HW_C1_VFP_AP_PACK( vfp_float, vfp_double ) \ 116 \ 117 ( ((vfp_float) << HW_C1_AP_CP10_SFT) \ 118 | ((vfp_double) << HW_C1_AP_CP11_SFT) ) 119 120 #define HW_C1_AP_CP10_MASK 0x00300000 // Permit access to CP10 121 #define HW_C1_AP_CP11_MASK 0x00C00000 // CP11 122 123 #define HW_C1_AP_CP10_SFT 20 124 #define HW_C1_AP_CP11_SFT 22 125 126 #define HW_C1_AP_NA 0 // Access denied 127 #define HW_C1_AP_SVR 1 // Supervisor access only 128 #define HW_C1_AP_PRIV 3 // Full access 129 130 131 // Register 2.0.0/1 : MMU L1 Table Base 132 133 #define HW_C2_0_T1_BASE_MASK_MAX 0xffffff80 // Pointer to the level one translation table when Boundary = 0 or VA = 0 134 #define HW_C2_0_T1_BASE_MASK_MIN 0xffffc000 135 #define HW_C2_1_T1_BASE_MASK 0xffffc000 // when Boundary > 0 and VA > 0 136 #define HW_C2_WALK_L2C_CA_MASK 0x00000018 // L2 Cache cachable attributes for page table walking (Invalid for CTR) 137 #define HW_C2_WALK_ON_SHARED_MEM 0x00000002 // Page table walk is to shared memory 138 139 #define HW_C2_WALK_L2C_CA_SFT 3 140 141 #define HW_C2_WALK_L2C_CA_NC 0 // L2 Cache Noncachable (Invalid for CTR) 142 #define HW_C2_WALK_L2C_CA_WB_WA 1 // L2 Cache Cachable Write-Back cached, Write Allocate (Invalid for CTR) 143 144 145 // Register 2.0.2 : MMU L1 Table Boundary 146 147 #define HW_C2_V5_T1_BOUNBARY_MASK 0x00000007 // the size of the first-level translation table base boundary for MMUv5 148 149 #define HW_C2_V5_T1_BOUNBARY_16KB 0 // 16 KB 150 #define HW_C2_V5_T1_BOUNBARY_8KB 1 // 8 KB 151 #define HW_C2_V5_T1_BOUNBARY_4KB 2 // 4 KB 152 #define HW_C2_V5_T1_BOUNBARY_2KB 3 // 2 KB 153 #define HW_C2_V5_T1_BOUNBARY_1KB 4 // 1 KB 154 #define HW_C2_V5_T1_BOUNBARY_512B 5 // 512 Byte 155 #define HW_C2_V5_T1_BOUNBARY_256B 6 // 256 byte 156 #define HW_C2_V5_T1_BOUNBARY_128B 7 // 128 byte 157 158 159 // Register 3 : Domain Access Control 160 161 #define HW_C3_DOMAIN_PACK( d0, d1, d2, d3, d4, d5, d6, d7, \ 162 d8, d9, d10, d11, d12, d13, d14, d15 ) \ 163 \ 164 ( ((d0) << HW_C3_DM0_SFT) \ 165 | ((d1) << HW_C3_DM1_SFT) \ 166 | ((d2) << HW_C3_DM2_SFT) \ 167 | ((d3) << HW_C3_DM3_SFT) \ 168 | ((d4) << HW_C3_DM4_SFT) \ 169 | ((d5) << HW_C3_DM5_SFT) \ 170 | ((d6) << HW_C3_DM6_SFT) \ 171 | ((d7) << HW_C3_DM7_SFT) \ 172 | ((d8) << HW_C3_DM8_SFT) \ 173 | ((d9) << HW_C3_DM9_SFT) \ 174 | ((d10) << HW_C3_DM10_SFT) \ 175 | ((d11) << HW_C3_DM11_SFT) \ 176 | ((d12) << HW_C3_DM12_SFT) \ 177 | ((d13) << HW_C3_DM13_SFT) \ 178 | ((d14) << HW_C3_DM14_SFT) \ 179 | ((d15) << HW_C3_DM15_SFT) ) 180 181 #define HW_C3_DOMAIN_ID_SFT( no ) ( (no) * 2 ) 182 183 #define HW_C3_DM0_SFT 0 // Domain 0 184 #define HW_C3_DM1_SFT 2 // 1 185 #define HW_C3_DM2_SFT 4 // 2 186 #define HW_C3_DM3_SFT 6 // 3 187 #define HW_C3_DM4_SFT 8 // 4 188 #define HW_C3_DM5_SFT 10 // 5 189 #define HW_C3_DM6_SFT 12 // 6 190 #define HW_C3_DM7_SFT 14 // 7 191 #define HW_C3_DM8_SFT 16 // 8 192 #define HW_C3_DM9_SFT 18 // 9 193 #define HW_C3_DM10_SFT 20 // 10 194 #define HW_C3_DM11_SFT 22 // 11 195 #define HW_C3_DM12_SFT 24 // 12 196 #define HW_C3_DM13_SFT 26 // 13 197 #define HW_C3_DM14_SFT 28 // 14 198 #define HW_C3_DM15_SFT 30 // 15 199 200 #define HW_C3_DM_AP_NA 0 // Any access generates a domain fault 201 #define HW_C3_DM_AP_CLIENT 1 // Permit clients to access a domain 202 #define HW_C3_DM_AP_MANAGER 3 // Permit managers to access a domain 203 204 205 // Register 5 : Data/Instruction Fault Status 206 207 #define HW_C5_FAULT_DOMAIN_ID_MASK 0x000000f0 // Domain's specify at data fault 208 #define HW_C5_FAULT_STATUS_MASK 0x0000040f // Fault status 209 #define HW_C5_FAULT_AXI_SLVERR 0x00001000 // AXI abort marked as SLVERR 210 #define HW_C5_FAULT_AXI_DECERR 0x00000000 // DECERR 211 #define HW_C5_FAULT_WRITE 0x00000800 // Write access caused the abort 212 #define HW_C5_FAULT_READ 0x00000000 // Read access 213 214 #define HW_C5_FAULT_DOMAIN_ID_SFT 4 215 216 #define HW_C5_ALIGN_FAULT 0x001 // Alignment fault 217 #define HW_C5_ICACHE_OP_FAULT 0x004 // Instruction cache maintenance operation fault 218 #define HW_C5_SECTION_TRANS_FAULT 0x005 // Section translation fault 219 #define HW_C5_SECTION_ACCESS_FAULT 0x003 // Section access bit fault 220 #define HW_C5_SECTION_DOMAIN_FAULT 0x009 // Section domain fault 221 #define HW_C5_SECTION_AP_FAULT 0x00d // Section permission fault 222 #define HW_C5_PAGE_TRANS_FAULT 0x007 // Page translation fault 223 #define HW_C5_PAGE_ACCESS_FAULT 0x006 // Page access bit fault 224 #define HW_C5_PAGE_DOMAIN_FAULT 0x00b // Page domain fault 225 #define HW_C5_PAGE_AP_FAULT 0x00f // Page permission fault 226 227 #define HW_C5_EA1_EXT_ABORT 0x00c // First-level external abort on translation 228 #define HW_C5_EA2_EXT_ABORT 0x00e // Second-level external abort on translation 229 #define HW_C5_PRECISE_EXT_ABORT 0x008 // Precise external abort 230 #define HW_C5_IMPRECISE_EXT_ABORT 0x106 // Imprecise external abort 231 232 #define HW_C5_DEGUB_EVENT_ABORT 0x002 // Debug event abort 233 234 235 // Register 7.0 : Wait for interrupt 236 237 // Register 7.5 : Prefetch Buffer / Branch Target Cache Operation 238 239 // Register 7.10 : Data Memory Barrier / Drain Synchronization Barrier (Wait for Write Buffer Empty) 240 241 // Register 7.5/6/7/10/14 : Cache Operations 242 243 #define HW_C7_IC_MVA_MASK 0xffffffe0 // Instruction cache's modified virtual address (per 32B) 244 #define HW_C7_DC_MVA_MASK 0xffffffe0 // Data cache's modified virtual address (per 32B) 245 #define HW_C7_BC_MVA_MASK 0xfffffff8 // Modified virtual address of Branch Target Cache (per 8B) 246 247 #define HW_C7_IC_IDX_MASK 0x00001fe0 // Instruction cache's address index (per 32B) 248 #define HW_C7_DC_IDX_MASK 0x00001fe0 // Data cache's address index (per 32B) 249 #define HW_C7_CACHE_WAY_NO_MASK 0xc0000000 // Number of cache way 250 251 #define HW_C7_CACHE_IDX_SFT 5 252 #define HW_C7_CACHE_WAY_NO_SFT 30 253 254 255 // Register 7.4/8 : VA to PA operations 256 257 #define HW_C7_VA_SRC_MASK 0xfffffc00 // Virtual address (per 1KB) 258 #define HW_C7_PA_DEST_MASK 0xfffff000 // Physical address (per 4KB) 259 #define HW_C7_PA_RGT_MASK 0x000000c0 // Region Type 260 #define HW_C7_PA_L1C_CA_MASK 0x00000030 // L1 Cache attributes 261 #define HW_C7_PA_L2C_CA_MASK 0x0000000c // L2 Cache attributes (Invalid for CTR) 262 #define HW_C7_PA_SHAREABLE 0x00000100 // Shareable 263 #define HW_C7_PA_AXI_SLVERR 0x00000040 // AXI abort marked as SLVERR 264 #define HW_C7_PA_AXI_DECERR 0x00000000 // DECERR 265 #define HW_C7_PA_FSR_ALIAS_MASK 0x0000003e // Fault Status Register Alias 266 #define HW_C7_PA_ABORT 0x00000001 // Abort 267 268 #define HW_C7_PA_RGT_TYPE_SFT 6 269 #define HW_C7_PA_L1C_CA_SFT 4 270 #define HW_C7_PA_L2C_CA_SFT 2 271 #define HW_C7_PA_SHAREABLE_SFT 8 272 #define HW_C7_PA_FSR_ALIAS_SFT 1 273 274 #define HW_C7_RGT_STRONG_ORDER 0 // Strongly ordered Region 275 #define HW_C7_RGT_DEVICE 1 // Device Region 276 #define HW_C7_RGT_NORMAL 2 // Normal Region 277 278 #define HW_C7_CA_NC 0 // Noncachable 279 #define HW_C7_CA_WB_WA 1 // Write-back Write-allocate 280 #define HW_C7_CA_WT_RA 2 // Write-through Read-allocate-only 281 #define HW_C7_CA_WB_RA 3 // Write-back Read-allocate 282 283 284 // Register 8 : TLB Operations 285 286 #define HW_C8_TLB_MVA_MASK 0xfffffc00 // Modified virtual address (per 1KB) 287 #define HW_C8_TLB_ASID_MASK 0x000000ff // Application Space ID 288 289 290 // Register 9 : Data Cache Lockdown 291 292 #define HW_C9_DCL_WAY0 0x00000001 // Lockdown Way0 293 #define HW_C9_DCL_WAY1 0x00000002 // Way1 294 #define HW_C9_DCL_WAY2 0x00000004 // Way2 295 #define HW_C9_DCL_WAY3 0x00000008 // Way3 296 297 298 // Register 10.0 : TLB Lockdown 299 300 #define HW_C10_TLBL_PRESERVE 0x00000001 // Preserve bit 301 #define HW_C10_TLBL_VICTIM_MASK 0x1c000000 // Victim 302 303 #define HW_C10_TLBL_VICTIM_SFT 26 304 305 306 // Register 10.2.0 : Region Type Remap for Primary Region 307 308 #define HW_C10_PRGT_SH_ON_NML_S1 0x00080000 // Remaps shareable attribute when S = 1, for Normal regions 309 #define HW_C10_PRGT_SH_ON_NML_S0 0x00040000 // when S = 0, for Normal regions 310 #define HW_C10_PRGT_SH_ON_DEV_S1 0x00020000 // when S = 1, for Device regions 311 #define HW_C10_PRGT_SH_ON_DEV_S0 0x00010000 // when S = 0, for Device regions 312 #define HW_C10_PRGT_TCB2_000_MASK 0x0000c000 // Remaps {TEX[0], C, B} = 000 for primary region 313 #define HW_C10_PRGT_TCB_101_MASK 0x00000c00 // Remaps {TEX[0], C, B} = 101 314 #define HW_C10_PRGT_TCB_100_MASK 0x00000300 // Remaps {TEX[0], C, B} = 100 315 #define HW_C10_PRGT_TCB_011_MASK 0x000000c0 // Remaps {TEX[0], C, B} = 011 316 #define HW_C10_PRGT_TCB_010_MASK 0x00000030 // Remaps {TEX[0], C, B} = 010 317 #define HW_C10_PRGT_TCB_001_MASK 0x0000000c // Remaps {TEX[0], C, B} = 001 318 #define HW_C10_PRGT_TCB_000_MASK 0x00000003 // Remaps {TEX[0], C, B} = 000 319 320 #define HW_C10_PRGT_TCB2_000_SFT 14 321 #define HW_C10_PRGT_TCB_101_SFT 10 322 #define HW_C10_PRGT_TCB_100_SFT 8 323 #define HW_C10_PRGT_TCB_011_SFT 6 324 #define HW_C10_PRGT_TCB_010_SFT 4 325 #define HW_C10_PRGT_TCB_001_SFT 2 326 #define HW_C10_PRGT_TCB_000_SFT 0 327 328 #define HW_C10_PRGT_STRONG_ORDER 0 // Strongly ordered Region 329 #define HW_C10_PRGT_DEVICE 1 // Device Region 330 #define HW_C10_PRGT_NORMAL 2 // Normal Region 331 332 // Register 10.2.1 : Region Attribute Remap for Normal Region 333 334 #define HW_C10_NCA_L2C_TCB_111_MASK 0xc0000000 // Remaps L2 Cache attribute for normal region {TEX[0], C, B} = 111 335 #define HW_C10_NCA_L2C_TCB_101_MASK 0x0c000000 // {TEX[0], C, B} = 101 336 #define HW_C10_NCA_L2C_TCB_100_MASK 0x03000000 // {TEX[0], C, B} = 100 337 #define HW_C10_NCA_L2C_TCB_011_MASK 0x00c00000 // {TEX[0], C, B} = 011 338 #define HW_C10_NCA_L2C_TCB_010_MASK 0x00300000 // {TEX[0], C, B} = 010 339 #define HW_C10_NCA_L2C_TCB_001_MASK 0x000c0000 // {TEX[0], C, B} = 001 340 #define HW_C10_NCA_L2C_TCB_000_MASK 0x00030000 // {TEX[0], C, B} = 000 341 342 #define HW_C10_NCA_L1C_TCB_111_MASK 0x0000c000 // Remaps L1 Cache attribute for normal region {TEX[0], C, B} = 111 343 #define HW_C10_NCA_L1C_TCB_101_MASK 0x00000c00 // {TEX[0], C, B} = 101 344 #define HW_C10_NCA_L1C_TCB_000_MASK 0x00000300 // {TEX[0], C, B} = 000 345 #define HW_C10_NCA_L1C_TCB_001_MASK 0x000000c0 // {TEX[0], C, B} = 001 346 #define HW_C10_NCA_L1C_TCB_010_MASK 0x00000030 // {TEX[0], C, B} = 010 347 #define HW_C10_NCA_L1C_TCB_011_MASK 0x0000000c // {TEX[0], C, B} = 011 348 #define HW_C10_NCA_L1C_TCB_100_MASK 0x00000003 // {TEX[0], C, B} = 100 349 350 #define HW_C10_NCA_L2C_TCB_111_SFT 30 351 #define HW_C10_NCA_L2C_TCB_101_SFT 26 352 #define HW_C10_NCA_L2C_TCB_100_SFT 24 353 #define HW_C10_NCA_L2C_TCB_011_SFT 22 354 #define HW_C10_NCA_L2C_TCB_010_SFT 20 355 #define HW_C10_NCA_L2C_TCB_001_SFT 18 356 #define HW_C10_NCA_L2C_TCB_000_SFT 16 357 358 #define HW_C10_NCA_L1C_TCB_111_SFT 14 359 #define HW_C10_NCA_L1C_TCB_101_SFT 10 360 #define HW_C10_NCA_L1C_TCB_000_SFT 8 361 #define HW_C10_NCA_L1C_TCB_010_SFT 4 362 #define HW_C10_NCA_L1C_TCB_011_SFT 2 363 #define HW_C10_NCA_L1C_TCB_100_SFT 0 364 365 #define HW_C10_NCA_NC 0 // Noncachable 366 #define HW_C10_NCA_WB_WA 1 // Write-back Write-allocate 367 368 369 // Register 13.0.0 : FCSE Process ID (Not Recommended for MPCore) 370 371 #define HW_C13_FCSE_PID_MASK 0xfe000000 // FCSE Process ID 372 373 #define HW_C13_FCSE_PID_SFT 25 374 375 376 // Register 13.0.1 : Context ID 377 378 #define HW_C13_CONTEXT_PROCID_MASK 0xffffff00 // Process ID 379 #define HW_C13_CONTEXT_ASID_MASK 0x000000ff // Application Space ID 380 381 #define HW_C13_CONTEXT_PROCID_SFT 8 382 383 384 // Register 13.0.2/3/4 : Thread ID 385 386 387 // Register 15.12.0 : Performance Monitor Control 388 389 #define HW_C15_COUNT0_EVT_MASK 0x0ff00000 // Identifies the source of events for Count Register 0 390 #define HW_C15_COUNT1_EVT_MASK 0x000ff000 // for Count Register 1 391 #define HW_C15_CYCLE_COUNT_OVERFLOW 0x00000400 // Cycle Counter overflow 392 #define HW_C15_COUNT1_OVERFLOW 0x00000200 // Count Register 1 overflow 393 #define HW_C15_COUNT0_OVERFLOW 0x00000100 // Count Register 0 overflow 394 #define HW_C15_CYCLE_COUNT_IE 0x00000040 // Cycle Counter interrupt enable 395 #define HW_C15_COUNT1_IE 0x00000020 // Count Register 1 interrupt enable 396 #define HW_C15_COUNT0_IE 0x00000010 // Count Register 0 interrupt enable 397 #define HW_C15_CYCLE_COUNT_D64 0x00000008 // Cycle Counter counts every 64th processor clock cycle 398 #define HW_C15_CYCLE_COUNT_RESET 0x00000004 // Cycle Counter Reset on Write 399 #define HW_C15_COUNT01_RESET 0x00000002 // Counter Register 0/1 Reset on Write 400 #define HW_C15_PMN_ENABLE 0x00000001 // All three counters enable 401 402 #define HW_C15_COUNT0_EVT_SFT 20 403 #define HW_C15_COUNT1_EVT_SFT 12 404 405 #define HW_C15_EVT_IC_MISS 0x00 // Instruction cache miss 406 #define HW_C15_EVT_IFETCH_STALL 0x01 // Instruction fetch stall 407 #define HW_C15_EVT_DATA_STALL 0x02 // Data stall 408 #define HW_C15_EVT_ITLB_MISS 0x03 // Instruction MicroTLB miss 409 #define HW_C15_EVT_DTLB_MISS 0x04 // Data MicroTLB miss 410 #define HW_C15_EVT_MIGHT_BR_MISS 0x05 // Branch might have changed program flow 411 #define HW_C15_EVT_BR_NOT_PREDICT 0x06 // Branch not predicted 412 #define HW_C15_EVT_BR_PREDICT_MISS 0x07 // Branch predict miss 413 #define HW_C15_EVT_INST_EXEC 0x08 // Instruction executed 414 #define HW_C15_EVT_FOLD_INST_EXEC 0x09 // Folded instruction executed 415 #define HW_C15_EVT_DC_READ 0x0a // Data cache read 416 #define HW_C15_EVT_DC_MISS 0x0b // Data cache miss 417 #define HW_C15_EVT_DC_WRITE 0x0c // Data cache write 418 #define HW_C15_EVT_DC_WRITE_MISS 0x0d // Data cache write miss 419 #define HW_C15_EVT_DC_LINE_EVICT 0x0e // Data cache line eviction 420 #define HW_C15_EVT_SW_CHANGE_PC 0x0f // Software changed the PC and there is not a mode change 421 #define HW_C15_EVT_MTLB_MISS 0x10 // Main TLB miss 422 #define HW_C15_EVT_EXMEM_REQ 0x11 // External memory request (Cache Refill, Noncachable, Write-Back) 423 #define HW_C15_EVT_LSQ_FULL_STALL 0x12 // Stall because of Load Store Unit request queue being full 424 #define HW_C15_EVT_STB_DRAIN_TIMES 0x13 // Store buffer drain times 425 #define HW_C15_EVT_STB_MERGED 0x14 // Store buffer write is merged 426 #define HW_C15_EVT_LSU_SAFE_MODE 0x15 // Load Store Unit is in safe mode 427 #define HW_C15_EVT_INC_EACH_CYCLE 0xff // An increment each cycle 428 429 430 // Register 15.1.0 : Main TLB Debug Control 431 432 #define HW_C15_MTLB_LD_ENABLE 0x00000000 // Main TLB load enabled 433 #define HW_C15_MTLB_LD_DISABLE 0x00000030 // Main TLB load disabled 434 435 436 // Register 15.4 : Select TLB lockdown entry operations 437 438 #define HW_C15_TLBL_SEL_ENTRY_IDX 0x0000003f // Set-associative region index 439 #define HW_C15_TLBL_LKABLE_IDX 0x80000000 // Lockable region index 440 441 #define HW_C15_TLBL_ASSOC_WAY_MASK 0x00000020 // if ASSOCIATIVE, Way index 442 #define HW_C15_TLBL_ASSOC_SET_MASK 0x0000001f // if ASSOCIATIVE, Set index 443 #define HW_C15_TLBL_LKABLE_ET_MASK 0x00000003 // if LOCKABLE, Lockable entry 444 445 446 // Register 15.5 : TLB Lockdown VA operations 447 448 #define HW_C15_TLBL_VPN_MASK 0xfffff000 // TLB Virtual page number (per 4KB) 449 #define HW_C15_TLBL_MSID_MASK 0x000003ff // Memory space ID 450 451 #define HW_C15_TLBL_VPN_SFT 12 452 453 #define HW_C15_TLBL_MSID_GLOBAL 0x200 // Global entries 454 #define HW_C15_TLBL_MSID_ASID_MASK 0x0ff // Application Space ID entries 455 456 457 // Register 15.6 : TLB Lockdown PA operations 458 459 #define HW_C15_TLBL_PPN_MASK 0xfffff000 // TLB Physical page number (per 4KB) 460 #define HW_C15_TLBL_PSIZE_MASK 0x000000c0 // Page size 461 #define HW_C15_TLBL_APX_MASK 0x0000000e // Access Permissions Extension 462 #define HW_C15_TLBL_LOCKED_VALID 0x00000001 // Locked and valid 463 464 #define HW_C15_TLBL_PPN_SFT 12 465 #define HW_C15_TLBL_PSIZE_SFT 6 466 #define HW_C15_TLBL_APX_SFT 1 467 468 #define HW_C15_PSIZE_4KB 1 // 4KB page 469 #define HW_C15_PSIZE_64KB 2 // 64KB page 470 #define HW_C15_PSIZE_1MB 3 // 1MB page 471 #define HW_C15_PSIZE_16MB 0 // 16MB page 472 473 #define HW_C15_APX_NA 0 // Access denied 474 #define HW_C15_APX_S_RW_U_NA 1 // Supervisor access only 475 #define HW_C15_APX_S_RW_U_RO 2 // Supervisor full access, User read only 476 #define HW_C15_APX_ALL 3 // Full access 477 #define HW_C15_APX_S_RO_U_NA 5 // Supervisor read only 478 #define HW_C15_APX_S_RO_U_RO 6 // Supervisor/User read only 479 480 481 // Register 15.7 : TLB Lockdown Attributes 482 /* 483 #define HW_C15_TLBL_SP4_AP_MASK 0xc0000000 // Permissions for the 4th subpage (for MMUv5) 484 #define HW_C15_TLBL_SP3_AP_MASK 0x30000000 // Permissions for the 3rd subpage (for MMUv5) 485 #define HW_C15_TLBL_SP2_AP_MASK 0x0c000000 // Permissions for the 2nd subpage (for MMUv5) 486 #define HW_C15_TLBL_SP_VALID 0x02000000 // Subpages are supported (for MMUv5) 487 */ 488 #define HW_C15_TLBL_SP_INVALID 0x00000000 // Subpages are not supported (for MMUv6) 489 #define HW_C15_TLBL_DOMAIN_MASK 0x00000780 // Domain number of the TLB entry 490 #define HW_C15_TLBL_XN 0x00000040 // Execute Never 491 #define HW_C15_TLBL_RGT_MASK 0x0000003e // Region Type 492 #define HW_C15_TLBL_SHARED 0x00000001 // Shared 493 /* 494 #define HW_C15_TLBL_SP4_AP_SFT 30 495 #define HW_C15_TLBL_SP3_AP_SFT 28 496 #define HW_C15_TLBL_SP2_AP_SFT 26 497 */ 498 #define HW_C15_TLBL_DOMAIN_SFT 7 499 #define HW_C15_TLBL_RGT_SFT 1 500 #define HW_C15_TLBL_CBA_L1C_SFT 1 501 #define HW_C15_TLBL_CBA_L2C_SFT 3 502 503 #define HW_C15_SP_AP_NA 0 // Access denied (not use S, R) 504 #define HW_C15_SP_AP_S_RW_U_NA 1 // Supervisor access only 505 #define HW_C15_SP_AP_S_RW_U_RO 2 // Supervisor full access, User read only 506 #define HW_C15_SP_AP_ALL 3 // Full access 507 508 #define HW_C15_RGT_STRONG_ORDER 0x00 // Strongly Ordered, regardless of the S bit in the page table 509 #define HW_C15_RGT_SHARED_DEVICE 0x01 // Shared Device, regardless of the S bit in the page table 510 #define HW_C15_RGT_NSHARED_DEVICE 0x08 // Non-Shared Device, regardless of the S bit in the page table 511 #define HW_C15_RGT_L1C_NC_NB 0x10 // L1C Noncachable, Unbuffered 512 #define HW_C15_RGT_L1C_WB_WA 0x11 // L1C Write-back Write-allocate, Buffered 513 #define HW_C15_RGT_L1L2C_NC 0x04 // L1C and L2C Noncachable 514 #define HW_C15_RGT_L1L2C_WB_WA 0x07 // L1C and L2C Write-Back, Allocate on Write 515 516 #define HW_C15_TTBR0_MASK 0xFFFFFFFF 517 518 #ifdef __cplusplus 519 } // extern "C" 520 #endif 521 522 // NN_HW_ARM_ARMV6_REG_H_ 523 #endif 524