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Searched refs:REG_DISP_MMEM_FIFO_ADDR (Results 1 – 7 of 7) sorted by relevance

/TwlSDK-5.1.0/build/libraries/mi/common/src/
Dmi_dma_mainmem.c42 MIi_DmaSetParameters(dmaNo, (u32)src, (u32)REG_DISP_MMEM_FIFO_ADDR, MI_CNT_MMCOPY(0), 0); in MI_DispMemDmaCopy()
/TwlSDK-5.1.0/build/libraries/gx/ARM9/src/
Dgx.c88 REG_DISP_MMEM_FIFO_ADDR - REG_BG0CNT_ADDR); in GX_Init()
100 REG_DISP_MMEM_FIFO_ADDR - REG_BG0CNT_ADDR); in GX_Init()
111 MI_CpuFill32((void *)REG_BG0CNT_ADDR, 0, REG_DISP_MMEM_FIFO_ADDR - REG_BG0CNT_ADDR); in GX_Init()
/TwlSDK-5.1.0/include/nitro/hw/ARM9/
Dioreg_GX.h61 #define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) macro
62 …efine reg_GX_DISP_MMEM_FIFO (*( REGType32v *) REG_DISP_MMEM_FIFO_ADDR)
/TwlSDK-5.1.0/include/twl/hw/ARM9/
Dioreg_GX.h61 #define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) macro
62 …efine reg_GX_DISP_MMEM_FIFO (*( REGType32v *) REG_DISP_MMEM_FIFO_ADDR)
/TwlSDK-5.1.0/build/libraries/mi/common/include/
Ddma_red.h273 __MI_DmaSet(dmaNo, srcp, REG_DISP_MMEM_FIFO_ADDR, ( \
/TwlSDK-5.1.0/build/libraries/os/common/include/
Ddma_red.h273 __MI_DmaSet(dmaNo, srcp, REG_DISP_MMEM_FIFO_ADDR, ( \
/TwlSDK-5.1.0/build/libraries/init/common/include/
Ddma_red.h273 __MI_DmaSet(dmaNo, srcp, REG_DISP_MMEM_FIFO_ADDR, ( \