Searched refs:reg_SCFG_CLK (Results 1 – 4 of 4) sorted by relevance
231 SCFGi_CHANGEBIT_16( ®_SCFG_CLK, SCFG_CAMERA_CKI_FLAG, sw, 0 ); in SCFG_SetCameraCKIClock()246 return (BOOL)((reg_SCFG_CLK & SCFG_CAMERA_CKI_FLAG)? TRUE: FALSE); in SCFG_IsCameraCKIClockEnable()261 return (BOOL)((reg_SCFG_CLK & SCFG_CLOCK_SUPPLY_WRAM)? TRUE: FALSE); in SCFG_IsClockSuppliedToWram()276 SCFGi_CHANGEBIT_16( ®_SCFG_CLK, SCFG_CLOCK_SUPPLY_CAMERA, sw, 0 ); in SCFG_SupplyClockToCamera()291 return (BOOL)((reg_SCFG_CLK & SCFG_CLOCK_SUPPLY_CAMERA)? TRUE: FALSE); in SCFG_IsClockSuppliedToCamera()306 SCFGi_CHANGEBIT_16( ®_SCFG_CLK, SCFG_CLOCK_SUPPLY_DSP, sw, 0 ); in SCFG_SupplyClockToDSP()321 return (BOOL)((reg_SCFG_CLK & SCFG_CLOCK_SUPPLY_DSP)? TRUE: FALSE); in SCFG_IsClockSuppliedToDSP()347 return (SCFGCpuSpeed)(reg_SCFG_CLK & SCFG_CPU_SPEED_MASK); in SCFG_GetCpuSpeed()
58 reg_SCFG_CLK |= REG_SCFG_CLK_CAMHCLK_MASK; // ensure powered on in CAMERA_ResetCore()62 reg_SCFG_CLK |= REG_SCFG_CLK_CAMCKI_MASK; // clock out to read internal ROM code in CAMERA_ResetCore()67 reg_SCFG_CLK &= ~REG_SCFG_CLK_CAMCKI_MASK; // stop to clock in CAMERA_ResetCore()
2401 u16 reg = reg_SCFG_CLK; in CAMERAi_StopMasterClock()2402 reg_SCFG_CLK = (u16)(reg & ~REG_SCFG_CLK_CAMCKI_MASK); in CAMERAi_StopMasterClock()2409 u16 reg = reg_SCFG_CLK; in CAMERAi_StartMasterClock()2410 reg_SCFG_CLK = (u16)(reg | REG_SCFG_CLK_CAMCKI_MASK); in CAMERAi_StartMasterClock()
44 #define reg_SCFG_CLK (*( REGType16v *) REG_CLK_ADDR) macro