Lines Matching refs:s0
39 VLDMIA r1!,{s0-s4} // Segment and load to shorten stall times due to data hazards in MTX33CopyAsm()
42 VSTMIA r2!,{s0-s4} // Store result in MTX33CopyAsm()
53 VMLA.F32 s1,s10,s0 in MTX33MAddAsm()
54 VMLA.F32 s2,s11,s0 in MTX33MAddAsm()
55 VMLA.F32 s3,s12,s0 in MTX33MAddAsm()
59 VMLA.F32 s4,s13,s0 in MTX33MAddAsm()
60 VMLA.F32 s5,s14,s0 in MTX33MAddAsm()
61 VMLA.F32 s6,s15,s0 in MTX33MAddAsm()
63 VMLA.F32 s7,s10,s0 in MTX33MAddAsm()
64 VMLA.F32 s8,s11,s0 in MTX33MAddAsm()
65 VMLA.F32 s9,s12,s0 in MTX33MAddAsm()
75 VLDMIA r1,{s0-s8} // First line of matrix pM to register [S0-S2] in VEC3TransformAsm()
78 VMUL.F32 s12,s0,s9 in VEC3TransformAsm()