1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_MI.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_MI_H_ 18 #define TWL_HW_ARM9_IOREG_MI_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DMA0SAD */ 35 36 #define REG_DMA0SAD_OFFSET 0x0b0 37 #define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) 38 #define reg_MI_DMA0SAD (*( REGType32v *) REG_DMA0SAD_ADDR) 39 40 /* DMA0DAD */ 41 42 #define REG_DMA0DAD_OFFSET 0x0b4 43 #define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) 44 #define reg_MI_DMA0DAD (*( REGType32v *) REG_DMA0DAD_ADDR) 45 46 /* DMA0CNT */ 47 48 #define REG_DMA0CNT_OFFSET 0x0b8 49 #define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) 50 #define reg_MI_DMA0CNT (*( REGType32v *) REG_DMA0CNT_ADDR) 51 52 /* DMA1SAD */ 53 54 #define REG_DMA1SAD_OFFSET 0x0bc 55 #define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET) 56 #define reg_MI_DMA1SAD (*( REGType32v *) REG_DMA1SAD_ADDR) 57 58 /* DMA1DAD */ 59 60 #define REG_DMA1DAD_OFFSET 0x0c0 61 #define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) 62 #define reg_MI_DMA1DAD (*( REGType32v *) REG_DMA1DAD_ADDR) 63 64 /* DMA1CNT */ 65 66 #define REG_DMA1CNT_OFFSET 0x0c4 67 #define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) 68 #define reg_MI_DMA1CNT (*( REGType32v *) REG_DMA1CNT_ADDR) 69 70 /* DMA2SAD */ 71 72 #define REG_DMA2SAD_OFFSET 0x0c8 73 #define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET) 74 #define reg_MI_DMA2SAD (*( REGType32v *) REG_DMA2SAD_ADDR) 75 76 /* DMA2DAD */ 77 78 #define REG_DMA2DAD_OFFSET 0x0cc 79 #define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) 80 #define reg_MI_DMA2DAD (*( REGType32v *) REG_DMA2DAD_ADDR) 81 82 /* DMA2CNT */ 83 84 #define REG_DMA2CNT_OFFSET 0x0d0 85 #define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) 86 #define reg_MI_DMA2CNT (*( REGType32v *) REG_DMA2CNT_ADDR) 87 88 /* DMA3SAD */ 89 90 #define REG_DMA3SAD_OFFSET 0x0d4 91 #define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET) 92 #define reg_MI_DMA3SAD (*( REGType32v *) REG_DMA3SAD_ADDR) 93 94 /* DMA3DAD */ 95 96 #define REG_DMA3DAD_OFFSET 0x0d8 97 #define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET) 98 #define reg_MI_DMA3DAD (*( REGType32v *) REG_DMA3DAD_ADDR) 99 100 /* DMA3CNT */ 101 102 #define REG_DMA3CNT_OFFSET 0x0dc 103 #define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) 104 #define reg_MI_DMA3CNT (*( REGType32v *) REG_DMA3CNT_ADDR) 105 106 /* DMA0_CLR_DATA */ 107 108 #define REG_DMA0_CLR_DATA_OFFSET 0x0e0 109 #define REG_DMA0_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA0_CLR_DATA_OFFSET) 110 #define reg_MI_DMA0_CLR_DATA (*( REGType32v *) REG_DMA0_CLR_DATA_ADDR) 111 112 /* DMA1_CLR_DATA */ 113 114 #define REG_DMA1_CLR_DATA_OFFSET 0x0e4 115 #define REG_DMA1_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA1_CLR_DATA_OFFSET) 116 #define reg_MI_DMA1_CLR_DATA (*( REGType32v *) REG_DMA1_CLR_DATA_ADDR) 117 118 /* DMA2_CLR_DATA */ 119 120 #define REG_DMA2_CLR_DATA_OFFSET 0x0e8 121 #define REG_DMA2_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA2_CLR_DATA_OFFSET) 122 #define reg_MI_DMA2_CLR_DATA (*( REGType32v *) REG_DMA2_CLR_DATA_ADDR) 123 124 /* DMA3_CLR_DATA */ 125 126 #define REG_DMA3_CLR_DATA_OFFSET 0x0ec 127 #define REG_DMA3_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA3_CLR_DATA_OFFSET) 128 #define reg_MI_DMA3_CLR_DATA (*( REGType32v *) REG_DMA3_CLR_DATA_ADDR) 129 130 /* NDMAGCNT */ 131 132 #define REG_NDMAGCNT_OFFSET 0x4100 133 #define REG_NDMAGCNT_ADDR (HW_REG_BASE + REG_NDMAGCNT_OFFSET) 134 #define reg_MI_NDMAGCNT (*( REGType32v *) REG_NDMAGCNT_ADDR) 135 136 /* NDMA0SAD */ 137 138 #define REG_NDMA0SAD_OFFSET 0x4104 139 #define REG_NDMA0SAD_ADDR (HW_REG_BASE + REG_NDMA0SAD_OFFSET) 140 #define reg_MI_NDMA0SAD (*( REGType32v *) REG_NDMA0SAD_ADDR) 141 142 /* NDAM0DAD */ 143 144 #define REG_NDAM0DAD_OFFSET 0x4108 145 #define REG_NDAM0DAD_ADDR (HW_REG_BASE + REG_NDAM0DAD_OFFSET) 146 #define reg_MI_NDAM0DAD (*( REGType32v *) REG_NDAM0DAD_ADDR) 147 148 /* NDMA0TCNT */ 149 150 #define REG_NDMA0TCNT_OFFSET 0x410c 151 #define REG_NDMA0TCNT_ADDR (HW_REG_BASE + REG_NDMA0TCNT_OFFSET) 152 #define reg_MI_NDMA0TCNT (*( REGType32v *) REG_NDMA0TCNT_ADDR) 153 154 /* NDMA0WCNT */ 155 156 #define REG_NDMA0WCNT_OFFSET 0x4110 157 #define REG_NDMA0WCNT_ADDR (HW_REG_BASE + REG_NDMA0WCNT_OFFSET) 158 #define reg_MI_NDMA0WCNT (*( REGType32v *) REG_NDMA0WCNT_ADDR) 159 160 /* NDMA0BCNT */ 161 162 #define REG_NDMA0BCNT_OFFSET 0x4114 163 #define REG_NDMA0BCNT_ADDR (HW_REG_BASE + REG_NDMA0BCNT_OFFSET) 164 #define reg_MI_NDMA0BCNT (*( REGType32v *) REG_NDMA0BCNT_ADDR) 165 166 /* NDMA0FDATA */ 167 168 #define REG_NDMA0FDATA_OFFSET 0x4118 169 #define REG_NDMA0FDATA_ADDR (HW_REG_BASE + REG_NDMA0FDATA_OFFSET) 170 #define reg_MI_NDMA0FDATA (*( REGType32v *) REG_NDMA0FDATA_ADDR) 171 172 /* NDMA0CNT */ 173 174 #define REG_NDMA0CNT_OFFSET 0x411c 175 #define REG_NDMA0CNT_ADDR (HW_REG_BASE + REG_NDMA0CNT_OFFSET) 176 #define reg_MI_NDMA0CNT (*( REGType32v *) REG_NDMA0CNT_ADDR) 177 178 /* NDMA1SAD */ 179 180 #define REG_NDMA1SAD_OFFSET 0x4120 181 #define REG_NDMA1SAD_ADDR (HW_REG_BASE + REG_NDMA1SAD_OFFSET) 182 #define reg_MI_NDMA1SAD (*( REGType32v *) REG_NDMA1SAD_ADDR) 183 184 /* NDAM1DAD */ 185 186 #define REG_NDAM1DAD_OFFSET 0x4124 187 #define REG_NDAM1DAD_ADDR (HW_REG_BASE + REG_NDAM1DAD_OFFSET) 188 #define reg_MI_NDAM1DAD (*( REGType32v *) REG_NDAM1DAD_ADDR) 189 190 /* NDMA1TCNT */ 191 192 #define REG_NDMA1TCNT_OFFSET 0x4128 193 #define REG_NDMA1TCNT_ADDR (HW_REG_BASE + REG_NDMA1TCNT_OFFSET) 194 #define reg_MI_NDMA1TCNT (*( REGType32v *) REG_NDMA1TCNT_ADDR) 195 196 /* NDMA1WCNT */ 197 198 #define REG_NDMA1WCNT_OFFSET 0x412c 199 #define REG_NDMA1WCNT_ADDR (HW_REG_BASE + REG_NDMA1WCNT_OFFSET) 200 #define reg_MI_NDMA1WCNT (*( REGType32v *) REG_NDMA1WCNT_ADDR) 201 202 /* NDMA1BCNT */ 203 204 #define REG_NDMA1BCNT_OFFSET 0x4130 205 #define REG_NDMA1BCNT_ADDR (HW_REG_BASE + REG_NDMA1BCNT_OFFSET) 206 #define reg_MI_NDMA1BCNT (*( REGType32v *) REG_NDMA1BCNT_ADDR) 207 208 /* NDMA1FDATA */ 209 210 #define REG_NDMA1FDATA_OFFSET 0x4134 211 #define REG_NDMA1FDATA_ADDR (HW_REG_BASE + REG_NDMA1FDATA_OFFSET) 212 #define reg_MI_NDMA1FDATA (*( REGType32v *) REG_NDMA1FDATA_ADDR) 213 214 /* NDMA1CNT */ 215 216 #define REG_NDMA1CNT_OFFSET 0x4138 217 #define REG_NDMA1CNT_ADDR (HW_REG_BASE + REG_NDMA1CNT_OFFSET) 218 #define reg_MI_NDMA1CNT (*( REGType32v *) REG_NDMA1CNT_ADDR) 219 220 /* NDMA2SAD */ 221 222 #define REG_NDMA2SAD_OFFSET 0x413c 223 #define REG_NDMA2SAD_ADDR (HW_REG_BASE + REG_NDMA2SAD_OFFSET) 224 #define reg_MI_NDMA2SAD (*( REGType32v *) REG_NDMA2SAD_ADDR) 225 226 /* NDAM2DAD */ 227 228 #define REG_NDAM2DAD_OFFSET 0x4140 229 #define REG_NDAM2DAD_ADDR (HW_REG_BASE + REG_NDAM2DAD_OFFSET) 230 #define reg_MI_NDAM2DAD (*( REGType32v *) REG_NDAM2DAD_ADDR) 231 232 /* NDMA2TCNT */ 233 234 #define REG_NDMA2TCNT_OFFSET 0x4144 235 #define REG_NDMA2TCNT_ADDR (HW_REG_BASE + REG_NDMA2TCNT_OFFSET) 236 #define reg_MI_NDMA2TCNT (*( REGType32v *) REG_NDMA2TCNT_ADDR) 237 238 /* NDMA2WCNT */ 239 240 #define REG_NDMA2WCNT_OFFSET 0x4148 241 #define REG_NDMA2WCNT_ADDR (HW_REG_BASE + REG_NDMA2WCNT_OFFSET) 242 #define reg_MI_NDMA2WCNT (*( REGType32v *) REG_NDMA2WCNT_ADDR) 243 244 /* NDMA2BCNT */ 245 246 #define REG_NDMA2BCNT_OFFSET 0x414c 247 #define REG_NDMA2BCNT_ADDR (HW_REG_BASE + REG_NDMA2BCNT_OFFSET) 248 #define reg_MI_NDMA2BCNT (*( REGType32v *) REG_NDMA2BCNT_ADDR) 249 250 /* NDMA2FDATA */ 251 252 #define REG_NDMA2FDATA_OFFSET 0x4150 253 #define REG_NDMA2FDATA_ADDR (HW_REG_BASE + REG_NDMA2FDATA_OFFSET) 254 #define reg_MI_NDMA2FDATA (*( REGType32v *) REG_NDMA2FDATA_ADDR) 255 256 /* NDMA2CNT */ 257 258 #define REG_NDMA2CNT_OFFSET 0x4154 259 #define REG_NDMA2CNT_ADDR (HW_REG_BASE + REG_NDMA2CNT_OFFSET) 260 #define reg_MI_NDMA2CNT (*( REGType32v *) REG_NDMA2CNT_ADDR) 261 262 /* NDMA3SAD */ 263 264 #define REG_NDMA3SAD_OFFSET 0x4158 265 #define REG_NDMA3SAD_ADDR (HW_REG_BASE + REG_NDMA3SAD_OFFSET) 266 #define reg_MI_NDMA3SAD (*( REGType32v *) REG_NDMA3SAD_ADDR) 267 268 /* NDAM3DAD */ 269 270 #define REG_NDAM3DAD_OFFSET 0x415c 271 #define REG_NDAM3DAD_ADDR (HW_REG_BASE + REG_NDAM3DAD_OFFSET) 272 #define reg_MI_NDAM3DAD (*( REGType32v *) REG_NDAM3DAD_ADDR) 273 274 /* NDMA3TCNT */ 275 276 #define REG_NDMA3TCNT_OFFSET 0x4160 277 #define REG_NDMA3TCNT_ADDR (HW_REG_BASE + REG_NDMA3TCNT_OFFSET) 278 #define reg_MI_NDMA3TCNT (*( REGType32v *) REG_NDMA3TCNT_ADDR) 279 280 /* NDMA3WCNT */ 281 282 #define REG_NDMA3WCNT_OFFSET 0x4164 283 #define REG_NDMA3WCNT_ADDR (HW_REG_BASE + REG_NDMA3WCNT_OFFSET) 284 #define reg_MI_NDMA3WCNT (*( REGType32v *) REG_NDMA3WCNT_ADDR) 285 286 /* NDMA3BCNT */ 287 288 #define REG_NDMA3BCNT_OFFSET 0x4168 289 #define REG_NDMA3BCNT_ADDR (HW_REG_BASE + REG_NDMA3BCNT_OFFSET) 290 #define reg_MI_NDMA3BCNT (*( REGType32v *) REG_NDMA3BCNT_ADDR) 291 292 /* NDMA3FDATA */ 293 294 #define REG_NDMA3FDATA_OFFSET 0x416c 295 #define REG_NDMA3FDATA_ADDR (HW_REG_BASE + REG_NDMA3FDATA_OFFSET) 296 #define reg_MI_NDMA3FDATA (*( REGType32v *) REG_NDMA3FDATA_ADDR) 297 298 /* NDMA3CNT */ 299 300 #define REG_NDMA3CNT_OFFSET 0x4170 301 #define REG_NDMA3CNT_ADDR (HW_REG_BASE + REG_NDMA3CNT_OFFSET) 302 #define reg_MI_NDMA3CNT (*( REGType32v *) REG_NDMA3CNT_ADDR) 303 304 /* MCCNT0 */ 305 306 #define REG_MCCNT0_OFFSET 0x1a0 307 #define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET) 308 #define reg_MI_MCCNT0 (*( REGType16v *) REG_MCCNT0_ADDR) 309 310 /* MCD0 */ 311 312 #define REG_MCD0_OFFSET 0x1a2 313 #define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET) 314 #define reg_MI_MCD0 (*( REGType16v *) REG_MCD0_ADDR) 315 316 /* MCD1 */ 317 318 #define REG_MCD1_OFFSET 0x100010 319 #define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET) 320 #define reg_MI_MCD1 (*( REGType32v *) REG_MCD1_ADDR) 321 322 /* MCCNT1 */ 323 324 #define REG_MCCNT1_OFFSET 0x1a4 325 #define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET) 326 #define reg_MI_MCCNT1 (*( REGType32v *) REG_MCCNT1_ADDR) 327 328 /* MCCMD0 */ 329 330 #define REG_MCCMD0_OFFSET 0x1a8 331 #define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET) 332 #define reg_MI_MCCMD0 (*( REGType32v *) REG_MCCMD0_ADDR) 333 334 /* MCCMD1 */ 335 336 #define REG_MCCMD1_OFFSET 0x1ac 337 #define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET) 338 #define reg_MI_MCCMD1 (*( REGType32v *) REG_MCCMD1_ADDR) 339 340 /* MCCNT0_A */ 341 342 #define REG_MCCNT0_A_OFFSET 0x1a0 343 #define REG_MCCNT0_A_ADDR (HW_REG_BASE + REG_MCCNT0_A_OFFSET) 344 #define reg_MI_MCCNT0_A (*( REGType16v *) REG_MCCNT0_A_ADDR) 345 346 /* MCD0_A */ 347 348 #define REG_MCD0_A_OFFSET 0x1a2 349 #define REG_MCD0_A_ADDR (HW_REG_BASE + REG_MCD0_A_OFFSET) 350 #define reg_MI_MCD0_A (*( REGType16v *) REG_MCD0_A_ADDR) 351 352 /* MCD1_A */ 353 354 #define REG_MCD1_A_OFFSET 0x100010 355 #define REG_MCD1_A_ADDR (HW_REG_BASE + REG_MCD1_A_OFFSET) 356 #define reg_MI_MCD1_A (*( REGType32v *) REG_MCD1_A_ADDR) 357 358 /* MCCNT1_A */ 359 360 #define REG_MCCNT1_A_OFFSET 0x1a4 361 #define REG_MCCNT1_A_ADDR (HW_REG_BASE + REG_MCCNT1_A_OFFSET) 362 #define reg_MI_MCCNT1_A (*( REGType32v *) REG_MCCNT1_A_ADDR) 363 364 /* MCCMD0_A */ 365 366 #define REG_MCCMD0_A_OFFSET 0x1a8 367 #define REG_MCCMD0_A_ADDR (HW_REG_BASE + REG_MCCMD0_A_OFFSET) 368 #define reg_MI_MCCMD0_A (*( REGType32v *) REG_MCCMD0_A_ADDR) 369 370 /* MCCMD1_A */ 371 372 #define REG_MCCMD1_A_OFFSET 0x1ac 373 #define REG_MCCMD1_A_ADDR (HW_REG_BASE + REG_MCCMD1_A_OFFSET) 374 #define reg_MI_MCCMD1_A (*( REGType32v *) REG_MCCMD1_A_ADDR) 375 376 /* MCSRC0_A */ 377 378 #define REG_MCSRC0_A_OFFSET 0x1b0 379 #define REG_MCSRC0_A_ADDR (HW_REG_BASE + REG_MCSRC0_A_OFFSET) 380 #define reg_MI_MCSRC0_A (*( REGType32v *) REG_MCSRC0_A_ADDR) 381 382 /* MCSRC1_A */ 383 384 #define REG_MCSRC1_A_OFFSET 0x1b4 385 #define REG_MCSRC1_A_ADDR (HW_REG_BASE + REG_MCSRC1_A_OFFSET) 386 #define reg_MI_MCSRC1_A (*( REGType32v *) REG_MCSRC1_A_ADDR) 387 388 /* MCSRC2_A */ 389 390 #define REG_MCSRC2_A_OFFSET 0x1b8 391 #define REG_MCSRC2_A_ADDR (HW_REG_BASE + REG_MCSRC2_A_OFFSET) 392 #define reg_MI_MCSRC2_A (*( REGType32v *) REG_MCSRC2_A_ADDR) 393 394 /* MCCNT0_B */ 395 396 #define REG_MCCNT0_B_OFFSET 0x21a0 397 #define REG_MCCNT0_B_ADDR (HW_REG_BASE + REG_MCCNT0_B_OFFSET) 398 #define reg_MI_MCCNT0_B (*( REGType16v *) REG_MCCNT0_B_ADDR) 399 400 /* MCD0_B */ 401 402 #define REG_MCD0_B_OFFSET 0x21a2 403 #define REG_MCD0_B_ADDR (HW_REG_BASE + REG_MCD0_B_OFFSET) 404 #define reg_MI_MCD0_B (*( REGType16v *) REG_MCD0_B_ADDR) 405 406 /* MCD1_B */ 407 408 #define REG_MCD1_B_OFFSET 0x102010 409 #define REG_MCD1_B_ADDR (HW_REG_BASE + REG_MCD1_B_OFFSET) 410 #define reg_MI_MCD1_B (*( REGType32v *) REG_MCD1_B_ADDR) 411 412 /* MCCNT1_B */ 413 414 #define REG_MCCNT1_B_OFFSET 0x21a4 415 #define REG_MCCNT1_B_ADDR (HW_REG_BASE + REG_MCCNT1_B_OFFSET) 416 #define reg_MI_MCCNT1_B (*( REGType32v *) REG_MCCNT1_B_ADDR) 417 418 /* MCCMD0_B */ 419 420 #define REG_MCCMD0_B_OFFSET 0x21a8 421 #define REG_MCCMD0_B_ADDR (HW_REG_BASE + REG_MCCMD0_B_OFFSET) 422 #define reg_MI_MCCMD0_B (*( REGType32v *) REG_MCCMD0_B_ADDR) 423 424 /* MCCMD1_B */ 425 426 #define REG_MCCMD1_B_OFFSET 0x21ac 427 #define REG_MCCMD1_B_ADDR (HW_REG_BASE + REG_MCCMD1_B_OFFSET) 428 #define reg_MI_MCCMD1_B (*( REGType32v *) REG_MCCMD1_B_ADDR) 429 430 /* MCSRC0_B */ 431 432 #define REG_MCSRC0_B_OFFSET 0x21b0 433 #define REG_MCSRC0_B_ADDR (HW_REG_BASE + REG_MCSRC0_B_OFFSET) 434 #define reg_MI_MCSRC0_B (*( REGType32v *) REG_MCSRC0_B_ADDR) 435 436 /* MCSRC1_B */ 437 438 #define REG_MCSRC1_B_OFFSET 0x21b4 439 #define REG_MCSRC1_B_ADDR (HW_REG_BASE + REG_MCSRC1_B_OFFSET) 440 #define reg_MI_MCSRC1_B (*( REGType32v *) REG_MCSRC1_B_ADDR) 441 442 /* MCSRC2_B */ 443 444 #define REG_MCSRC2_B_OFFSET 0x21b8 445 #define REG_MCSRC2_B_ADDR (HW_REG_BASE + REG_MCSRC2_B_OFFSET) 446 #define reg_MI_MCSRC2_B (*( REGType32v *) REG_MCSRC2_B_ADDR) 447 448 /* EXMEMCNT */ 449 450 #define REG_EXMEMCNT_OFFSET 0x204 451 #define REG_EXMEMCNT_ADDR (HW_REG_BASE + REG_EXMEMCNT_OFFSET) 452 #define reg_MI_EXMEMCNT (*( REGType16v *) REG_EXMEMCNT_ADDR) 453 454 /* MC */ 455 456 #define REG_MC_OFFSET 0x4010 457 #define REG_MC_ADDR (HW_REG_BASE + REG_MC_OFFSET) 458 #define reg_MI_MC (*(const REGType16v *) REG_MC_ADDR) 459 460 /* MBK1 */ 461 462 #define REG_MBK1_OFFSET 0x4040 463 #define REG_MBK1_ADDR (HW_REG_BASE + REG_MBK1_OFFSET) 464 #define reg_MI_MBK1 (*( REGType32v *) REG_MBK1_ADDR) 465 466 /* MBK_A0 */ 467 468 #define REG_MBK_A0_OFFSET 0x4040 469 #define REG_MBK_A0_ADDR (HW_REG_BASE + REG_MBK_A0_OFFSET) 470 #define reg_MI_MBK_A0 (*( REGType8v *) REG_MBK_A0_ADDR) 471 472 /* MBK_A1 */ 473 474 #define REG_MBK_A1_OFFSET 0x4041 475 #define REG_MBK_A1_ADDR (HW_REG_BASE + REG_MBK_A1_OFFSET) 476 #define reg_MI_MBK_A1 (*( REGType8v *) REG_MBK_A1_ADDR) 477 478 /* MBK_A2 */ 479 480 #define REG_MBK_A2_OFFSET 0x4042 481 #define REG_MBK_A2_ADDR (HW_REG_BASE + REG_MBK_A2_OFFSET) 482 #define reg_MI_MBK_A2 (*( REGType8v *) REG_MBK_A2_ADDR) 483 484 /* MBK_A3 */ 485 486 #define REG_MBK_A3_OFFSET 0x4043 487 #define REG_MBK_A3_ADDR (HW_REG_BASE + REG_MBK_A3_OFFSET) 488 #define reg_MI_MBK_A3 (*( REGType8v *) REG_MBK_A3_ADDR) 489 490 /* MBK2 */ 491 492 #define REG_MBK2_OFFSET 0x4044 493 #define REG_MBK2_ADDR (HW_REG_BASE + REG_MBK2_OFFSET) 494 #define reg_MI_MBK2 (*( REGType32v *) REG_MBK2_ADDR) 495 496 /* MBK_B0 */ 497 498 #define REG_MBK_B0_OFFSET 0x4044 499 #define REG_MBK_B0_ADDR (HW_REG_BASE + REG_MBK_B0_OFFSET) 500 #define reg_MI_MBK_B0 (*( REGType8v *) REG_MBK_B0_ADDR) 501 502 /* MBK_B1 */ 503 504 #define REG_MBK_B1_OFFSET 0x4045 505 #define REG_MBK_B1_ADDR (HW_REG_BASE + REG_MBK_B1_OFFSET) 506 #define reg_MI_MBK_B1 (*( REGType8v *) REG_MBK_B1_ADDR) 507 508 /* MBK_B2 */ 509 510 #define REG_MBK_B2_OFFSET 0x4046 511 #define REG_MBK_B2_ADDR (HW_REG_BASE + REG_MBK_B2_OFFSET) 512 #define reg_MI_MBK_B2 (*( REGType8v *) REG_MBK_B2_ADDR) 513 514 /* MBK_B3 */ 515 516 #define REG_MBK_B3_OFFSET 0x4047 517 #define REG_MBK_B3_ADDR (HW_REG_BASE + REG_MBK_B3_OFFSET) 518 #define reg_MI_MBK_B3 (*( REGType8v *) REG_MBK_B3_ADDR) 519 520 /* MBK3 */ 521 522 #define REG_MBK3_OFFSET 0x4048 523 #define REG_MBK3_ADDR (HW_REG_BASE + REG_MBK3_OFFSET) 524 #define reg_MI_MBK3 (*( REGType32v *) REG_MBK3_ADDR) 525 526 /* MBK_B4 */ 527 528 #define REG_MBK_B4_OFFSET 0x4048 529 #define REG_MBK_B4_ADDR (HW_REG_BASE + REG_MBK_B4_OFFSET) 530 #define reg_MI_MBK_B4 (*( REGType8v *) REG_MBK_B4_ADDR) 531 532 /* MBK_B5 */ 533 534 #define REG_MBK_B5_OFFSET 0x4049 535 #define REG_MBK_B5_ADDR (HW_REG_BASE + REG_MBK_B5_OFFSET) 536 #define reg_MI_MBK_B5 (*( REGType8v *) REG_MBK_B5_ADDR) 537 538 /* MBK_B6 */ 539 540 #define REG_MBK_B6_OFFSET 0x404a 541 #define REG_MBK_B6_ADDR (HW_REG_BASE + REG_MBK_B6_OFFSET) 542 #define reg_MI_MBK_B6 (*( REGType8v *) REG_MBK_B6_ADDR) 543 544 /* MBK_B7 */ 545 546 #define REG_MBK_B7_OFFSET 0x404b 547 #define REG_MBK_B7_ADDR (HW_REG_BASE + REG_MBK_B7_OFFSET) 548 #define reg_MI_MBK_B7 (*( REGType8v *) REG_MBK_B7_ADDR) 549 550 /* MBK4 */ 551 552 #define REG_MBK4_OFFSET 0x404c 553 #define REG_MBK4_ADDR (HW_REG_BASE + REG_MBK4_OFFSET) 554 #define reg_MI_MBK4 (*( REGType32v *) REG_MBK4_ADDR) 555 556 /* MBK_C0 */ 557 558 #define REG_MBK_C0_OFFSET 0x404c 559 #define REG_MBK_C0_ADDR (HW_REG_BASE + REG_MBK_C0_OFFSET) 560 #define reg_MI_MBK_C0 (*( REGType8v *) REG_MBK_C0_ADDR) 561 562 /* MBK_C1 */ 563 564 #define REG_MBK_C1_OFFSET 0x404d 565 #define REG_MBK_C1_ADDR (HW_REG_BASE + REG_MBK_C1_OFFSET) 566 #define reg_MI_MBK_C1 (*( REGType8v *) REG_MBK_C1_ADDR) 567 568 /* MBK_C2 */ 569 570 #define REG_MBK_C2_OFFSET 0x404e 571 #define REG_MBK_C2_ADDR (HW_REG_BASE + REG_MBK_C2_OFFSET) 572 #define reg_MI_MBK_C2 (*( REGType8v *) REG_MBK_C2_ADDR) 573 574 /* MBK_C3 */ 575 576 #define REG_MBK_C3_OFFSET 0x404f 577 #define REG_MBK_C3_ADDR (HW_REG_BASE + REG_MBK_C3_OFFSET) 578 #define reg_MI_MBK_C3 (*( REGType8v *) REG_MBK_C3_ADDR) 579 580 /* MBK5 */ 581 582 #define REG_MBK5_OFFSET 0x4050 583 #define REG_MBK5_ADDR (HW_REG_BASE + REG_MBK5_OFFSET) 584 #define reg_MI_MBK5 (*( REGType32v *) REG_MBK5_ADDR) 585 586 /* MBK_C4 */ 587 588 #define REG_MBK_C4_OFFSET 0x4050 589 #define REG_MBK_C4_ADDR (HW_REG_BASE + REG_MBK_C4_OFFSET) 590 #define reg_MI_MBK_C4 (*( REGType8v *) REG_MBK_C4_ADDR) 591 592 /* MBK_C5 */ 593 594 #define REG_MBK_C5_OFFSET 0x4051 595 #define REG_MBK_C5_ADDR (HW_REG_BASE + REG_MBK_C5_OFFSET) 596 #define reg_MI_MBK_C5 (*( REGType8v *) REG_MBK_C5_ADDR) 597 598 /* MBK_C6 */ 599 600 #define REG_MBK_C6_OFFSET 0x4052 601 #define REG_MBK_C6_ADDR (HW_REG_BASE + REG_MBK_C6_OFFSET) 602 #define reg_MI_MBK_C6 (*( REGType8v *) REG_MBK_C6_ADDR) 603 604 /* MBK_C7 */ 605 606 #define REG_MBK_C7_OFFSET 0x4053 607 #define REG_MBK_C7_ADDR (HW_REG_BASE + REG_MBK_C7_OFFSET) 608 #define reg_MI_MBK_C7 (*( REGType8v *) REG_MBK_C7_ADDR) 609 610 /* MBK6 */ 611 612 #define REG_MBK6_OFFSET 0x4054 613 #define REG_MBK6_ADDR (HW_REG_BASE + REG_MBK6_OFFSET) 614 #define reg_MI_MBK6 (*( REGType32v *) REG_MBK6_ADDR) 615 616 /* MBK7 */ 617 618 #define REG_MBK7_OFFSET 0x4058 619 #define REG_MBK7_ADDR (HW_REG_BASE + REG_MBK7_OFFSET) 620 #define reg_MI_MBK7 (*( REGType32v *) REG_MBK7_ADDR) 621 622 /* MBK8 */ 623 624 #define REG_MBK8_OFFSET 0x405c 625 #define REG_MBK8_ADDR (HW_REG_BASE + REG_MBK8_OFFSET) 626 #define reg_MI_MBK8 (*( REGType32v *) REG_MBK8_ADDR) 627 628 /* MBK9 */ 629 630 #define REG_MBK9_OFFSET 0x4060 631 #define REG_MBK9_ADDR (HW_REG_BASE + REG_MBK9_OFFSET) 632 #define reg_MI_MBK9 (*( REGType32v *) REG_MBK9_ADDR) 633 634 /* MBK_A_LOCK */ 635 636 #define REG_MBK_A_LOCK_OFFSET 0x4060 637 #define REG_MBK_A_LOCK_ADDR (HW_REG_BASE + REG_MBK_A_LOCK_OFFSET) 638 #define reg_MI_MBK_A_LOCK (*( REGType8v *) REG_MBK_A_LOCK_ADDR) 639 640 /* MBK_B_LOCK */ 641 642 #define REG_MBK_B_LOCK_OFFSET 0x4061 643 #define REG_MBK_B_LOCK_ADDR (HW_REG_BASE + REG_MBK_B_LOCK_OFFSET) 644 #define reg_MI_MBK_B_LOCK (*( REGType8v *) REG_MBK_B_LOCK_ADDR) 645 646 /* MBK_C_LOCK */ 647 648 #define REG_MBK_C_LOCK_OFFSET 0x4062 649 #define REG_MBK_C_LOCK_ADDR (HW_REG_BASE + REG_MBK_C_LOCK_OFFSET) 650 #define reg_MI_MBK_C_LOCK (*( REGType8v *) REG_MBK_C_LOCK_ADDR) 651 652 653 /* 654 * Definitions of Register fields 655 */ 656 657 658 /* DMA0SAD */ 659 660 #define REG_MI_DMA0SAD_DMASRC_SHIFT 0 661 #define REG_MI_DMA0SAD_DMASRC_SIZE 28 662 #define REG_MI_DMA0SAD_DMASRC_MASK 0x0fffffff 663 664 #ifndef SDK_ASM 665 #define REG_MI_DMA0SAD_FIELD( dmasrc ) \ 666 (u32)( \ 667 ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) 668 #endif 669 670 671 /* DMA0DAD */ 672 673 #define REG_MI_DMA0DAD_DMADEST_SHIFT 0 674 #define REG_MI_DMA0DAD_DMADEST_SIZE 28 675 #define REG_MI_DMA0DAD_DMADEST_MASK 0x0fffffff 676 677 #ifndef SDK_ASM 678 #define REG_MI_DMA0DAD_FIELD( dmadest ) \ 679 (u32)( \ 680 ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) 681 #endif 682 683 684 /* DMA0CNT */ 685 686 #define REG_MI_DMA0CNT_E_SHIFT 31 687 #define REG_MI_DMA0CNT_E_SIZE 1 688 #define REG_MI_DMA0CNT_E_MASK 0x80000000 689 690 #define REG_MI_DMA0CNT_I_SHIFT 30 691 #define REG_MI_DMA0CNT_I_SIZE 1 692 #define REG_MI_DMA0CNT_I_MASK 0x40000000 693 694 #define REG_MI_DMA0CNT_MODE_SHIFT 27 695 #define REG_MI_DMA0CNT_MODE_SIZE 3 696 #define REG_MI_DMA0CNT_MODE_MASK 0x38000000 697 698 #define REG_MI_DMA0CNT_SB_SHIFT 26 699 #define REG_MI_DMA0CNT_SB_SIZE 1 700 #define REG_MI_DMA0CNT_SB_MASK 0x04000000 701 702 #define REG_MI_DMA0CNT_CM_SHIFT 25 703 #define REG_MI_DMA0CNT_CM_SIZE 1 704 #define REG_MI_DMA0CNT_CM_MASK 0x02000000 705 706 #define REG_MI_DMA0CNT_SAR_SHIFT 23 707 #define REG_MI_DMA0CNT_SAR_SIZE 2 708 #define REG_MI_DMA0CNT_SAR_MASK 0x01800000 709 710 #define REG_MI_DMA0CNT_DAR_SHIFT 21 711 #define REG_MI_DMA0CNT_DAR_SIZE 2 712 #define REG_MI_DMA0CNT_DAR_MASK 0x00600000 713 714 #define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 715 #define REG_MI_DMA0CNT_WORDCNT_SIZE 21 716 #define REG_MI_DMA0CNT_WORDCNT_MASK 0x001fffff 717 718 #ifndef SDK_ASM 719 #define REG_MI_DMA0CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 720 (u32)( \ 721 ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \ 722 ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \ 723 ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \ 724 ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \ 725 ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \ 726 ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \ 727 ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \ 728 ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) 729 #endif 730 731 732 /* DMA1SAD */ 733 734 #define REG_MI_DMA1SAD_DMASRC_SHIFT 0 735 #define REG_MI_DMA1SAD_DMASRC_SIZE 28 736 #define REG_MI_DMA1SAD_DMASRC_MASK 0x0fffffff 737 738 #ifndef SDK_ASM 739 #define REG_MI_DMA1SAD_FIELD( dmasrc ) \ 740 (u32)( \ 741 ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) 742 #endif 743 744 745 /* DMA1DAD */ 746 747 #define REG_MI_DMA1DAD_DMADEST_SHIFT 0 748 #define REG_MI_DMA1DAD_DMADEST_SIZE 28 749 #define REG_MI_DMA1DAD_DMADEST_MASK 0x0fffffff 750 751 #ifndef SDK_ASM 752 #define REG_MI_DMA1DAD_FIELD( dmadest ) \ 753 (u32)( \ 754 ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) 755 #endif 756 757 758 /* DMA1CNT */ 759 760 #define REG_MI_DMA1CNT_E_SHIFT 31 761 #define REG_MI_DMA1CNT_E_SIZE 1 762 #define REG_MI_DMA1CNT_E_MASK 0x80000000 763 764 #define REG_MI_DMA1CNT_I_SHIFT 30 765 #define REG_MI_DMA1CNT_I_SIZE 1 766 #define REG_MI_DMA1CNT_I_MASK 0x40000000 767 768 #define REG_MI_DMA1CNT_MODE_SHIFT 27 769 #define REG_MI_DMA1CNT_MODE_SIZE 3 770 #define REG_MI_DMA1CNT_MODE_MASK 0x38000000 771 772 #define REG_MI_DMA1CNT_SB_SHIFT 26 773 #define REG_MI_DMA1CNT_SB_SIZE 1 774 #define REG_MI_DMA1CNT_SB_MASK 0x04000000 775 776 #define REG_MI_DMA1CNT_CM_SHIFT 25 777 #define REG_MI_DMA1CNT_CM_SIZE 1 778 #define REG_MI_DMA1CNT_CM_MASK 0x02000000 779 780 #define REG_MI_DMA1CNT_SAR_SHIFT 23 781 #define REG_MI_DMA1CNT_SAR_SIZE 2 782 #define REG_MI_DMA1CNT_SAR_MASK 0x01800000 783 784 #define REG_MI_DMA1CNT_DAR_SHIFT 21 785 #define REG_MI_DMA1CNT_DAR_SIZE 2 786 #define REG_MI_DMA1CNT_DAR_MASK 0x00600000 787 788 #define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 789 #define REG_MI_DMA1CNT_WORDCNT_SIZE 21 790 #define REG_MI_DMA1CNT_WORDCNT_MASK 0x001fffff 791 792 #ifndef SDK_ASM 793 #define REG_MI_DMA1CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 794 (u32)( \ 795 ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \ 796 ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \ 797 ((u32)(mode) << REG_MI_DMA1CNT_MODE_SHIFT) | \ 798 ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \ 799 ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \ 800 ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \ 801 ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \ 802 ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) 803 #endif 804 805 806 /* DMA2SAD */ 807 808 #define REG_MI_DMA2SAD_DMASRC_SHIFT 0 809 #define REG_MI_DMA2SAD_DMASRC_SIZE 28 810 #define REG_MI_DMA2SAD_DMASRC_MASK 0x0fffffff 811 812 #ifndef SDK_ASM 813 #define REG_MI_DMA2SAD_FIELD( dmasrc ) \ 814 (u32)( \ 815 ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) 816 #endif 817 818 819 /* DMA2DAD */ 820 821 #define REG_MI_DMA2DAD_DMADEST_SHIFT 0 822 #define REG_MI_DMA2DAD_DMADEST_SIZE 28 823 #define REG_MI_DMA2DAD_DMADEST_MASK 0x0fffffff 824 825 #ifndef SDK_ASM 826 #define REG_MI_DMA2DAD_FIELD( dmadest ) \ 827 (u32)( \ 828 ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) 829 #endif 830 831 832 /* DMA2CNT */ 833 834 #define REG_MI_DMA2CNT_E_SHIFT 31 835 #define REG_MI_DMA2CNT_E_SIZE 1 836 #define REG_MI_DMA2CNT_E_MASK 0x80000000 837 838 #define REG_MI_DMA2CNT_I_SHIFT 30 839 #define REG_MI_DMA2CNT_I_SIZE 1 840 #define REG_MI_DMA2CNT_I_MASK 0x40000000 841 842 #define REG_MI_DMA2CNT_MODE_SHIFT 27 843 #define REG_MI_DMA2CNT_MODE_SIZE 3 844 #define REG_MI_DMA2CNT_MODE_MASK 0x38000000 845 846 #define REG_MI_DMA2CNT_SB_SHIFT 26 847 #define REG_MI_DMA2CNT_SB_SIZE 1 848 #define REG_MI_DMA2CNT_SB_MASK 0x04000000 849 850 #define REG_MI_DMA2CNT_CM_SHIFT 25 851 #define REG_MI_DMA2CNT_CM_SIZE 1 852 #define REG_MI_DMA2CNT_CM_MASK 0x02000000 853 854 #define REG_MI_DMA2CNT_SAR_SHIFT 23 855 #define REG_MI_DMA2CNT_SAR_SIZE 2 856 #define REG_MI_DMA2CNT_SAR_MASK 0x01800000 857 858 #define REG_MI_DMA2CNT_DAR_SHIFT 21 859 #define REG_MI_DMA2CNT_DAR_SIZE 2 860 #define REG_MI_DMA2CNT_DAR_MASK 0x00600000 861 862 #define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 863 #define REG_MI_DMA2CNT_WORDCNT_SIZE 21 864 #define REG_MI_DMA2CNT_WORDCNT_MASK 0x001fffff 865 866 #ifndef SDK_ASM 867 #define REG_MI_DMA2CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 868 (u32)( \ 869 ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \ 870 ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \ 871 ((u32)(mode) << REG_MI_DMA2CNT_MODE_SHIFT) | \ 872 ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \ 873 ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \ 874 ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \ 875 ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \ 876 ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) 877 #endif 878 879 880 /* DMA3SAD */ 881 882 #define REG_MI_DMA3SAD_DMASRC_SHIFT 0 883 #define REG_MI_DMA3SAD_DMASRC_SIZE 28 884 #define REG_MI_DMA3SAD_DMASRC_MASK 0x0fffffff 885 886 #ifndef SDK_ASM 887 #define REG_MI_DMA3SAD_FIELD( dmasrc ) \ 888 (u32)( \ 889 ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) 890 #endif 891 892 893 /* DMA3DAD */ 894 895 #define REG_MI_DMA3DAD_DMADEST_SHIFT 0 896 #define REG_MI_DMA3DAD_DMADEST_SIZE 28 897 #define REG_MI_DMA3DAD_DMADEST_MASK 0x0fffffff 898 899 #ifndef SDK_ASM 900 #define REG_MI_DMA3DAD_FIELD( dmadest ) \ 901 (u32)( \ 902 ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) 903 #endif 904 905 906 /* DMA3CNT */ 907 908 #define REG_MI_DMA3CNT_E_SHIFT 31 909 #define REG_MI_DMA3CNT_E_SIZE 1 910 #define REG_MI_DMA3CNT_E_MASK 0x80000000 911 912 #define REG_MI_DMA3CNT_I_SHIFT 30 913 #define REG_MI_DMA3CNT_I_SIZE 1 914 #define REG_MI_DMA3CNT_I_MASK 0x40000000 915 916 #define REG_MI_DMA3CNT_MODE_SHIFT 27 917 #define REG_MI_DMA3CNT_MODE_SIZE 3 918 #define REG_MI_DMA3CNT_MODE_MASK 0x38000000 919 920 #define REG_MI_DMA3CNT_SB_SHIFT 26 921 #define REG_MI_DMA3CNT_SB_SIZE 1 922 #define REG_MI_DMA3CNT_SB_MASK 0x04000000 923 924 #define REG_MI_DMA3CNT_CM_SHIFT 25 925 #define REG_MI_DMA3CNT_CM_SIZE 1 926 #define REG_MI_DMA3CNT_CM_MASK 0x02000000 927 928 #define REG_MI_DMA3CNT_SAR_SHIFT 23 929 #define REG_MI_DMA3CNT_SAR_SIZE 2 930 #define REG_MI_DMA3CNT_SAR_MASK 0x01800000 931 932 #define REG_MI_DMA3CNT_DAR_SHIFT 21 933 #define REG_MI_DMA3CNT_DAR_SIZE 2 934 #define REG_MI_DMA3CNT_DAR_MASK 0x00600000 935 936 #define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 937 #define REG_MI_DMA3CNT_WORDCNT_SIZE 21 938 #define REG_MI_DMA3CNT_WORDCNT_MASK 0x001fffff 939 940 #ifndef SDK_ASM 941 #define REG_MI_DMA3CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 942 (u32)( \ 943 ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \ 944 ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \ 945 ((u32)(mode) << REG_MI_DMA3CNT_MODE_SHIFT) | \ 946 ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \ 947 ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \ 948 ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \ 949 ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \ 950 ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) 951 #endif 952 953 954 /* DMA0_CLR_DATA */ 955 956 /* DMA1_CLR_DATA */ 957 958 /* DMA2_CLR_DATA */ 959 960 /* DMA3_CLR_DATA */ 961 962 /* NDMAGCNT */ 963 964 #define REG_MI_NDMAGCNT_ARBITER_SHIFT 31 965 #define REG_MI_NDMAGCNT_ARBITER_SIZE 1 966 #define REG_MI_NDMAGCNT_ARBITER_MASK 0x80000000 967 968 #define REG_MI_NDMAGCNT_CPUCYCLE_SHIFT 16 969 #define REG_MI_NDMAGCNT_CPUCYCLE_SIZE 4 970 #define REG_MI_NDMAGCNT_CPUCYCLE_MASK 0x000f0000 971 972 #ifndef SDK_ASM 973 #define REG_MI_NDMAGCNT_FIELD( arbiter, cpucycle ) \ 974 (u32)( \ 975 ((u32)(arbiter) << REG_MI_NDMAGCNT_ARBITER_SHIFT) | \ 976 ((u32)(cpucycle) << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT)) 977 #endif 978 979 980 /* NDMA0SAD */ 981 982 #define REG_MI_NDMA0SAD_DMASRC_SHIFT 2 983 #define REG_MI_NDMA0SAD_DMASRC_SIZE 30 984 #define REG_MI_NDMA0SAD_DMASRC_MASK 0xfffffffc 985 986 #ifndef SDK_ASM 987 #define REG_MI_NDMA0SAD_FIELD( dmasrc ) \ 988 (u32)( \ 989 ((u32)(dmasrc) << REG_MI_NDMA0SAD_DMASRC_SHIFT)) 990 #endif 991 992 993 /* NDAM0DAD */ 994 995 #define REG_MI_NDAM0DAD_DMADEST_SHIFT 2 996 #define REG_MI_NDAM0DAD_DMADEST_SIZE 30 997 #define REG_MI_NDAM0DAD_DMADEST_MASK 0xfffffffc 998 999 #ifndef SDK_ASM 1000 #define REG_MI_NDAM0DAD_FIELD( dmadest ) \ 1001 (u32)( \ 1002 ((u32)(dmadest) << REG_MI_NDAM0DAD_DMADEST_SHIFT)) 1003 #endif 1004 1005 1006 /* NDMA0TCNT */ 1007 1008 #define REG_MI_NDMA0TCNT_TOTALCNT_SHIFT 0 1009 #define REG_MI_NDMA0TCNT_TOTALCNT_SIZE 28 1010 #define REG_MI_NDMA0TCNT_TOTALCNT_MASK 0x0fffffff 1011 1012 #ifndef SDK_ASM 1013 #define REG_MI_NDMA0TCNT_FIELD( totalcnt ) \ 1014 (u32)( \ 1015 ((u32)(totalcnt) << REG_MI_NDMA0TCNT_TOTALCNT_SHIFT)) 1016 #endif 1017 1018 1019 /* NDMA0WCNT */ 1020 1021 #define REG_MI_NDMA0WCNT_WORDCNT_SHIFT 0 1022 #define REG_MI_NDMA0WCNT_WORDCNT_SIZE 24 1023 #define REG_MI_NDMA0WCNT_WORDCNT_MASK 0x00ffffff 1024 1025 #ifndef SDK_ASM 1026 #define REG_MI_NDMA0WCNT_FIELD( wordcnt ) \ 1027 (u32)( \ 1028 ((u32)(wordcnt) << REG_MI_NDMA0WCNT_WORDCNT_SHIFT)) 1029 #endif 1030 1031 1032 /* NDMA0BCNT */ 1033 1034 #define REG_MI_NDMA0BCNT_PS_SHIFT 16 1035 #define REG_MI_NDMA0BCNT_PS_SIZE 2 1036 #define REG_MI_NDMA0BCNT_PS_MASK 0x00030000 1037 1038 #define REG_MI_NDMA0BCNT_ICNT_SHIFT 0 1039 #define REG_MI_NDMA0BCNT_ICNT_SIZE 16 1040 #define REG_MI_NDMA0BCNT_ICNT_MASK 0x0000ffff 1041 1042 #ifndef SDK_ASM 1043 #define REG_MI_NDMA0BCNT_FIELD( ps, icnt ) \ 1044 (u32)( \ 1045 ((u32)(ps) << REG_MI_NDMA0BCNT_PS_SHIFT) | \ 1046 ((u32)(icnt) << REG_MI_NDMA0BCNT_ICNT_SHIFT)) 1047 #endif 1048 1049 1050 /* NDMA0FDATA */ 1051 1052 #define REG_MI_NDMA0FDATA_FDATA_SHIFT 0 1053 #define REG_MI_NDMA0FDATA_FDATA_SIZE 32 1054 #define REG_MI_NDMA0FDATA_FDATA_MASK 0xffffffff 1055 1056 #ifndef SDK_ASM 1057 #define REG_MI_NDMA0FDATA_FIELD( fdata ) \ 1058 (u32)( \ 1059 ((u32)(fdata) << REG_MI_NDMA0FDATA_FDATA_SHIFT)) 1060 #endif 1061 1062 1063 /* NDMA0CNT */ 1064 1065 #define REG_MI_NDMA0CNT_E_SHIFT 31 1066 #define REG_MI_NDMA0CNT_E_SIZE 1 1067 #define REG_MI_NDMA0CNT_E_MASK 0x80000000 1068 1069 #define REG_MI_NDMA0CNT_I_SHIFT 30 1070 #define REG_MI_NDMA0CNT_I_SIZE 1 1071 #define REG_MI_NDMA0CNT_I_MASK 0x40000000 1072 1073 #define REG_MI_NDMA0CNT_CM_SHIFT 29 1074 #define REG_MI_NDMA0CNT_CM_SIZE 1 1075 #define REG_MI_NDMA0CNT_CM_MASK 0x20000000 1076 1077 #define REG_MI_NDMA0CNT_IM_SHIFT 28 1078 #define REG_MI_NDMA0CNT_IM_SIZE 1 1079 #define REG_MI_NDMA0CNT_IM_MASK 0x10000000 1080 1081 #define REG_MI_NDMA0CNT_MODE_SHIFT 24 1082 #define REG_MI_NDMA0CNT_MODE_SIZE 4 1083 #define REG_MI_NDMA0CNT_MODE_MASK 0x0f000000 1084 1085 #define REG_MI_NDMA0CNT_WORDCNT_SHIFT 16 1086 #define REG_MI_NDMA0CNT_WORDCNT_SIZE 4 1087 #define REG_MI_NDMA0CNT_WORDCNT_MASK 0x000f0000 1088 1089 #define REG_MI_NDMA0CNT_SRL_SHIFT 15 1090 #define REG_MI_NDMA0CNT_SRL_SIZE 1 1091 #define REG_MI_NDMA0CNT_SRL_MASK 0x00008000 1092 1093 #define REG_MI_NDMA0CNT_SAR_SHIFT 13 1094 #define REG_MI_NDMA0CNT_SAR_SIZE 2 1095 #define REG_MI_NDMA0CNT_SAR_MASK 0x00006000 1096 1097 #define REG_MI_NDMA0CNT_DRL_SHIFT 12 1098 #define REG_MI_NDMA0CNT_DRL_SIZE 1 1099 #define REG_MI_NDMA0CNT_DRL_MASK 0x00001000 1100 1101 #define REG_MI_NDMA0CNT_DAR_SHIFT 10 1102 #define REG_MI_NDMA0CNT_DAR_SIZE 2 1103 #define REG_MI_NDMA0CNT_DAR_MASK 0x00000c00 1104 1105 #ifndef SDK_ASM 1106 #define REG_MI_NDMA0CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ 1107 (u32)( \ 1108 ((u32)(e) << REG_MI_NDMA0CNT_E_SHIFT) | \ 1109 ((u32)(i) << REG_MI_NDMA0CNT_I_SHIFT) | \ 1110 ((u32)(cm) << REG_MI_NDMA0CNT_CM_SHIFT) | \ 1111 ((u32)(im) << REG_MI_NDMA0CNT_IM_SHIFT) | \ 1112 ((u32)(mode) << REG_MI_NDMA0CNT_MODE_SHIFT) | \ 1113 ((u32)(wordcnt) << REG_MI_NDMA0CNT_WORDCNT_SHIFT) | \ 1114 ((u32)(srl) << REG_MI_NDMA0CNT_SRL_SHIFT) | \ 1115 ((u32)(sar) << REG_MI_NDMA0CNT_SAR_SHIFT) | \ 1116 ((u32)(drl) << REG_MI_NDMA0CNT_DRL_SHIFT) | \ 1117 ((u32)(dar) << REG_MI_NDMA0CNT_DAR_SHIFT)) 1118 #endif 1119 1120 1121 /* NDMA1SAD */ 1122 1123 #define REG_MI_NDMA1SAD_DMASRC_SHIFT 2 1124 #define REG_MI_NDMA1SAD_DMASRC_SIZE 30 1125 #define REG_MI_NDMA1SAD_DMASRC_MASK 0xfffffffc 1126 1127 #ifndef SDK_ASM 1128 #define REG_MI_NDMA1SAD_FIELD( dmasrc ) \ 1129 (u32)( \ 1130 ((u32)(dmasrc) << REG_MI_NDMA1SAD_DMASRC_SHIFT)) 1131 #endif 1132 1133 1134 /* NDAM1DAD */ 1135 1136 #define REG_MI_NDAM1DAD_DMADEST_SHIFT 2 1137 #define REG_MI_NDAM1DAD_DMADEST_SIZE 30 1138 #define REG_MI_NDAM1DAD_DMADEST_MASK 0xfffffffc 1139 1140 #ifndef SDK_ASM 1141 #define REG_MI_NDAM1DAD_FIELD( dmadest ) \ 1142 (u32)( \ 1143 ((u32)(dmadest) << REG_MI_NDAM1DAD_DMADEST_SHIFT)) 1144 #endif 1145 1146 1147 /* NDMA1TCNT */ 1148 1149 #define REG_MI_NDMA1TCNT_TOTALCNT_SHIFT 0 1150 #define REG_MI_NDMA1TCNT_TOTALCNT_SIZE 28 1151 #define REG_MI_NDMA1TCNT_TOTALCNT_MASK 0x0fffffff 1152 1153 #ifndef SDK_ASM 1154 #define REG_MI_NDMA1TCNT_FIELD( totalcnt ) \ 1155 (u32)( \ 1156 ((u32)(totalcnt) << REG_MI_NDMA1TCNT_TOTALCNT_SHIFT)) 1157 #endif 1158 1159 1160 /* NDMA1WCNT */ 1161 1162 #define REG_MI_NDMA1WCNT_WORDCNT_SHIFT 0 1163 #define REG_MI_NDMA1WCNT_WORDCNT_SIZE 24 1164 #define REG_MI_NDMA1WCNT_WORDCNT_MASK 0x00ffffff 1165 1166 #ifndef SDK_ASM 1167 #define REG_MI_NDMA1WCNT_FIELD( wordcnt ) \ 1168 (u32)( \ 1169 ((u32)(wordcnt) << REG_MI_NDMA1WCNT_WORDCNT_SHIFT)) 1170 #endif 1171 1172 1173 /* NDMA1BCNT */ 1174 1175 #define REG_MI_NDMA1BCNT_PS_SHIFT 16 1176 #define REG_MI_NDMA1BCNT_PS_SIZE 2 1177 #define REG_MI_NDMA1BCNT_PS_MASK 0x00030000 1178 1179 #define REG_MI_NDMA1BCNT_ICNT_SHIFT 0 1180 #define REG_MI_NDMA1BCNT_ICNT_SIZE 16 1181 #define REG_MI_NDMA1BCNT_ICNT_MASK 0x0000ffff 1182 1183 #ifndef SDK_ASM 1184 #define REG_MI_NDMA1BCNT_FIELD( ps, icnt ) \ 1185 (u32)( \ 1186 ((u32)(ps) << REG_MI_NDMA1BCNT_PS_SHIFT) | \ 1187 ((u32)(icnt) << REG_MI_NDMA1BCNT_ICNT_SHIFT)) 1188 #endif 1189 1190 1191 /* NDMA1FDATA */ 1192 1193 #define REG_MI_NDMA1FDATA_FDATA_SHIFT 0 1194 #define REG_MI_NDMA1FDATA_FDATA_SIZE 32 1195 #define REG_MI_NDMA1FDATA_FDATA_MASK 0xffffffff 1196 1197 #ifndef SDK_ASM 1198 #define REG_MI_NDMA1FDATA_FIELD( fdata ) \ 1199 (u32)( \ 1200 ((u32)(fdata) << REG_MI_NDMA1FDATA_FDATA_SHIFT)) 1201 #endif 1202 1203 1204 /* NDMA1CNT */ 1205 1206 #define REG_MI_NDMA1CNT_E_SHIFT 31 1207 #define REG_MI_NDMA1CNT_E_SIZE 1 1208 #define REG_MI_NDMA1CNT_E_MASK 0x80000000 1209 1210 #define REG_MI_NDMA1CNT_I_SHIFT 30 1211 #define REG_MI_NDMA1CNT_I_SIZE 1 1212 #define REG_MI_NDMA1CNT_I_MASK 0x40000000 1213 1214 #define REG_MI_NDMA1CNT_CM_SHIFT 29 1215 #define REG_MI_NDMA1CNT_CM_SIZE 1 1216 #define REG_MI_NDMA1CNT_CM_MASK 0x20000000 1217 1218 #define REG_MI_NDMA1CNT_IM_SHIFT 28 1219 #define REG_MI_NDMA1CNT_IM_SIZE 1 1220 #define REG_MI_NDMA1CNT_IM_MASK 0x10000000 1221 1222 #define REG_MI_NDMA1CNT_MODE_SHIFT 24 1223 #define REG_MI_NDMA1CNT_MODE_SIZE 4 1224 #define REG_MI_NDMA1CNT_MODE_MASK 0x0f000000 1225 1226 #define REG_MI_NDMA1CNT_WORDCNT_SHIFT 16 1227 #define REG_MI_NDMA1CNT_WORDCNT_SIZE 4 1228 #define REG_MI_NDMA1CNT_WORDCNT_MASK 0x000f0000 1229 1230 #define REG_MI_NDMA1CNT_SRL_SHIFT 15 1231 #define REG_MI_NDMA1CNT_SRL_SIZE 1 1232 #define REG_MI_NDMA1CNT_SRL_MASK 0x00008000 1233 1234 #define REG_MI_NDMA1CNT_SAR_SHIFT 13 1235 #define REG_MI_NDMA1CNT_SAR_SIZE 2 1236 #define REG_MI_NDMA1CNT_SAR_MASK 0x00006000 1237 1238 #define REG_MI_NDMA1CNT_DRL_SHIFT 12 1239 #define REG_MI_NDMA1CNT_DRL_SIZE 1 1240 #define REG_MI_NDMA1CNT_DRL_MASK 0x00001000 1241 1242 #define REG_MI_NDMA1CNT_DAR_SHIFT 10 1243 #define REG_MI_NDMA1CNT_DAR_SIZE 2 1244 #define REG_MI_NDMA1CNT_DAR_MASK 0x00000c00 1245 1246 #ifndef SDK_ASM 1247 #define REG_MI_NDMA1CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ 1248 (u32)( \ 1249 ((u32)(e) << REG_MI_NDMA1CNT_E_SHIFT) | \ 1250 ((u32)(i) << REG_MI_NDMA1CNT_I_SHIFT) | \ 1251 ((u32)(cm) << REG_MI_NDMA1CNT_CM_SHIFT) | \ 1252 ((u32)(im) << REG_MI_NDMA1CNT_IM_SHIFT) | \ 1253 ((u32)(mode) << REG_MI_NDMA1CNT_MODE_SHIFT) | \ 1254 ((u32)(wordcnt) << REG_MI_NDMA1CNT_WORDCNT_SHIFT) | \ 1255 ((u32)(srl) << REG_MI_NDMA1CNT_SRL_SHIFT) | \ 1256 ((u32)(sar) << REG_MI_NDMA1CNT_SAR_SHIFT) | \ 1257 ((u32)(drl) << REG_MI_NDMA1CNT_DRL_SHIFT) | \ 1258 ((u32)(dar) << REG_MI_NDMA1CNT_DAR_SHIFT)) 1259 #endif 1260 1261 1262 /* NDMA2SAD */ 1263 1264 #define REG_MI_NDMA2SAD_DMASRC_SHIFT 2 1265 #define REG_MI_NDMA2SAD_DMASRC_SIZE 30 1266 #define REG_MI_NDMA2SAD_DMASRC_MASK 0xfffffffc 1267 1268 #ifndef SDK_ASM 1269 #define REG_MI_NDMA2SAD_FIELD( dmasrc ) \ 1270 (u32)( \ 1271 ((u32)(dmasrc) << REG_MI_NDMA2SAD_DMASRC_SHIFT)) 1272 #endif 1273 1274 1275 /* NDAM2DAD */ 1276 1277 #define REG_MI_NDAM2DAD_DMADEST_SHIFT 2 1278 #define REG_MI_NDAM2DAD_DMADEST_SIZE 30 1279 #define REG_MI_NDAM2DAD_DMADEST_MASK 0xfffffffc 1280 1281 #ifndef SDK_ASM 1282 #define REG_MI_NDAM2DAD_FIELD( dmadest ) \ 1283 (u32)( \ 1284 ((u32)(dmadest) << REG_MI_NDAM2DAD_DMADEST_SHIFT)) 1285 #endif 1286 1287 1288 /* NDMA2TCNT */ 1289 1290 #define REG_MI_NDMA2TCNT_TOTALCNT_SHIFT 0 1291 #define REG_MI_NDMA2TCNT_TOTALCNT_SIZE 28 1292 #define REG_MI_NDMA2TCNT_TOTALCNT_MASK 0x0fffffff 1293 1294 #ifndef SDK_ASM 1295 #define REG_MI_NDMA2TCNT_FIELD( totalcnt ) \ 1296 (u32)( \ 1297 ((u32)(totalcnt) << REG_MI_NDMA2TCNT_TOTALCNT_SHIFT)) 1298 #endif 1299 1300 1301 /* NDMA2WCNT */ 1302 1303 #define REG_MI_NDMA2WCNT_WORDCNT_SHIFT 0 1304 #define REG_MI_NDMA2WCNT_WORDCNT_SIZE 24 1305 #define REG_MI_NDMA2WCNT_WORDCNT_MASK 0x00ffffff 1306 1307 #ifndef SDK_ASM 1308 #define REG_MI_NDMA2WCNT_FIELD( wordcnt ) \ 1309 (u32)( \ 1310 ((u32)(wordcnt) << REG_MI_NDMA2WCNT_WORDCNT_SHIFT)) 1311 #endif 1312 1313 1314 /* NDMA2BCNT */ 1315 1316 #define REG_MI_NDMA2BCNT_PS_SHIFT 16 1317 #define REG_MI_NDMA2BCNT_PS_SIZE 2 1318 #define REG_MI_NDMA2BCNT_PS_MASK 0x00030000 1319 1320 #define REG_MI_NDMA2BCNT_ICNT_SHIFT 0 1321 #define REG_MI_NDMA2BCNT_ICNT_SIZE 16 1322 #define REG_MI_NDMA2BCNT_ICNT_MASK 0x0000ffff 1323 1324 #ifndef SDK_ASM 1325 #define REG_MI_NDMA2BCNT_FIELD( ps, icnt ) \ 1326 (u32)( \ 1327 ((u32)(ps) << REG_MI_NDMA2BCNT_PS_SHIFT) | \ 1328 ((u32)(icnt) << REG_MI_NDMA2BCNT_ICNT_SHIFT)) 1329 #endif 1330 1331 1332 /* NDMA2FDATA */ 1333 1334 #define REG_MI_NDMA2FDATA_FDATA_SHIFT 0 1335 #define REG_MI_NDMA2FDATA_FDATA_SIZE 32 1336 #define REG_MI_NDMA2FDATA_FDATA_MASK 0xffffffff 1337 1338 #ifndef SDK_ASM 1339 #define REG_MI_NDMA2FDATA_FIELD( fdata ) \ 1340 (u32)( \ 1341 ((u32)(fdata) << REG_MI_NDMA2FDATA_FDATA_SHIFT)) 1342 #endif 1343 1344 1345 /* NDMA2CNT */ 1346 1347 #define REG_MI_NDMA2CNT_E_SHIFT 31 1348 #define REG_MI_NDMA2CNT_E_SIZE 1 1349 #define REG_MI_NDMA2CNT_E_MASK 0x80000000 1350 1351 #define REG_MI_NDMA2CNT_I_SHIFT 30 1352 #define REG_MI_NDMA2CNT_I_SIZE 1 1353 #define REG_MI_NDMA2CNT_I_MASK 0x40000000 1354 1355 #define REG_MI_NDMA2CNT_CM_SHIFT 29 1356 #define REG_MI_NDMA2CNT_CM_SIZE 1 1357 #define REG_MI_NDMA2CNT_CM_MASK 0x20000000 1358 1359 #define REG_MI_NDMA2CNT_IM_SHIFT 28 1360 #define REG_MI_NDMA2CNT_IM_SIZE 1 1361 #define REG_MI_NDMA2CNT_IM_MASK 0x10000000 1362 1363 #define REG_MI_NDMA2CNT_MODE_SHIFT 24 1364 #define REG_MI_NDMA2CNT_MODE_SIZE 4 1365 #define REG_MI_NDMA2CNT_MODE_MASK 0x0f000000 1366 1367 #define REG_MI_NDMA2CNT_WORDCNT_SHIFT 16 1368 #define REG_MI_NDMA2CNT_WORDCNT_SIZE 4 1369 #define REG_MI_NDMA2CNT_WORDCNT_MASK 0x000f0000 1370 1371 #define REG_MI_NDMA2CNT_SRL_SHIFT 15 1372 #define REG_MI_NDMA2CNT_SRL_SIZE 1 1373 #define REG_MI_NDMA2CNT_SRL_MASK 0x00008000 1374 1375 #define REG_MI_NDMA2CNT_SAR_SHIFT 13 1376 #define REG_MI_NDMA2CNT_SAR_SIZE 2 1377 #define REG_MI_NDMA2CNT_SAR_MASK 0x00006000 1378 1379 #define REG_MI_NDMA2CNT_DRL_SHIFT 12 1380 #define REG_MI_NDMA2CNT_DRL_SIZE 1 1381 #define REG_MI_NDMA2CNT_DRL_MASK 0x00001000 1382 1383 #define REG_MI_NDMA2CNT_DAR_SHIFT 10 1384 #define REG_MI_NDMA2CNT_DAR_SIZE 2 1385 #define REG_MI_NDMA2CNT_DAR_MASK 0x00000c00 1386 1387 #ifndef SDK_ASM 1388 #define REG_MI_NDMA2CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ 1389 (u32)( \ 1390 ((u32)(e) << REG_MI_NDMA2CNT_E_SHIFT) | \ 1391 ((u32)(i) << REG_MI_NDMA2CNT_I_SHIFT) | \ 1392 ((u32)(cm) << REG_MI_NDMA2CNT_CM_SHIFT) | \ 1393 ((u32)(im) << REG_MI_NDMA2CNT_IM_SHIFT) | \ 1394 ((u32)(mode) << REG_MI_NDMA2CNT_MODE_SHIFT) | \ 1395 ((u32)(wordcnt) << REG_MI_NDMA2CNT_WORDCNT_SHIFT) | \ 1396 ((u32)(srl) << REG_MI_NDMA2CNT_SRL_SHIFT) | \ 1397 ((u32)(sar) << REG_MI_NDMA2CNT_SAR_SHIFT) | \ 1398 ((u32)(drl) << REG_MI_NDMA2CNT_DRL_SHIFT) | \ 1399 ((u32)(dar) << REG_MI_NDMA2CNT_DAR_SHIFT)) 1400 #endif 1401 1402 1403 /* NDMA3SAD */ 1404 1405 #define REG_MI_NDMA3SAD_DMASRC_SHIFT 2 1406 #define REG_MI_NDMA3SAD_DMASRC_SIZE 30 1407 #define REG_MI_NDMA3SAD_DMASRC_MASK 0xfffffffc 1408 1409 #ifndef SDK_ASM 1410 #define REG_MI_NDMA3SAD_FIELD( dmasrc ) \ 1411 (u32)( \ 1412 ((u32)(dmasrc) << REG_MI_NDMA3SAD_DMASRC_SHIFT)) 1413 #endif 1414 1415 1416 /* NDAM3DAD */ 1417 1418 #define REG_MI_NDAM3DAD_DMADEST_SHIFT 2 1419 #define REG_MI_NDAM3DAD_DMADEST_SIZE 30 1420 #define REG_MI_NDAM3DAD_DMADEST_MASK 0xfffffffc 1421 1422 #ifndef SDK_ASM 1423 #define REG_MI_NDAM3DAD_FIELD( dmadest ) \ 1424 (u32)( \ 1425 ((u32)(dmadest) << REG_MI_NDAM3DAD_DMADEST_SHIFT)) 1426 #endif 1427 1428 1429 /* NDMA3TCNT */ 1430 1431 #define REG_MI_NDMA3TCNT_TOTALCNT_SHIFT 0 1432 #define REG_MI_NDMA3TCNT_TOTALCNT_SIZE 28 1433 #define REG_MI_NDMA3TCNT_TOTALCNT_MASK 0x0fffffff 1434 1435 #ifndef SDK_ASM 1436 #define REG_MI_NDMA3TCNT_FIELD( totalcnt ) \ 1437 (u32)( \ 1438 ((u32)(totalcnt) << REG_MI_NDMA3TCNT_TOTALCNT_SHIFT)) 1439 #endif 1440 1441 1442 /* NDMA3WCNT */ 1443 1444 #define REG_MI_NDMA3WCNT_WORDCNT_SHIFT 0 1445 #define REG_MI_NDMA3WCNT_WORDCNT_SIZE 24 1446 #define REG_MI_NDMA3WCNT_WORDCNT_MASK 0x00ffffff 1447 1448 #ifndef SDK_ASM 1449 #define REG_MI_NDMA3WCNT_FIELD( wordcnt ) \ 1450 (u32)( \ 1451 ((u32)(wordcnt) << REG_MI_NDMA3WCNT_WORDCNT_SHIFT)) 1452 #endif 1453 1454 1455 /* NDMA3BCNT */ 1456 1457 #define REG_MI_NDMA3BCNT_PS_SHIFT 16 1458 #define REG_MI_NDMA3BCNT_PS_SIZE 2 1459 #define REG_MI_NDMA3BCNT_PS_MASK 0x00030000 1460 1461 #define REG_MI_NDMA3BCNT_ICNT_SHIFT 0 1462 #define REG_MI_NDMA3BCNT_ICNT_SIZE 16 1463 #define REG_MI_NDMA3BCNT_ICNT_MASK 0x0000ffff 1464 1465 #ifndef SDK_ASM 1466 #define REG_MI_NDMA3BCNT_FIELD( ps, icnt ) \ 1467 (u32)( \ 1468 ((u32)(ps) << REG_MI_NDMA3BCNT_PS_SHIFT) | \ 1469 ((u32)(icnt) << REG_MI_NDMA3BCNT_ICNT_SHIFT)) 1470 #endif 1471 1472 1473 /* NDMA3FDATA */ 1474 1475 #define REG_MI_NDMA3FDATA_FDATA_SHIFT 0 1476 #define REG_MI_NDMA3FDATA_FDATA_SIZE 32 1477 #define REG_MI_NDMA3FDATA_FDATA_MASK 0xffffffff 1478 1479 #ifndef SDK_ASM 1480 #define REG_MI_NDMA3FDATA_FIELD( fdata ) \ 1481 (u32)( \ 1482 ((u32)(fdata) << REG_MI_NDMA3FDATA_FDATA_SHIFT)) 1483 #endif 1484 1485 1486 /* NDMA3CNT */ 1487 1488 #define REG_MI_NDMA3CNT_E_SHIFT 31 1489 #define REG_MI_NDMA3CNT_E_SIZE 1 1490 #define REG_MI_NDMA3CNT_E_MASK 0x80000000 1491 1492 #define REG_MI_NDMA3CNT_I_SHIFT 30 1493 #define REG_MI_NDMA3CNT_I_SIZE 1 1494 #define REG_MI_NDMA3CNT_I_MASK 0x40000000 1495 1496 #define REG_MI_NDMA3CNT_CM_SHIFT 29 1497 #define REG_MI_NDMA3CNT_CM_SIZE 1 1498 #define REG_MI_NDMA3CNT_CM_MASK 0x20000000 1499 1500 #define REG_MI_NDMA3CNT_IM_SHIFT 28 1501 #define REG_MI_NDMA3CNT_IM_SIZE 1 1502 #define REG_MI_NDMA3CNT_IM_MASK 0x10000000 1503 1504 #define REG_MI_NDMA3CNT_MODE_SHIFT 24 1505 #define REG_MI_NDMA3CNT_MODE_SIZE 4 1506 #define REG_MI_NDMA3CNT_MODE_MASK 0x0f000000 1507 1508 #define REG_MI_NDMA3CNT_WORDCNT_SHIFT 16 1509 #define REG_MI_NDMA3CNT_WORDCNT_SIZE 4 1510 #define REG_MI_NDMA3CNT_WORDCNT_MASK 0x000f0000 1511 1512 #define REG_MI_NDMA3CNT_SRL_SHIFT 15 1513 #define REG_MI_NDMA3CNT_SRL_SIZE 1 1514 #define REG_MI_NDMA3CNT_SRL_MASK 0x00008000 1515 1516 #define REG_MI_NDMA3CNT_SAR_SHIFT 13 1517 #define REG_MI_NDMA3CNT_SAR_SIZE 2 1518 #define REG_MI_NDMA3CNT_SAR_MASK 0x00006000 1519 1520 #define REG_MI_NDMA3CNT_DRL_SHIFT 12 1521 #define REG_MI_NDMA3CNT_DRL_SIZE 1 1522 #define REG_MI_NDMA3CNT_DRL_MASK 0x00001000 1523 1524 #define REG_MI_NDMA3CNT_DAR_SHIFT 10 1525 #define REG_MI_NDMA3CNT_DAR_SIZE 2 1526 #define REG_MI_NDMA3CNT_DAR_MASK 0x00000c00 1527 1528 #ifndef SDK_ASM 1529 #define REG_MI_NDMA3CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ 1530 (u32)( \ 1531 ((u32)(e) << REG_MI_NDMA3CNT_E_SHIFT) | \ 1532 ((u32)(i) << REG_MI_NDMA3CNT_I_SHIFT) | \ 1533 ((u32)(cm) << REG_MI_NDMA3CNT_CM_SHIFT) | \ 1534 ((u32)(im) << REG_MI_NDMA3CNT_IM_SHIFT) | \ 1535 ((u32)(mode) << REG_MI_NDMA3CNT_MODE_SHIFT) | \ 1536 ((u32)(wordcnt) << REG_MI_NDMA3CNT_WORDCNT_SHIFT) | \ 1537 ((u32)(srl) << REG_MI_NDMA3CNT_SRL_SHIFT) | \ 1538 ((u32)(sar) << REG_MI_NDMA3CNT_SAR_SHIFT) | \ 1539 ((u32)(drl) << REG_MI_NDMA3CNT_DRL_SHIFT) | \ 1540 ((u32)(dar) << REG_MI_NDMA3CNT_DAR_SHIFT)) 1541 #endif 1542 1543 1544 /* MCCNT0 */ 1545 1546 #define REG_MI_MCCNT0_E_SHIFT 15 1547 #define REG_MI_MCCNT0_E_SIZE 1 1548 #define REG_MI_MCCNT0_E_MASK 0x8000 1549 1550 #define REG_MI_MCCNT0_I_SHIFT 14 1551 #define REG_MI_MCCNT0_I_SIZE 1 1552 #define REG_MI_MCCNT0_I_MASK 0x4000 1553 1554 #define REG_MI_MCCNT0_SEL_SHIFT 13 1555 #define REG_MI_MCCNT0_SEL_SIZE 1 1556 #define REG_MI_MCCNT0_SEL_MASK 0x2000 1557 1558 #define REG_MI_MCCNT0_BUSY_SHIFT 7 1559 #define REG_MI_MCCNT0_BUSY_SIZE 1 1560 #define REG_MI_MCCNT0_BUSY_MASK 0x0080 1561 1562 #define REG_MI_MCCNT0_MODE_SHIFT 6 1563 #define REG_MI_MCCNT0_MODE_SIZE 1 1564 #define REG_MI_MCCNT0_MODE_MASK 0x0040 1565 1566 #define REG_MI_MCCNT0_BAUDRATE_SHIFT 0 1567 #define REG_MI_MCCNT0_BAUDRATE_SIZE 2 1568 #define REG_MI_MCCNT0_BAUDRATE_MASK 0x0003 1569 1570 #ifndef SDK_ASM 1571 #define REG_MI_MCCNT0_FIELD( e, i, sel, busy, mode, baudrate ) \ 1572 (u16)( \ 1573 ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \ 1574 ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \ 1575 ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \ 1576 ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \ 1577 ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \ 1578 ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) 1579 #endif 1580 1581 1582 /* MCD0 */ 1583 1584 #define REG_MI_MCD0_DATA_SHIFT 0 1585 #define REG_MI_MCD0_DATA_SIZE 8 1586 #define REG_MI_MCD0_DATA_MASK 0x00ff 1587 1588 #ifndef SDK_ASM 1589 #define REG_MI_MCD0_FIELD( data ) \ 1590 (u16)( \ 1591 ((u32)(data) << REG_MI_MCD0_DATA_SHIFT)) 1592 #endif 1593 1594 1595 /* MCD1 */ 1596 1597 /* MCCNT1 */ 1598 1599 #define REG_MI_MCCNT1_START_SHIFT 31 1600 #define REG_MI_MCCNT1_START_SIZE 1 1601 #define REG_MI_MCCNT1_START_MASK 0x80000000 1602 1603 #define REG_MI_MCCNT1_WR_SHIFT 30 1604 #define REG_MI_MCCNT1_WR_SIZE 1 1605 #define REG_MI_MCCNT1_WR_MASK 0x40000000 1606 1607 #define REG_MI_MCCNT1_RESB_SHIFT 29 1608 #define REG_MI_MCCNT1_RESB_SIZE 1 1609 #define REG_MI_MCCNT1_RESB_MASK 0x20000000 1610 1611 #define REG_MI_MCCNT1_RTM_SHIFT 28 1612 #define REG_MI_MCCNT1_RTM_SIZE 1 1613 #define REG_MI_MCCNT1_RTM_MASK 0x10000000 1614 1615 #define REG_MI_MCCNT1_CT_SHIFT 27 1616 #define REG_MI_MCCNT1_CT_SIZE 1 1617 #define REG_MI_MCCNT1_CT_MASK 0x08000000 1618 1619 #define REG_MI_MCCNT1_PC_SHIFT 24 1620 #define REG_MI_MCCNT1_PC_SIZE 3 1621 #define REG_MI_MCCNT1_PC_MASK 0x07000000 1622 1623 #define REG_MI_MCCNT1_RDY_SHIFT 23 1624 #define REG_MI_MCCNT1_RDY_SIZE 1 1625 #define REG_MI_MCCNT1_RDY_MASK 0x00800000 1626 1627 #define REG_MI_MCCNT1_L2_SHIFT 16 1628 #define REG_MI_MCCNT1_L2_SIZE 6 1629 #define REG_MI_MCCNT1_L2_MASK 0x003f0000 1630 1631 #define REG_MI_MCCNT1_SCR_SHIFT 15 1632 #define REG_MI_MCCNT1_SCR_SIZE 1 1633 #define REG_MI_MCCNT1_SCR_MASK 0x00008000 1634 1635 #define REG_MI_MCCNT1_SE_SHIFT 14 1636 #define REG_MI_MCCNT1_SE_SIZE 1 1637 #define REG_MI_MCCNT1_SE_MASK 0x00004000 1638 1639 #define REG_MI_MCCNT1_DS_SHIFT 13 1640 #define REG_MI_MCCNT1_DS_SIZE 1 1641 #define REG_MI_MCCNT1_DS_MASK 0x00002000 1642 1643 #define REG_MI_MCCNT1_L1_SHIFT 0 1644 #define REG_MI_MCCNT1_L1_SIZE 13 1645 #define REG_MI_MCCNT1_L1_MASK 0x00001fff 1646 1647 #ifndef SDK_ASM 1648 #define REG_MI_MCCNT1_FIELD( start, wr, resb, rtm, ct, pc, rdy, l2, scr, se, ds, l1 ) \ 1649 (u32)( \ 1650 ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \ 1651 ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \ 1652 ((u32)(resb) << REG_MI_MCCNT1_RESB_SHIFT) | \ 1653 ((u32)(rtm) << REG_MI_MCCNT1_RTM_SHIFT) | \ 1654 ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \ 1655 ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \ 1656 ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \ 1657 ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \ 1658 ((u32)(scr) << REG_MI_MCCNT1_SCR_SHIFT) | \ 1659 ((u32)(se) << REG_MI_MCCNT1_SE_SHIFT) | \ 1660 ((u32)(ds) << REG_MI_MCCNT1_DS_SHIFT) | \ 1661 ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT)) 1662 #endif 1663 1664 1665 /* MCCMD0 */ 1666 1667 #define REG_MI_MCCMD0_CMD3_SHIFT 24 1668 #define REG_MI_MCCMD0_CMD3_SIZE 8 1669 #define REG_MI_MCCMD0_CMD3_MASK 0xff000000 1670 1671 #define REG_MI_MCCMD0_CMD2_SHIFT 16 1672 #define REG_MI_MCCMD0_CMD2_SIZE 8 1673 #define REG_MI_MCCMD0_CMD2_MASK 0x00ff0000 1674 1675 #define REG_MI_MCCMD0_CMD1_SHIFT 8 1676 #define REG_MI_MCCMD0_CMD1_SIZE 8 1677 #define REG_MI_MCCMD0_CMD1_MASK 0x0000ff00 1678 1679 #define REG_MI_MCCMD0_CMD0_SHIFT 0 1680 #define REG_MI_MCCMD0_CMD0_SIZE 8 1681 #define REG_MI_MCCMD0_CMD0_MASK 0x000000ff 1682 1683 #ifndef SDK_ASM 1684 #define REG_MI_MCCMD0_FIELD( cmd3, cmd2, cmd1, cmd0 ) \ 1685 (u32)( \ 1686 ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \ 1687 ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \ 1688 ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \ 1689 ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) 1690 #endif 1691 1692 1693 /* MCCMD1 */ 1694 1695 #define REG_MI_MCCMD1_CMD7_SHIFT 24 1696 #define REG_MI_MCCMD1_CMD7_SIZE 8 1697 #define REG_MI_MCCMD1_CMD7_MASK 0xff000000 1698 1699 #define REG_MI_MCCMD1_CMD6_SHIFT 16 1700 #define REG_MI_MCCMD1_CMD6_SIZE 8 1701 #define REG_MI_MCCMD1_CMD6_MASK 0x00ff0000 1702 1703 #define REG_MI_MCCMD1_CMD5_SHIFT 8 1704 #define REG_MI_MCCMD1_CMD5_SIZE 8 1705 #define REG_MI_MCCMD1_CMD5_MASK 0x0000ff00 1706 1707 #define REG_MI_MCCMD1_CMD4_SHIFT 0 1708 #define REG_MI_MCCMD1_CMD4_SIZE 8 1709 #define REG_MI_MCCMD1_CMD4_MASK 0x000000ff 1710 1711 #ifndef SDK_ASM 1712 #define REG_MI_MCCMD1_FIELD( cmd7, cmd6, cmd5, cmd4 ) \ 1713 (u32)( \ 1714 ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \ 1715 ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \ 1716 ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \ 1717 ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) 1718 #endif 1719 1720 1721 /* MCCNT0_A */ 1722 1723 #define REG_MI_MCCNT0_A_E_SHIFT 15 1724 #define REG_MI_MCCNT0_A_E_SIZE 1 1725 #define REG_MI_MCCNT0_A_E_MASK 0x8000 1726 1727 #define REG_MI_MCCNT0_A_I_SHIFT 14 1728 #define REG_MI_MCCNT0_A_I_SIZE 1 1729 #define REG_MI_MCCNT0_A_I_MASK 0x4000 1730 1731 #define REG_MI_MCCNT0_A_SEL_SHIFT 13 1732 #define REG_MI_MCCNT0_A_SEL_SIZE 1 1733 #define REG_MI_MCCNT0_A_SEL_MASK 0x2000 1734 1735 #define REG_MI_MCCNT0_A_BUSY_SHIFT 7 1736 #define REG_MI_MCCNT0_A_BUSY_SIZE 1 1737 #define REG_MI_MCCNT0_A_BUSY_MASK 0x0080 1738 1739 #define REG_MI_MCCNT0_A_MODE_SHIFT 6 1740 #define REG_MI_MCCNT0_A_MODE_SIZE 1 1741 #define REG_MI_MCCNT0_A_MODE_MASK 0x0040 1742 1743 #define REG_MI_MCCNT0_A_BAUDRATE_SHIFT 0 1744 #define REG_MI_MCCNT0_A_BAUDRATE_SIZE 2 1745 #define REG_MI_MCCNT0_A_BAUDRATE_MASK 0x0003 1746 1747 #ifndef SDK_ASM 1748 #define REG_MI_MCCNT0_A_FIELD( e, i, sel, busy, mode, baudrate ) \ 1749 (u16)( \ 1750 ((u32)(e) << REG_MI_MCCNT0_A_E_SHIFT) | \ 1751 ((u32)(i) << REG_MI_MCCNT0_A_I_SHIFT) | \ 1752 ((u32)(sel) << REG_MI_MCCNT0_A_SEL_SHIFT) | \ 1753 ((u32)(busy) << REG_MI_MCCNT0_A_BUSY_SHIFT) | \ 1754 ((u32)(mode) << REG_MI_MCCNT0_A_MODE_SHIFT) | \ 1755 ((u32)(baudrate) << REG_MI_MCCNT0_A_BAUDRATE_SHIFT)) 1756 #endif 1757 1758 1759 /* MCD0_A */ 1760 1761 #define REG_MI_MCD0_A_DATA_SHIFT 0 1762 #define REG_MI_MCD0_A_DATA_SIZE 8 1763 #define REG_MI_MCD0_A_DATA_MASK 0x00ff 1764 1765 #ifndef SDK_ASM 1766 #define REG_MI_MCD0_A_FIELD( data ) \ 1767 (u16)( \ 1768 ((u32)(data) << REG_MI_MCD0_A_DATA_SHIFT)) 1769 #endif 1770 1771 1772 /* MCD1_A */ 1773 1774 #define REG_MI_MCD1_A_DATA_SHIFT 0 1775 #define REG_MI_MCD1_A_DATA_SIZE 32 1776 #define REG_MI_MCD1_A_DATA_MASK 0xffffffff 1777 1778 #ifndef SDK_ASM 1779 #define REG_MI_MCD1_A_FIELD( data ) \ 1780 (u32)( \ 1781 ((u32)(data) << REG_MI_MCD1_A_DATA_SHIFT)) 1782 #endif 1783 1784 1785 /* MCCNT1_A */ 1786 1787 #define REG_MI_MCCNT1_A_START_SHIFT 31 1788 #define REG_MI_MCCNT1_A_START_SIZE 1 1789 #define REG_MI_MCCNT1_A_START_MASK 0x80000000 1790 1791 #define REG_MI_MCCNT1_A_WR_SHIFT 30 1792 #define REG_MI_MCCNT1_A_WR_SIZE 1 1793 #define REG_MI_MCCNT1_A_WR_MASK 0x40000000 1794 1795 #define REG_MI_MCCNT1_A_RESB_SHIFT 29 1796 #define REG_MI_MCCNT1_A_RESB_SIZE 1 1797 #define REG_MI_MCCNT1_A_RESB_MASK 0x20000000 1798 1799 #define REG_MI_MCCNT1_A_TRM_SHIFT 28 1800 #define REG_MI_MCCNT1_A_TRM_SIZE 1 1801 #define REG_MI_MCCNT1_A_TRM_MASK 0x10000000 1802 1803 #define REG_MI_MCCNT1_A_CT_SHIFT 27 1804 #define REG_MI_MCCNT1_A_CT_SIZE 1 1805 #define REG_MI_MCCNT1_A_CT_MASK 0x08000000 1806 1807 #define REG_MI_MCCNT1_A_PC_SHIFT 24 1808 #define REG_MI_MCCNT1_A_PC_SIZE 3 1809 #define REG_MI_MCCNT1_A_PC_MASK 0x07000000 1810 1811 #define REG_MI_MCCNT1_A_RDY_SHIFT 23 1812 #define REG_MI_MCCNT1_A_RDY_SIZE 1 1813 #define REG_MI_MCCNT1_A_RDY_MASK 0x00800000 1814 1815 #define REG_MI_MCCNT1_A_CS_SHIFT 22 1816 #define REG_MI_MCCNT1_A_CS_SIZE 1 1817 #define REG_MI_MCCNT1_A_CS_MASK 0x00400000 1818 1819 #define REG_MI_MCCNT1_A_L2_SHIFT 16 1820 #define REG_MI_MCCNT1_A_L2_SIZE 6 1821 #define REG_MI_MCCNT1_A_L2_MASK 0x003f0000 1822 1823 #define REG_MI_MCCNT1_A_SCR_SHIFT 15 1824 #define REG_MI_MCCNT1_A_SCR_SIZE 1 1825 #define REG_MI_MCCNT1_A_SCR_MASK 0x00008000 1826 1827 #define REG_MI_MCCNT1_A_SE_SHIFT 14 1828 #define REG_MI_MCCNT1_A_SE_SIZE 1 1829 #define REG_MI_MCCNT1_A_SE_MASK 0x00004000 1830 1831 #define REG_MI_MCCNT1_A_DS_SHIFT 13 1832 #define REG_MI_MCCNT1_A_DS_SIZE 1 1833 #define REG_MI_MCCNT1_A_DS_MASK 0x00002000 1834 1835 #define REG_MI_MCCNT1_A_L1_SHIFT 0 1836 #define REG_MI_MCCNT1_A_L1_SIZE 13 1837 #define REG_MI_MCCNT1_A_L1_MASK 0x00001fff 1838 1839 #ifndef SDK_ASM 1840 #define REG_MI_MCCNT1_A_FIELD( start, wr, resb, trm, ct, pc, rdy, cs, l2, scr, se, ds, l1 ) \ 1841 (u32)( \ 1842 ((u32)(start) << REG_MI_MCCNT1_A_START_SHIFT) | \ 1843 ((u32)(wr) << REG_MI_MCCNT1_A_WR_SHIFT) | \ 1844 ((u32)(resb) << REG_MI_MCCNT1_A_RESB_SHIFT) | \ 1845 ((u32)(trm) << REG_MI_MCCNT1_A_TRM_SHIFT) | \ 1846 ((u32)(ct) << REG_MI_MCCNT1_A_CT_SHIFT) | \ 1847 ((u32)(pc) << REG_MI_MCCNT1_A_PC_SHIFT) | \ 1848 ((u32)(rdy) << REG_MI_MCCNT1_A_RDY_SHIFT) | \ 1849 ((u32)(cs) << REG_MI_MCCNT1_A_CS_SHIFT) | \ 1850 ((u32)(l2) << REG_MI_MCCNT1_A_L2_SHIFT) | \ 1851 ((u32)(scr) << REG_MI_MCCNT1_A_SCR_SHIFT) | \ 1852 ((u32)(se) << REG_MI_MCCNT1_A_SE_SHIFT) | \ 1853 ((u32)(ds) << REG_MI_MCCNT1_A_DS_SHIFT) | \ 1854 ((u32)(l1) << REG_MI_MCCNT1_A_L1_SHIFT)) 1855 #endif 1856 1857 1858 /* MCCMD0_A */ 1859 1860 #define REG_MI_MCCMD0_A_CMD3_SHIFT 24 1861 #define REG_MI_MCCMD0_A_CMD3_SIZE 8 1862 #define REG_MI_MCCMD0_A_CMD3_MASK 0xff000000 1863 1864 #define REG_MI_MCCMD0_A_CMD2_SHIFT 16 1865 #define REG_MI_MCCMD0_A_CMD2_SIZE 8 1866 #define REG_MI_MCCMD0_A_CMD2_MASK 0x00ff0000 1867 1868 #define REG_MI_MCCMD0_A_CMD1_SHIFT 8 1869 #define REG_MI_MCCMD0_A_CMD1_SIZE 8 1870 #define REG_MI_MCCMD0_A_CMD1_MASK 0x0000ff00 1871 1872 #define REG_MI_MCCMD0_A_CMD0_SHIFT 0 1873 #define REG_MI_MCCMD0_A_CMD0_SIZE 8 1874 #define REG_MI_MCCMD0_A_CMD0_MASK 0x000000ff 1875 1876 #ifndef SDK_ASM 1877 #define REG_MI_MCCMD0_A_FIELD( cmd3, cmd2, cmd1, cmd0 ) \ 1878 (u32)( \ 1879 ((u32)(cmd3) << REG_MI_MCCMD0_A_CMD3_SHIFT) | \ 1880 ((u32)(cmd2) << REG_MI_MCCMD0_A_CMD2_SHIFT) | \ 1881 ((u32)(cmd1) << REG_MI_MCCMD0_A_CMD1_SHIFT) | \ 1882 ((u32)(cmd0) << REG_MI_MCCMD0_A_CMD0_SHIFT)) 1883 #endif 1884 1885 1886 /* MCCMD1_A */ 1887 1888 #define REG_MI_MCCMD1_A_CMD7_SHIFT 24 1889 #define REG_MI_MCCMD1_A_CMD7_SIZE 8 1890 #define REG_MI_MCCMD1_A_CMD7_MASK 0xff000000 1891 1892 #define REG_MI_MCCMD1_A_CMD6_SHIFT 16 1893 #define REG_MI_MCCMD1_A_CMD6_SIZE 8 1894 #define REG_MI_MCCMD1_A_CMD6_MASK 0x00ff0000 1895 1896 #define REG_MI_MCCMD1_A_CMD5_SHIFT 8 1897 #define REG_MI_MCCMD1_A_CMD5_SIZE 8 1898 #define REG_MI_MCCMD1_A_CMD5_MASK 0x0000ff00 1899 1900 #define REG_MI_MCCMD1_A_CMD4_SHIFT 0 1901 #define REG_MI_MCCMD1_A_CMD4_SIZE 8 1902 #define REG_MI_MCCMD1_A_CMD4_MASK 0x000000ff 1903 1904 #ifndef SDK_ASM 1905 #define REG_MI_MCCMD1_A_FIELD( cmd7, cmd6, cmd5, cmd4 ) \ 1906 (u32)( \ 1907 ((u32)(cmd7) << REG_MI_MCCMD1_A_CMD7_SHIFT) | \ 1908 ((u32)(cmd6) << REG_MI_MCCMD1_A_CMD6_SHIFT) | \ 1909 ((u32)(cmd5) << REG_MI_MCCMD1_A_CMD5_SHIFT) | \ 1910 ((u32)(cmd4) << REG_MI_MCCMD1_A_CMD4_SHIFT)) 1911 #endif 1912 1913 1914 /* MCSRC0_A */ 1915 1916 #define REG_MI_MCSRC0_A_SCRA_SHIFT 0 1917 #define REG_MI_MCSRC0_A_SCRA_SIZE 32 1918 #define REG_MI_MCSRC0_A_SCRA_MASK 0xffffffff 1919 1920 #ifndef SDK_ASM 1921 #define REG_MI_MCSRC0_A_FIELD( scra ) \ 1922 (u32)( \ 1923 ((u32)(scra) << REG_MI_MCSRC0_A_SCRA_SHIFT)) 1924 #endif 1925 1926 1927 /* MCSRC1_A */ 1928 1929 #define REG_MI_MCSRC1_A_SCRB_SHIFT 0 1930 #define REG_MI_MCSRC1_A_SCRB_SIZE 32 1931 #define REG_MI_MCSRC1_A_SCRB_MASK 0xffffffff 1932 1933 #ifndef SDK_ASM 1934 #define REG_MI_MCSRC1_A_FIELD( scrb ) \ 1935 (u32)( \ 1936 ((u32)(scrb) << REG_MI_MCSRC1_A_SCRB_SHIFT)) 1937 #endif 1938 1939 1940 /* MCSRC2_A */ 1941 1942 #define REG_MI_MCSRC2_A_SCRB_SHIFT 26 1943 #define REG_MI_MCSRC2_A_SCRB_SIZE 7 1944 #define REG_MI_MCSRC2_A_SCRB_MASK 0x1fc000000 1945 1946 #define REG_MI_MCSRC2_A_SCRA_SHIFT 0 1947 #define REG_MI_MCSRC2_A_SCRA_SIZE 7 1948 #define REG_MI_MCSRC2_A_SCRA_MASK 0x0000007f 1949 1950 #ifndef SDK_ASM 1951 #define REG_MI_MCSRC2_A_FIELD( scrb, scra ) \ 1952 (u32)( \ 1953 ((u32)(scrb) << REG_MI_MCSRC2_A_SCRB_SHIFT) | \ 1954 ((u32)(scra) << REG_MI_MCSRC2_A_SCRA_SHIFT)) 1955 #endif 1956 1957 1958 /* MCCNT0_B */ 1959 1960 #define REG_MI_MCCNT0_B_E_SHIFT 15 1961 #define REG_MI_MCCNT0_B_E_SIZE 1 1962 #define REG_MI_MCCNT0_B_E_MASK 0x8000 1963 1964 #define REG_MI_MCCNT0_B_I_SHIFT 14 1965 #define REG_MI_MCCNT0_B_I_SIZE 1 1966 #define REG_MI_MCCNT0_B_I_MASK 0x4000 1967 1968 #define REG_MI_MCCNT0_B_SEL_SHIFT 13 1969 #define REG_MI_MCCNT0_B_SEL_SIZE 1 1970 #define REG_MI_MCCNT0_B_SEL_MASK 0x2000 1971 1972 #define REG_MI_MCCNT0_B_BUSY_SHIFT 7 1973 #define REG_MI_MCCNT0_B_BUSY_SIZE 1 1974 #define REG_MI_MCCNT0_B_BUSY_MASK 0x0080 1975 1976 #define REG_MI_MCCNT0_B_MODE_SHIFT 6 1977 #define REG_MI_MCCNT0_B_MODE_SIZE 1 1978 #define REG_MI_MCCNT0_B_MODE_MASK 0x0040 1979 1980 #define REG_MI_MCCNT0_B_BAUDRATE_SHIFT 0 1981 #define REG_MI_MCCNT0_B_BAUDRATE_SIZE 2 1982 #define REG_MI_MCCNT0_B_BAUDRATE_MASK 0x0003 1983 1984 #ifndef SDK_ASM 1985 #define REG_MI_MCCNT0_B_FIELD( e, i, sel, busy, mode, baudrate ) \ 1986 (u16)( \ 1987 ((u32)(e) << REG_MI_MCCNT0_B_E_SHIFT) | \ 1988 ((u32)(i) << REG_MI_MCCNT0_B_I_SHIFT) | \ 1989 ((u32)(sel) << REG_MI_MCCNT0_B_SEL_SHIFT) | \ 1990 ((u32)(busy) << REG_MI_MCCNT0_B_BUSY_SHIFT) | \ 1991 ((u32)(mode) << REG_MI_MCCNT0_B_MODE_SHIFT) | \ 1992 ((u32)(baudrate) << REG_MI_MCCNT0_B_BAUDRATE_SHIFT)) 1993 #endif 1994 1995 1996 /* MCD0_B */ 1997 1998 #define REG_MI_MCD0_B_DATA_SHIFT 0 1999 #define REG_MI_MCD0_B_DATA_SIZE 8 2000 #define REG_MI_MCD0_B_DATA_MASK 0x00ff 2001 2002 #ifndef SDK_ASM 2003 #define REG_MI_MCD0_B_FIELD( data ) \ 2004 (u16)( \ 2005 ((u32)(data) << REG_MI_MCD0_B_DATA_SHIFT)) 2006 #endif 2007 2008 2009 /* MCD1_B */ 2010 2011 #define REG_MI_MCD1_B_DATA_SHIFT 0 2012 #define REG_MI_MCD1_B_DATA_SIZE 32 2013 #define REG_MI_MCD1_B_DATA_MASK 0xffffffff 2014 2015 #ifndef SDK_ASM 2016 #define REG_MI_MCD1_B_FIELD( data ) \ 2017 (u32)( \ 2018 ((u32)(data) << REG_MI_MCD1_B_DATA_SHIFT)) 2019 #endif 2020 2021 2022 /* MCCNT1_B */ 2023 2024 #define REG_MI_MCCNT1_B_START_SHIFT 31 2025 #define REG_MI_MCCNT1_B_START_SIZE 1 2026 #define REG_MI_MCCNT1_B_START_MASK 0x80000000 2027 2028 #define REG_MI_MCCNT1_B_WR_SHIFT 30 2029 #define REG_MI_MCCNT1_B_WR_SIZE 1 2030 #define REG_MI_MCCNT1_B_WR_MASK 0x40000000 2031 2032 #define REG_MI_MCCNT1_B_RESB_SHIFT 29 2033 #define REG_MI_MCCNT1_B_RESB_SIZE 1 2034 #define REG_MI_MCCNT1_B_RESB_MASK 0x20000000 2035 2036 #define REG_MI_MCCNT1_B_TRM_SHIFT 28 2037 #define REG_MI_MCCNT1_B_TRM_SIZE 1 2038 #define REG_MI_MCCNT1_B_TRM_MASK 0x10000000 2039 2040 #define REG_MI_MCCNT1_B_CT_SHIFT 27 2041 #define REG_MI_MCCNT1_B_CT_SIZE 1 2042 #define REG_MI_MCCNT1_B_CT_MASK 0x08000000 2043 2044 #define REG_MI_MCCNT1_B_PC_SHIFT 24 2045 #define REG_MI_MCCNT1_B_PC_SIZE 3 2046 #define REG_MI_MCCNT1_B_PC_MASK 0x07000000 2047 2048 #define REG_MI_MCCNT1_B_RDY_SHIFT 23 2049 #define REG_MI_MCCNT1_B_RDY_SIZE 1 2050 #define REG_MI_MCCNT1_B_RDY_MASK 0x00800000 2051 2052 #define REG_MI_MCCNT1_B_CS_SHIFT 22 2053 #define REG_MI_MCCNT1_B_CS_SIZE 1 2054 #define REG_MI_MCCNT1_B_CS_MASK 0x00400000 2055 2056 #define REG_MI_MCCNT1_B_L2_SHIFT 16 2057 #define REG_MI_MCCNT1_B_L2_SIZE 6 2058 #define REG_MI_MCCNT1_B_L2_MASK 0x003f0000 2059 2060 #define REG_MI_MCCNT1_B_SCR_SHIFT 15 2061 #define REG_MI_MCCNT1_B_SCR_SIZE 1 2062 #define REG_MI_MCCNT1_B_SCR_MASK 0x00008000 2063 2064 #define REG_MI_MCCNT1_B_SE_SHIFT 14 2065 #define REG_MI_MCCNT1_B_SE_SIZE 1 2066 #define REG_MI_MCCNT1_B_SE_MASK 0x00004000 2067 2068 #define REG_MI_MCCNT1_B_DS_SHIFT 13 2069 #define REG_MI_MCCNT1_B_DS_SIZE 1 2070 #define REG_MI_MCCNT1_B_DS_MASK 0x00002000 2071 2072 #define REG_MI_MCCNT1_B_L1_SHIFT 0 2073 #define REG_MI_MCCNT1_B_L1_SIZE 13 2074 #define REG_MI_MCCNT1_B_L1_MASK 0x00001fff 2075 2076 #ifndef SDK_ASM 2077 #define REG_MI_MCCNT1_B_FIELD( start, wr, resb, trm, ct, pc, rdy, cs, l2, scr, se, ds, l1 ) \ 2078 (u32)( \ 2079 ((u32)(start) << REG_MI_MCCNT1_B_START_SHIFT) | \ 2080 ((u32)(wr) << REG_MI_MCCNT1_B_WR_SHIFT) | \ 2081 ((u32)(resb) << REG_MI_MCCNT1_B_RESB_SHIFT) | \ 2082 ((u32)(trm) << REG_MI_MCCNT1_B_TRM_SHIFT) | \ 2083 ((u32)(ct) << REG_MI_MCCNT1_B_CT_SHIFT) | \ 2084 ((u32)(pc) << REG_MI_MCCNT1_B_PC_SHIFT) | \ 2085 ((u32)(rdy) << REG_MI_MCCNT1_B_RDY_SHIFT) | \ 2086 ((u32)(cs) << REG_MI_MCCNT1_B_CS_SHIFT) | \ 2087 ((u32)(l2) << REG_MI_MCCNT1_B_L2_SHIFT) | \ 2088 ((u32)(scr) << REG_MI_MCCNT1_B_SCR_SHIFT) | \ 2089 ((u32)(se) << REG_MI_MCCNT1_B_SE_SHIFT) | \ 2090 ((u32)(ds) << REG_MI_MCCNT1_B_DS_SHIFT) | \ 2091 ((u32)(l1) << REG_MI_MCCNT1_B_L1_SHIFT)) 2092 #endif 2093 2094 2095 /* MCCMD0_B */ 2096 2097 #define REG_MI_MCCMD0_B_CMD3_SHIFT 24 2098 #define REG_MI_MCCMD0_B_CMD3_SIZE 8 2099 #define REG_MI_MCCMD0_B_CMD3_MASK 0xff000000 2100 2101 #define REG_MI_MCCMD0_B_CMD2_SHIFT 16 2102 #define REG_MI_MCCMD0_B_CMD2_SIZE 8 2103 #define REG_MI_MCCMD0_B_CMD2_MASK 0x00ff0000 2104 2105 #define REG_MI_MCCMD0_B_CMD1_SHIFT 8 2106 #define REG_MI_MCCMD0_B_CMD1_SIZE 8 2107 #define REG_MI_MCCMD0_B_CMD1_MASK 0x0000ff00 2108 2109 #define REG_MI_MCCMD0_B_CMD0_SHIFT 0 2110 #define REG_MI_MCCMD0_B_CMD0_SIZE 8 2111 #define REG_MI_MCCMD0_B_CMD0_MASK 0x000000ff 2112 2113 #ifndef SDK_ASM 2114 #define REG_MI_MCCMD0_B_FIELD( cmd3, cmd2, cmd1, cmd0 ) \ 2115 (u32)( \ 2116 ((u32)(cmd3) << REG_MI_MCCMD0_B_CMD3_SHIFT) | \ 2117 ((u32)(cmd2) << REG_MI_MCCMD0_B_CMD2_SHIFT) | \ 2118 ((u32)(cmd1) << REG_MI_MCCMD0_B_CMD1_SHIFT) | \ 2119 ((u32)(cmd0) << REG_MI_MCCMD0_B_CMD0_SHIFT)) 2120 #endif 2121 2122 2123 /* MCCMD1_B */ 2124 2125 #define REG_MI_MCCMD1_B_CMD7_SHIFT 24 2126 #define REG_MI_MCCMD1_B_CMD7_SIZE 8 2127 #define REG_MI_MCCMD1_B_CMD7_MASK 0xff000000 2128 2129 #define REG_MI_MCCMD1_B_CMD6_SHIFT 16 2130 #define REG_MI_MCCMD1_B_CMD6_SIZE 8 2131 #define REG_MI_MCCMD1_B_CMD6_MASK 0x00ff0000 2132 2133 #define REG_MI_MCCMD1_B_CMD5_SHIFT 8 2134 #define REG_MI_MCCMD1_B_CMD5_SIZE 8 2135 #define REG_MI_MCCMD1_B_CMD5_MASK 0x0000ff00 2136 2137 #define REG_MI_MCCMD1_B_CMD4_SHIFT 0 2138 #define REG_MI_MCCMD1_B_CMD4_SIZE 8 2139 #define REG_MI_MCCMD1_B_CMD4_MASK 0x000000ff 2140 2141 #ifndef SDK_ASM 2142 #define REG_MI_MCCMD1_B_FIELD( cmd7, cmd6, cmd5, cmd4 ) \ 2143 (u32)( \ 2144 ((u32)(cmd7) << REG_MI_MCCMD1_B_CMD7_SHIFT) | \ 2145 ((u32)(cmd6) << REG_MI_MCCMD1_B_CMD6_SHIFT) | \ 2146 ((u32)(cmd5) << REG_MI_MCCMD1_B_CMD5_SHIFT) | \ 2147 ((u32)(cmd4) << REG_MI_MCCMD1_B_CMD4_SHIFT)) 2148 #endif 2149 2150 2151 /* MCSRC0_B */ 2152 2153 #define REG_MI_MCSRC0_B_SCRA_SHIFT 0 2154 #define REG_MI_MCSRC0_B_SCRA_SIZE 32 2155 #define REG_MI_MCSRC0_B_SCRA_MASK 0xffffffff 2156 2157 #ifndef SDK_ASM 2158 #define REG_MI_MCSRC0_B_FIELD( scra ) \ 2159 (u32)( \ 2160 ((u32)(scra) << REG_MI_MCSRC0_B_SCRA_SHIFT)) 2161 #endif 2162 2163 2164 /* MCSRC1_B */ 2165 2166 #define REG_MI_MCSRC1_B_SCRB_SHIFT 0 2167 #define REG_MI_MCSRC1_B_SCRB_SIZE 32 2168 #define REG_MI_MCSRC1_B_SCRB_MASK 0xffffffff 2169 2170 #ifndef SDK_ASM 2171 #define REG_MI_MCSRC1_B_FIELD( scrb ) \ 2172 (u32)( \ 2173 ((u32)(scrb) << REG_MI_MCSRC1_B_SCRB_SHIFT)) 2174 #endif 2175 2176 2177 /* MCSRC2_B */ 2178 2179 #define REG_MI_MCSRC2_B_SCRB_SHIFT 26 2180 #define REG_MI_MCSRC2_B_SCRB_SIZE 7 2181 #define REG_MI_MCSRC2_B_SCRB_MASK 0x1fc000000 2182 2183 #define REG_MI_MCSRC2_B_SCRA_SHIFT 0 2184 #define REG_MI_MCSRC2_B_SCRA_SIZE 7 2185 #define REG_MI_MCSRC2_B_SCRA_MASK 0x0000007f 2186 2187 #ifndef SDK_ASM 2188 #define REG_MI_MCSRC2_B_FIELD( scrb, scra ) \ 2189 (u32)( \ 2190 ((u32)(scrb) << REG_MI_MCSRC2_B_SCRB_SHIFT) | \ 2191 ((u32)(scra) << REG_MI_MCSRC2_B_SCRA_SHIFT)) 2192 #endif 2193 2194 2195 /* EXMEMCNT */ 2196 2197 #define REG_MI_EXMEMCNT_EP_SHIFT 15 2198 #define REG_MI_EXMEMCNT_EP_SIZE 1 2199 #define REG_MI_EXMEMCNT_EP_MASK 0x8000 2200 2201 #define REG_MI_EXMEMCNT_IFM_SHIFT 14 2202 #define REG_MI_EXMEMCNT_IFM_SIZE 1 2203 #define REG_MI_EXMEMCNT_IFM_MASK 0x4000 2204 2205 #define REG_MI_EXMEMCNT_CE2_SHIFT 13 2206 #define REG_MI_EXMEMCNT_CE2_SIZE 1 2207 #define REG_MI_EXMEMCNT_CE2_MASK 0x2000 2208 2209 #define REG_MI_EXMEMCNT_MPA_SHIFT 11 2210 #define REG_MI_EXMEMCNT_MPA_SIZE 1 2211 #define REG_MI_EXMEMCNT_MPA_MASK 0x0800 2212 2213 #define REG_MI_EXMEMCNT_MP_SHIFT 11 2214 #define REG_MI_EXMEMCNT_MP_SIZE 1 2215 #define REG_MI_EXMEMCNT_MP_MASK 0x0800 2216 2217 #define REG_MI_EXMEMCNT_MPB_SHIFT 10 2218 #define REG_MI_EXMEMCNT_MPB_SIZE 1 2219 #define REG_MI_EXMEMCNT_MPB_MASK 0x0400 2220 2221 #define REG_MI_EXMEMCNT_CP_SHIFT 7 2222 #define REG_MI_EXMEMCNT_CP_SIZE 1 2223 #define REG_MI_EXMEMCNT_CP_MASK 0x0080 2224 2225 #define REG_MI_EXMEMCNT_PHI_SHIFT 5 2226 #define REG_MI_EXMEMCNT_PHI_SIZE 2 2227 #define REG_MI_EXMEMCNT_PHI_MASK 0x0060 2228 2229 #define REG_MI_EXMEMCNT_ROM2nd_SHIFT 4 2230 #define REG_MI_EXMEMCNT_ROM2nd_SIZE 1 2231 #define REG_MI_EXMEMCNT_ROM2nd_MASK 0x0010 2232 2233 #define REG_MI_EXMEMCNT_ROM1st_SHIFT 2 2234 #define REG_MI_EXMEMCNT_ROM1st_SIZE 2 2235 #define REG_MI_EXMEMCNT_ROM1st_MASK 0x000c 2236 2237 #define REG_MI_EXMEMCNT_RAM_SHIFT 0 2238 #define REG_MI_EXMEMCNT_RAM_SIZE 2 2239 #define REG_MI_EXMEMCNT_RAM_MASK 0x0003 2240 2241 #ifndef SDK_ASM 2242 #define REG_MI_EXMEMCNT_FIELD( ep, ifm, ce2, mpa, mp, mpb, cp, phi, rom2nd, rom1st, ram ) \ 2243 (u16)( \ 2244 ((u32)(ep) << REG_MI_EXMEMCNT_EP_SHIFT) | \ 2245 ((u32)(ifm) << REG_MI_EXMEMCNT_IFM_SHIFT) | \ 2246 ((u32)(ce2) << REG_MI_EXMEMCNT_CE2_SHIFT) | \ 2247 ((u32)(mpa) << REG_MI_EXMEMCNT_MPA_SHIFT) | \ 2248 ((u32)(mp) << REG_MI_EXMEMCNT_MP_SHIFT) | \ 2249 ((u32)(mpb) << REG_MI_EXMEMCNT_MPB_SHIFT) | \ 2250 ((u32)(cp) << REG_MI_EXMEMCNT_CP_SHIFT) | \ 2251 ((u32)(phi) << REG_MI_EXMEMCNT_PHI_SHIFT) | \ 2252 ((u32)(rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT) | \ 2253 ((u32)(rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT) | \ 2254 ((u32)(ram) << REG_MI_EXMEMCNT_RAM_SHIFT)) 2255 #endif 2256 2257 2258 /* MC */ 2259 2260 #define REG_MI_MC_SWP_SHIFT 15 2261 #define REG_MI_MC_SWP_SIZE 1 2262 #define REG_MI_MC_SWP_MASK 0x8000 2263 2264 #define REG_MI_MC_SL2_MODE_SHIFT 6 2265 #define REG_MI_MC_SL2_MODE_SIZE 2 2266 #define REG_MI_MC_SL2_MODE_MASK 0x00c0 2267 2268 #define REG_MI_MC_SL2_CDET_SHIFT 4 2269 #define REG_MI_MC_SL2_CDET_SIZE 1 2270 #define REG_MI_MC_SL2_CDET_MASK 0x0010 2271 2272 #define REG_MI_MC_SL1_MODE_SHIFT 2 2273 #define REG_MI_MC_SL1_MODE_SIZE 2 2274 #define REG_MI_MC_SL1_MODE_MASK 0x000c 2275 2276 #define REG_MI_MC_SL1_CDET_SHIFT 0 2277 #define REG_MI_MC_SL1_CDET_SIZE 1 2278 #define REG_MI_MC_SL1_CDET_MASK 0x0001 2279 2280 #ifndef SDK_ASM 2281 #define REG_MI_MC_FIELD( swp, sl2_mode, sl2_cdet, sl1_mode, sl1_cdet ) \ 2282 (u16)( \ 2283 ((u32)(swp) << REG_MI_MC_SWP_SHIFT) | \ 2284 ((u32)(sl2_mode) << REG_MI_MC_SL2_MODE_SHIFT) | \ 2285 ((u32)(sl2_cdet) << REG_MI_MC_SL2_CDET_SHIFT) | \ 2286 ((u32)(sl1_mode) << REG_MI_MC_SL1_MODE_SHIFT) | \ 2287 ((u32)(sl1_cdet) << REG_MI_MC_SL1_CDET_SHIFT)) 2288 #endif 2289 2290 2291 /* MBK1 */ 2292 2293 #define REG_MI_MBK1_WA3_E_SHIFT 31 2294 #define REG_MI_MBK1_WA3_E_SIZE 1 2295 #define REG_MI_MBK1_WA3_E_MASK 0x80000000 2296 2297 #define REG_MI_MBK1_WA3_OF_SHIFT 26 2298 #define REG_MI_MBK1_WA3_OF_SIZE 2 2299 #define REG_MI_MBK1_WA3_OF_MASK 0x0c000000 2300 2301 #define REG_MI_MBK1_WA3_M_SHIFT 24 2302 #define REG_MI_MBK1_WA3_M_SIZE 1 2303 #define REG_MI_MBK1_WA3_M_MASK 0x01000000 2304 2305 #define REG_MI_MBK1_WA2_E_SHIFT 23 2306 #define REG_MI_MBK1_WA2_E_SIZE 1 2307 #define REG_MI_MBK1_WA2_E_MASK 0x00800000 2308 2309 #define REG_MI_MBK1_WA2_OF_SHIFT 18 2310 #define REG_MI_MBK1_WA2_OF_SIZE 2 2311 #define REG_MI_MBK1_WA2_OF_MASK 0x000c0000 2312 2313 #define REG_MI_MBK1_WA2_M_SHIFT 16 2314 #define REG_MI_MBK1_WA2_M_SIZE 1 2315 #define REG_MI_MBK1_WA2_M_MASK 0x00010000 2316 2317 #define REG_MI_MBK1_WA1_E_SHIFT 15 2318 #define REG_MI_MBK1_WA1_E_SIZE 1 2319 #define REG_MI_MBK1_WA1_E_MASK 0x00008000 2320 2321 #define REG_MI_MBK1_WA1_OF_SHIFT 10 2322 #define REG_MI_MBK1_WA1_OF_SIZE 2 2323 #define REG_MI_MBK1_WA1_OF_MASK 0x00000c00 2324 2325 #define REG_MI_MBK1_WA1_M_SHIFT 8 2326 #define REG_MI_MBK1_WA1_M_SIZE 1 2327 #define REG_MI_MBK1_WA1_M_MASK 0x00000100 2328 2329 #define REG_MI_MBK1_WA0_E_SHIFT 7 2330 #define REG_MI_MBK1_WA0_E_SIZE 1 2331 #define REG_MI_MBK1_WA0_E_MASK 0x00000080 2332 2333 #define REG_MI_MBK1_WA0_OF_SHIFT 2 2334 #define REG_MI_MBK1_WA0_OF_SIZE 2 2335 #define REG_MI_MBK1_WA0_OF_MASK 0x0000000c 2336 2337 #define REG_MI_MBK1_WA0_M_SHIFT 0 2338 #define REG_MI_MBK1_WA0_M_SIZE 1 2339 #define REG_MI_MBK1_WA0_M_MASK 0x00000001 2340 2341 #ifndef SDK_ASM 2342 #define REG_MI_MBK1_FIELD( wa3_e, wa3_of, wa3_m, wa2_e, wa2_of, wa2_m, wa1_e, wa1_of, wa1_m, wa0_e, wa0_of, wa0_m ) \ 2343 (u32)( \ 2344 ((u32)(wa3_e) << REG_MI_MBK1_WA3_E_SHIFT) | \ 2345 ((u32)(wa3_of) << REG_MI_MBK1_WA3_OF_SHIFT) | \ 2346 ((u32)(wa3_m) << REG_MI_MBK1_WA3_M_SHIFT) | \ 2347 ((u32)(wa2_e) << REG_MI_MBK1_WA2_E_SHIFT) | \ 2348 ((u32)(wa2_of) << REG_MI_MBK1_WA2_OF_SHIFT) | \ 2349 ((u32)(wa2_m) << REG_MI_MBK1_WA2_M_SHIFT) | \ 2350 ((u32)(wa1_e) << REG_MI_MBK1_WA1_E_SHIFT) | \ 2351 ((u32)(wa1_of) << REG_MI_MBK1_WA1_OF_SHIFT) | \ 2352 ((u32)(wa1_m) << REG_MI_MBK1_WA1_M_SHIFT) | \ 2353 ((u32)(wa0_e) << REG_MI_MBK1_WA0_E_SHIFT) | \ 2354 ((u32)(wa0_of) << REG_MI_MBK1_WA0_OF_SHIFT) | \ 2355 ((u32)(wa0_m) << REG_MI_MBK1_WA0_M_SHIFT)) 2356 #endif 2357 2358 2359 /* MBK_A0 */ 2360 2361 #define REG_MI_MBK_A0_E_SHIFT 7 2362 #define REG_MI_MBK_A0_E_SIZE 1 2363 #define REG_MI_MBK_A0_E_MASK 0x80 2364 2365 #define REG_MI_MBK_A0_OF_SHIFT 2 2366 #define REG_MI_MBK_A0_OF_SIZE 2 2367 #define REG_MI_MBK_A0_OF_MASK 0x0c 2368 2369 #define REG_MI_MBK_A0_M_SHIFT 0 2370 #define REG_MI_MBK_A0_M_SIZE 1 2371 #define REG_MI_MBK_A0_M_MASK 0x01 2372 2373 #ifndef SDK_ASM 2374 #define REG_MI_MBK_A0_FIELD( e, of, m ) \ 2375 (u8)( \ 2376 ((u32)(e) << REG_MI_MBK_A0_E_SHIFT) | \ 2377 ((u32)(of) << REG_MI_MBK_A0_OF_SHIFT) | \ 2378 ((u32)(m) << REG_MI_MBK_A0_M_SHIFT)) 2379 #endif 2380 2381 2382 /* MBK_A1 */ 2383 2384 #define REG_MI_MBK_A1_E_SHIFT 7 2385 #define REG_MI_MBK_A1_E_SIZE 1 2386 #define REG_MI_MBK_A1_E_MASK 0x80 2387 2388 #define REG_MI_MBK_A1_OF_SHIFT 2 2389 #define REG_MI_MBK_A1_OF_SIZE 2 2390 #define REG_MI_MBK_A1_OF_MASK 0x0c 2391 2392 #define REG_MI_MBK_A1_M_SHIFT 0 2393 #define REG_MI_MBK_A1_M_SIZE 1 2394 #define REG_MI_MBK_A1_M_MASK 0x01 2395 2396 #ifndef SDK_ASM 2397 #define REG_MI_MBK_A1_FIELD( e, of, m ) \ 2398 (u8)( \ 2399 ((u32)(e) << REG_MI_MBK_A1_E_SHIFT) | \ 2400 ((u32)(of) << REG_MI_MBK_A1_OF_SHIFT) | \ 2401 ((u32)(m) << REG_MI_MBK_A1_M_SHIFT)) 2402 #endif 2403 2404 2405 /* MBK_A2 */ 2406 2407 #define REG_MI_MBK_A2_E_SHIFT 7 2408 #define REG_MI_MBK_A2_E_SIZE 1 2409 #define REG_MI_MBK_A2_E_MASK 0x80 2410 2411 #define REG_MI_MBK_A2_OF_SHIFT 2 2412 #define REG_MI_MBK_A2_OF_SIZE 2 2413 #define REG_MI_MBK_A2_OF_MASK 0x0c 2414 2415 #define REG_MI_MBK_A2_M_SHIFT 0 2416 #define REG_MI_MBK_A2_M_SIZE 1 2417 #define REG_MI_MBK_A2_M_MASK 0x01 2418 2419 #ifndef SDK_ASM 2420 #define REG_MI_MBK_A2_FIELD( e, of, m ) \ 2421 (u8)( \ 2422 ((u32)(e) << REG_MI_MBK_A2_E_SHIFT) | \ 2423 ((u32)(of) << REG_MI_MBK_A2_OF_SHIFT) | \ 2424 ((u32)(m) << REG_MI_MBK_A2_M_SHIFT)) 2425 #endif 2426 2427 2428 /* MBK_A3 */ 2429 2430 #define REG_MI_MBK_A3_E_SHIFT 7 2431 #define REG_MI_MBK_A3_E_SIZE 1 2432 #define REG_MI_MBK_A3_E_MASK 0x80 2433 2434 #define REG_MI_MBK_A3_OF_SHIFT 2 2435 #define REG_MI_MBK_A3_OF_SIZE 2 2436 #define REG_MI_MBK_A3_OF_MASK 0x0c 2437 2438 #define REG_MI_MBK_A3_M_SHIFT 0 2439 #define REG_MI_MBK_A3_M_SIZE 1 2440 #define REG_MI_MBK_A3_M_MASK 0x01 2441 2442 #ifndef SDK_ASM 2443 #define REG_MI_MBK_A3_FIELD( e, of, m ) \ 2444 (u8)( \ 2445 ((u32)(e) << REG_MI_MBK_A3_E_SHIFT) | \ 2446 ((u32)(of) << REG_MI_MBK_A3_OF_SHIFT) | \ 2447 ((u32)(m) << REG_MI_MBK_A3_M_SHIFT)) 2448 #endif 2449 2450 2451 /* MBK2 */ 2452 2453 #define REG_MI_MBK2_WB3_E_SHIFT 31 2454 #define REG_MI_MBK2_WB3_E_SIZE 1 2455 #define REG_MI_MBK2_WB3_E_MASK 0x80000000 2456 2457 #define REG_MI_MBK2_WB3_OF_SHIFT 28 2458 #define REG_MI_MBK2_WB3_OF_SIZE 3 2459 #define REG_MI_MBK2_WB3_OF_MASK 0x70000000 2460 2461 #define REG_MI_MBK2_WB3_M_SHIFT 24 2462 #define REG_MI_MBK2_WB3_M_SIZE 2 2463 #define REG_MI_MBK2_WB3_M_MASK 0x03000000 2464 2465 #define REG_MI_MBK2_WB2_E_SHIFT 23 2466 #define REG_MI_MBK2_WB2_E_SIZE 1 2467 #define REG_MI_MBK2_WB2_E_MASK 0x00800000 2468 2469 #define REG_MI_MBK2_WB2_OF_SHIFT 18 2470 #define REG_MI_MBK2_WB2_OF_SIZE 3 2471 #define REG_MI_MBK2_WB2_OF_MASK 0x001c0000 2472 2473 #define REG_MI_MBK2_WB2_M_SHIFT 16 2474 #define REG_MI_MBK2_WB2_M_SIZE 2 2475 #define REG_MI_MBK2_WB2_M_MASK 0x00030000 2476 2477 #define REG_MI_MBK2_WB1_E_SHIFT 15 2478 #define REG_MI_MBK2_WB1_E_SIZE 1 2479 #define REG_MI_MBK2_WB1_E_MASK 0x00008000 2480 2481 #define REG_MI_MBK2_WB1_OF_SHIFT 10 2482 #define REG_MI_MBK2_WB1_OF_SIZE 3 2483 #define REG_MI_MBK2_WB1_OF_MASK 0x00001c00 2484 2485 #define REG_MI_MBK2_WB1_M_SHIFT 8 2486 #define REG_MI_MBK2_WB1_M_SIZE 2 2487 #define REG_MI_MBK2_WB1_M_MASK 0x00000300 2488 2489 #define REG_MI_MBK2_WB0_E_SHIFT 7 2490 #define REG_MI_MBK2_WB0_E_SIZE 1 2491 #define REG_MI_MBK2_WB0_E_MASK 0x00000080 2492 2493 #define REG_MI_MBK2_WB0_OF_SHIFT 2 2494 #define REG_MI_MBK2_WB0_OF_SIZE 3 2495 #define REG_MI_MBK2_WB0_OF_MASK 0x0000001c 2496 2497 #define REG_MI_MBK2_WB0_M_SHIFT 0 2498 #define REG_MI_MBK2_WB0_M_SIZE 2 2499 #define REG_MI_MBK2_WB0_M_MASK 0x00000003 2500 2501 #ifndef SDK_ASM 2502 #define REG_MI_MBK2_FIELD( wb3_e, wb3_of, wb3_m, wb2_e, wb2_of, wb2_m, wb1_e, wb1_of, wb1_m, wb0_e, wb0_of, wb0_m ) \ 2503 (u32)( \ 2504 ((u32)(wb3_e) << REG_MI_MBK2_WB3_E_SHIFT) | \ 2505 ((u32)(wb3_of) << REG_MI_MBK2_WB3_OF_SHIFT) | \ 2506 ((u32)(wb3_m) << REG_MI_MBK2_WB3_M_SHIFT) | \ 2507 ((u32)(wb2_e) << REG_MI_MBK2_WB2_E_SHIFT) | \ 2508 ((u32)(wb2_of) << REG_MI_MBK2_WB2_OF_SHIFT) | \ 2509 ((u32)(wb2_m) << REG_MI_MBK2_WB2_M_SHIFT) | \ 2510 ((u32)(wb1_e) << REG_MI_MBK2_WB1_E_SHIFT) | \ 2511 ((u32)(wb1_of) << REG_MI_MBK2_WB1_OF_SHIFT) | \ 2512 ((u32)(wb1_m) << REG_MI_MBK2_WB1_M_SHIFT) | \ 2513 ((u32)(wb0_e) << REG_MI_MBK2_WB0_E_SHIFT) | \ 2514 ((u32)(wb0_of) << REG_MI_MBK2_WB0_OF_SHIFT) | \ 2515 ((u32)(wb0_m) << REG_MI_MBK2_WB0_M_SHIFT)) 2516 #endif 2517 2518 2519 /* MBK_B0 */ 2520 2521 #define REG_MI_MBK_B0_E_SHIFT 7 2522 #define REG_MI_MBK_B0_E_SIZE 1 2523 #define REG_MI_MBK_B0_E_MASK 0x80 2524 2525 #define REG_MI_MBK_B0_OF_SHIFT 2 2526 #define REG_MI_MBK_B0_OF_SIZE 3 2527 #define REG_MI_MBK_B0_OF_MASK 0x1c 2528 2529 #define REG_MI_MBK_B0_M_SHIFT 0 2530 #define REG_MI_MBK_B0_M_SIZE 2 2531 #define REG_MI_MBK_B0_M_MASK 0x03 2532 2533 #ifndef SDK_ASM 2534 #define REG_MI_MBK_B0_FIELD( e, of, m ) \ 2535 (u8)( \ 2536 ((u32)(e) << REG_MI_MBK_B0_E_SHIFT) | \ 2537 ((u32)(of) << REG_MI_MBK_B0_OF_SHIFT) | \ 2538 ((u32)(m) << REG_MI_MBK_B0_M_SHIFT)) 2539 #endif 2540 2541 2542 /* MBK_B1 */ 2543 2544 #define REG_MI_MBK_B1_E_SHIFT 7 2545 #define REG_MI_MBK_B1_E_SIZE 1 2546 #define REG_MI_MBK_B1_E_MASK 0x80 2547 2548 #define REG_MI_MBK_B1_OF_SHIFT 2 2549 #define REG_MI_MBK_B1_OF_SIZE 3 2550 #define REG_MI_MBK_B1_OF_MASK 0x1c 2551 2552 #define REG_MI_MBK_B1_M_SHIFT 0 2553 #define REG_MI_MBK_B1_M_SIZE 2 2554 #define REG_MI_MBK_B1_M_MASK 0x03 2555 2556 #ifndef SDK_ASM 2557 #define REG_MI_MBK_B1_FIELD( e, of, m ) \ 2558 (u8)( \ 2559 ((u32)(e) << REG_MI_MBK_B1_E_SHIFT) | \ 2560 ((u32)(of) << REG_MI_MBK_B1_OF_SHIFT) | \ 2561 ((u32)(m) << REG_MI_MBK_B1_M_SHIFT)) 2562 #endif 2563 2564 2565 /* MBK_B2 */ 2566 2567 #define REG_MI_MBK_B2_E_SHIFT 7 2568 #define REG_MI_MBK_B2_E_SIZE 1 2569 #define REG_MI_MBK_B2_E_MASK 0x80 2570 2571 #define REG_MI_MBK_B2_OF_SHIFT 2 2572 #define REG_MI_MBK_B2_OF_SIZE 3 2573 #define REG_MI_MBK_B2_OF_MASK 0x1c 2574 2575 #define REG_MI_MBK_B2_M_SHIFT 0 2576 #define REG_MI_MBK_B2_M_SIZE 2 2577 #define REG_MI_MBK_B2_M_MASK 0x03 2578 2579 #ifndef SDK_ASM 2580 #define REG_MI_MBK_B2_FIELD( e, of, m ) \ 2581 (u8)( \ 2582 ((u32)(e) << REG_MI_MBK_B2_E_SHIFT) | \ 2583 ((u32)(of) << REG_MI_MBK_B2_OF_SHIFT) | \ 2584 ((u32)(m) << REG_MI_MBK_B2_M_SHIFT)) 2585 #endif 2586 2587 2588 /* MBK_B3 */ 2589 2590 #define REG_MI_MBK_B3_E_SHIFT 7 2591 #define REG_MI_MBK_B3_E_SIZE 1 2592 #define REG_MI_MBK_B3_E_MASK 0x80 2593 2594 #define REG_MI_MBK_B3_OF_SHIFT 2 2595 #define REG_MI_MBK_B3_OF_SIZE 3 2596 #define REG_MI_MBK_B3_OF_MASK 0x1c 2597 2598 #define REG_MI_MBK_B3_M_SHIFT 0 2599 #define REG_MI_MBK_B3_M_SIZE 2 2600 #define REG_MI_MBK_B3_M_MASK 0x03 2601 2602 #ifndef SDK_ASM 2603 #define REG_MI_MBK_B3_FIELD( e, of, m ) \ 2604 (u8)( \ 2605 ((u32)(e) << REG_MI_MBK_B3_E_SHIFT) | \ 2606 ((u32)(of) << REG_MI_MBK_B3_OF_SHIFT) | \ 2607 ((u32)(m) << REG_MI_MBK_B3_M_SHIFT)) 2608 #endif 2609 2610 2611 /* MBK3 */ 2612 2613 #define REG_MI_MBK3_WB7_E_SHIFT 31 2614 #define REG_MI_MBK3_WB7_E_SIZE 1 2615 #define REG_MI_MBK3_WB7_E_MASK 0x80000000 2616 2617 #define REG_MI_MBK3_WB7_OF_SHIFT 28 2618 #define REG_MI_MBK3_WB7_OF_SIZE 3 2619 #define REG_MI_MBK3_WB7_OF_MASK 0x70000000 2620 2621 #define REG_MI_MBK3_WB7_M_SHIFT 24 2622 #define REG_MI_MBK3_WB7_M_SIZE 2 2623 #define REG_MI_MBK3_WB7_M_MASK 0x03000000 2624 2625 #define REG_MI_MBK3_WB6_E_SHIFT 23 2626 #define REG_MI_MBK3_WB6_E_SIZE 1 2627 #define REG_MI_MBK3_WB6_E_MASK 0x00800000 2628 2629 #define REG_MI_MBK3_WB6_OF_SHIFT 18 2630 #define REG_MI_MBK3_WB6_OF_SIZE 3 2631 #define REG_MI_MBK3_WB6_OF_MASK 0x001c0000 2632 2633 #define REG_MI_MBK3_WB6_M_SHIFT 16 2634 #define REG_MI_MBK3_WB6_M_SIZE 2 2635 #define REG_MI_MBK3_WB6_M_MASK 0x00030000 2636 2637 #define REG_MI_MBK3_WB5_E_SHIFT 15 2638 #define REG_MI_MBK3_WB5_E_SIZE 1 2639 #define REG_MI_MBK3_WB5_E_MASK 0x00008000 2640 2641 #define REG_MI_MBK3_WB5_OF_SHIFT 10 2642 #define REG_MI_MBK3_WB5_OF_SIZE 3 2643 #define REG_MI_MBK3_WB5_OF_MASK 0x00001c00 2644 2645 #define REG_MI_MBK3_WB5_M_SHIFT 8 2646 #define REG_MI_MBK3_WB5_M_SIZE 2 2647 #define REG_MI_MBK3_WB5_M_MASK 0x00000300 2648 2649 #define REG_MI_MBK3_WB4_E_SHIFT 7 2650 #define REG_MI_MBK3_WB4_E_SIZE 1 2651 #define REG_MI_MBK3_WB4_E_MASK 0x00000080 2652 2653 #define REG_MI_MBK3_WB4_OF_SHIFT 2 2654 #define REG_MI_MBK3_WB4_OF_SIZE 3 2655 #define REG_MI_MBK3_WB4_OF_MASK 0x0000001c 2656 2657 #define REG_MI_MBK3_WB4_M_SHIFT 0 2658 #define REG_MI_MBK3_WB4_M_SIZE 2 2659 #define REG_MI_MBK3_WB4_M_MASK 0x00000003 2660 2661 #ifndef SDK_ASM 2662 #define REG_MI_MBK3_FIELD( wb7_e, wb7_of, wb7_m, wb6_e, wb6_of, wb6_m, wb5_e, wb5_of, wb5_m, wb4_e, wb4_of, wb4_m ) \ 2663 (u32)( \ 2664 ((u32)(wb7_e) << REG_MI_MBK3_WB7_E_SHIFT) | \ 2665 ((u32)(wb7_of) << REG_MI_MBK3_WB7_OF_SHIFT) | \ 2666 ((u32)(wb7_m) << REG_MI_MBK3_WB7_M_SHIFT) | \ 2667 ((u32)(wb6_e) << REG_MI_MBK3_WB6_E_SHIFT) | \ 2668 ((u32)(wb6_of) << REG_MI_MBK3_WB6_OF_SHIFT) | \ 2669 ((u32)(wb6_m) << REG_MI_MBK3_WB6_M_SHIFT) | \ 2670 ((u32)(wb5_e) << REG_MI_MBK3_WB5_E_SHIFT) | \ 2671 ((u32)(wb5_of) << REG_MI_MBK3_WB5_OF_SHIFT) | \ 2672 ((u32)(wb5_m) << REG_MI_MBK3_WB5_M_SHIFT) | \ 2673 ((u32)(wb4_e) << REG_MI_MBK3_WB4_E_SHIFT) | \ 2674 ((u32)(wb4_of) << REG_MI_MBK3_WB4_OF_SHIFT) | \ 2675 ((u32)(wb4_m) << REG_MI_MBK3_WB4_M_SHIFT)) 2676 #endif 2677 2678 2679 /* MBK_B4 */ 2680 2681 #define REG_MI_MBK_B4_E_SHIFT 7 2682 #define REG_MI_MBK_B4_E_SIZE 1 2683 #define REG_MI_MBK_B4_E_MASK 0x80 2684 2685 #define REG_MI_MBK_B4_OF_SHIFT 2 2686 #define REG_MI_MBK_B4_OF_SIZE 3 2687 #define REG_MI_MBK_B4_OF_MASK 0x1c 2688 2689 #define REG_MI_MBK_B4_M_SHIFT 0 2690 #define REG_MI_MBK_B4_M_SIZE 2 2691 #define REG_MI_MBK_B4_M_MASK 0x03 2692 2693 #ifndef SDK_ASM 2694 #define REG_MI_MBK_B4_FIELD( e, of, m ) \ 2695 (u8)( \ 2696 ((u32)(e) << REG_MI_MBK_B4_E_SHIFT) | \ 2697 ((u32)(of) << REG_MI_MBK_B4_OF_SHIFT) | \ 2698 ((u32)(m) << REG_MI_MBK_B4_M_SHIFT)) 2699 #endif 2700 2701 2702 /* MBK_B5 */ 2703 2704 #define REG_MI_MBK_B5_E_SHIFT 7 2705 #define REG_MI_MBK_B5_E_SIZE 1 2706 #define REG_MI_MBK_B5_E_MASK 0x80 2707 2708 #define REG_MI_MBK_B5_OF_SHIFT 2 2709 #define REG_MI_MBK_B5_OF_SIZE 3 2710 #define REG_MI_MBK_B5_OF_MASK 0x1c 2711 2712 #define REG_MI_MBK_B5_M_SHIFT 0 2713 #define REG_MI_MBK_B5_M_SIZE 2 2714 #define REG_MI_MBK_B5_M_MASK 0x03 2715 2716 #ifndef SDK_ASM 2717 #define REG_MI_MBK_B5_FIELD( e, of, m ) \ 2718 (u8)( \ 2719 ((u32)(e) << REG_MI_MBK_B5_E_SHIFT) | \ 2720 ((u32)(of) << REG_MI_MBK_B5_OF_SHIFT) | \ 2721 ((u32)(m) << REG_MI_MBK_B5_M_SHIFT)) 2722 #endif 2723 2724 2725 /* MBK_B6 */ 2726 2727 #define REG_MI_MBK_B6_E_SHIFT 7 2728 #define REG_MI_MBK_B6_E_SIZE 1 2729 #define REG_MI_MBK_B6_E_MASK 0x80 2730 2731 #define REG_MI_MBK_B6_OF_SHIFT 2 2732 #define REG_MI_MBK_B6_OF_SIZE 3 2733 #define REG_MI_MBK_B6_OF_MASK 0x1c 2734 2735 #define REG_MI_MBK_B6_M_SHIFT 0 2736 #define REG_MI_MBK_B6_M_SIZE 2 2737 #define REG_MI_MBK_B6_M_MASK 0x03 2738 2739 #ifndef SDK_ASM 2740 #define REG_MI_MBK_B6_FIELD( e, of, m ) \ 2741 (u8)( \ 2742 ((u32)(e) << REG_MI_MBK_B6_E_SHIFT) | \ 2743 ((u32)(of) << REG_MI_MBK_B6_OF_SHIFT) | \ 2744 ((u32)(m) << REG_MI_MBK_B6_M_SHIFT)) 2745 #endif 2746 2747 2748 /* MBK_B7 */ 2749 2750 #define REG_MI_MBK_B7_E_SHIFT 7 2751 #define REG_MI_MBK_B7_E_SIZE 1 2752 #define REG_MI_MBK_B7_E_MASK 0x80 2753 2754 #define REG_MI_MBK_B7_OF_SHIFT 2 2755 #define REG_MI_MBK_B7_OF_SIZE 3 2756 #define REG_MI_MBK_B7_OF_MASK 0x1c 2757 2758 #define REG_MI_MBK_B7_M_SHIFT 0 2759 #define REG_MI_MBK_B7_M_SIZE 2 2760 #define REG_MI_MBK_B7_M_MASK 0x03 2761 2762 #ifndef SDK_ASM 2763 #define REG_MI_MBK_B7_FIELD( e, of, m ) \ 2764 (u8)( \ 2765 ((u32)(e) << REG_MI_MBK_B7_E_SHIFT) | \ 2766 ((u32)(of) << REG_MI_MBK_B7_OF_SHIFT) | \ 2767 ((u32)(m) << REG_MI_MBK_B7_M_SHIFT)) 2768 #endif 2769 2770 2771 /* MBK4 */ 2772 2773 #define REG_MI_MBK4_WC3_E_SHIFT 31 2774 #define REG_MI_MBK4_WC3_E_SIZE 1 2775 #define REG_MI_MBK4_WC3_E_MASK 0x80000000 2776 2777 #define REG_MI_MBK4_WC3_OF_SHIFT 28 2778 #define REG_MI_MBK4_WC3_OF_SIZE 3 2779 #define REG_MI_MBK4_WC3_OF_MASK 0x70000000 2780 2781 #define REG_MI_MBK4_WC3_M_SHIFT 24 2782 #define REG_MI_MBK4_WC3_M_SIZE 2 2783 #define REG_MI_MBK4_WC3_M_MASK 0x03000000 2784 2785 #define REG_MI_MBK4_WC2_E_SHIFT 23 2786 #define REG_MI_MBK4_WC2_E_SIZE 1 2787 #define REG_MI_MBK4_WC2_E_MASK 0x00800000 2788 2789 #define REG_MI_MBK4_WC2_OF_SHIFT 18 2790 #define REG_MI_MBK4_WC2_OF_SIZE 3 2791 #define REG_MI_MBK4_WC2_OF_MASK 0x001c0000 2792 2793 #define REG_MI_MBK4_WC2_M_SHIFT 16 2794 #define REG_MI_MBK4_WC2_M_SIZE 2 2795 #define REG_MI_MBK4_WC2_M_MASK 0x00030000 2796 2797 #define REG_MI_MBK4_WC1_E_SHIFT 15 2798 #define REG_MI_MBK4_WC1_E_SIZE 1 2799 #define REG_MI_MBK4_WC1_E_MASK 0x00008000 2800 2801 #define REG_MI_MBK4_WC1_OF_SHIFT 10 2802 #define REG_MI_MBK4_WC1_OF_SIZE 3 2803 #define REG_MI_MBK4_WC1_OF_MASK 0x00001c00 2804 2805 #define REG_MI_MBK4_WC1_M_SHIFT 8 2806 #define REG_MI_MBK4_WC1_M_SIZE 2 2807 #define REG_MI_MBK4_WC1_M_MASK 0x00000300 2808 2809 #define REG_MI_MBK4_WC0_E_SHIFT 7 2810 #define REG_MI_MBK4_WC0_E_SIZE 1 2811 #define REG_MI_MBK4_WC0_E_MASK 0x00000080 2812 2813 #define REG_MI_MBK4_WC0_OF_SHIFT 2 2814 #define REG_MI_MBK4_WC0_OF_SIZE 3 2815 #define REG_MI_MBK4_WC0_OF_MASK 0x0000001c 2816 2817 #define REG_MI_MBK4_WC0_M_SHIFT 0 2818 #define REG_MI_MBK4_WC0_M_SIZE 2 2819 #define REG_MI_MBK4_WC0_M_MASK 0x00000003 2820 2821 #ifndef SDK_ASM 2822 #define REG_MI_MBK4_FIELD( wc3_e, wc3_of, wc3_m, wc2_e, wc2_of, wc2_m, wc1_e, wc1_of, wc1_m, wc0_e, wc0_of, wc0_m ) \ 2823 (u32)( \ 2824 ((u32)(wc3_e) << REG_MI_MBK4_WC3_E_SHIFT) | \ 2825 ((u32)(wc3_of) << REG_MI_MBK4_WC3_OF_SHIFT) | \ 2826 ((u32)(wc3_m) << REG_MI_MBK4_WC3_M_SHIFT) | \ 2827 ((u32)(wc2_e) << REG_MI_MBK4_WC2_E_SHIFT) | \ 2828 ((u32)(wc2_of) << REG_MI_MBK4_WC2_OF_SHIFT) | \ 2829 ((u32)(wc2_m) << REG_MI_MBK4_WC2_M_SHIFT) | \ 2830 ((u32)(wc1_e) << REG_MI_MBK4_WC1_E_SHIFT) | \ 2831 ((u32)(wc1_of) << REG_MI_MBK4_WC1_OF_SHIFT) | \ 2832 ((u32)(wc1_m) << REG_MI_MBK4_WC1_M_SHIFT) | \ 2833 ((u32)(wc0_e) << REG_MI_MBK4_WC0_E_SHIFT) | \ 2834 ((u32)(wc0_of) << REG_MI_MBK4_WC0_OF_SHIFT) | \ 2835 ((u32)(wc0_m) << REG_MI_MBK4_WC0_M_SHIFT)) 2836 #endif 2837 2838 2839 /* MBK_C0 */ 2840 2841 #define REG_MI_MBK_C0_E_SHIFT 7 2842 #define REG_MI_MBK_C0_E_SIZE 1 2843 #define REG_MI_MBK_C0_E_MASK 0x80 2844 2845 #define REG_MI_MBK_C0_OF_SHIFT 2 2846 #define REG_MI_MBK_C0_OF_SIZE 3 2847 #define REG_MI_MBK_C0_OF_MASK 0x1c 2848 2849 #define REG_MI_MBK_C0_M_SHIFT 0 2850 #define REG_MI_MBK_C0_M_SIZE 2 2851 #define REG_MI_MBK_C0_M_MASK 0x03 2852 2853 #ifndef SDK_ASM 2854 #define REG_MI_MBK_C0_FIELD( e, of, m ) \ 2855 (u8)( \ 2856 ((u32)(e) << REG_MI_MBK_C0_E_SHIFT) | \ 2857 ((u32)(of) << REG_MI_MBK_C0_OF_SHIFT) | \ 2858 ((u32)(m) << REG_MI_MBK_C0_M_SHIFT)) 2859 #endif 2860 2861 2862 /* MBK_C1 */ 2863 2864 #define REG_MI_MBK_C1_E_SHIFT 7 2865 #define REG_MI_MBK_C1_E_SIZE 1 2866 #define REG_MI_MBK_C1_E_MASK 0x80 2867 2868 #define REG_MI_MBK_C1_OF_SHIFT 2 2869 #define REG_MI_MBK_C1_OF_SIZE 3 2870 #define REG_MI_MBK_C1_OF_MASK 0x1c 2871 2872 #define REG_MI_MBK_C1_M_SHIFT 0 2873 #define REG_MI_MBK_C1_M_SIZE 2 2874 #define REG_MI_MBK_C1_M_MASK 0x03 2875 2876 #ifndef SDK_ASM 2877 #define REG_MI_MBK_C1_FIELD( e, of, m ) \ 2878 (u8)( \ 2879 ((u32)(e) << REG_MI_MBK_C1_E_SHIFT) | \ 2880 ((u32)(of) << REG_MI_MBK_C1_OF_SHIFT) | \ 2881 ((u32)(m) << REG_MI_MBK_C1_M_SHIFT)) 2882 #endif 2883 2884 2885 /* MBK_C2 */ 2886 2887 #define REG_MI_MBK_C2_E_SHIFT 7 2888 #define REG_MI_MBK_C2_E_SIZE 1 2889 #define REG_MI_MBK_C2_E_MASK 0x80 2890 2891 #define REG_MI_MBK_C2_OF_SHIFT 2 2892 #define REG_MI_MBK_C2_OF_SIZE 3 2893 #define REG_MI_MBK_C2_OF_MASK 0x1c 2894 2895 #define REG_MI_MBK_C2_M_SHIFT 0 2896 #define REG_MI_MBK_C2_M_SIZE 2 2897 #define REG_MI_MBK_C2_M_MASK 0x03 2898 2899 #ifndef SDK_ASM 2900 #define REG_MI_MBK_C2_FIELD( e, of, m ) \ 2901 (u8)( \ 2902 ((u32)(e) << REG_MI_MBK_C2_E_SHIFT) | \ 2903 ((u32)(of) << REG_MI_MBK_C2_OF_SHIFT) | \ 2904 ((u32)(m) << REG_MI_MBK_C2_M_SHIFT)) 2905 #endif 2906 2907 2908 /* MBK_C3 */ 2909 2910 #define REG_MI_MBK_C3_E_SHIFT 7 2911 #define REG_MI_MBK_C3_E_SIZE 1 2912 #define REG_MI_MBK_C3_E_MASK 0x80 2913 2914 #define REG_MI_MBK_C3_OF_SHIFT 2 2915 #define REG_MI_MBK_C3_OF_SIZE 3 2916 #define REG_MI_MBK_C3_OF_MASK 0x1c 2917 2918 #define REG_MI_MBK_C3_M_SHIFT 0 2919 #define REG_MI_MBK_C3_M_SIZE 2 2920 #define REG_MI_MBK_C3_M_MASK 0x03 2921 2922 #ifndef SDK_ASM 2923 #define REG_MI_MBK_C3_FIELD( e, of, m ) \ 2924 (u8)( \ 2925 ((u32)(e) << REG_MI_MBK_C3_E_SHIFT) | \ 2926 ((u32)(of) << REG_MI_MBK_C3_OF_SHIFT) | \ 2927 ((u32)(m) << REG_MI_MBK_C3_M_SHIFT)) 2928 #endif 2929 2930 2931 /* MBK5 */ 2932 2933 #define REG_MI_MBK5_WC7_E_SHIFT 31 2934 #define REG_MI_MBK5_WC7_E_SIZE 1 2935 #define REG_MI_MBK5_WC7_E_MASK 0x80000000 2936 2937 #define REG_MI_MBK5_WC7_OF_SHIFT 28 2938 #define REG_MI_MBK5_WC7_OF_SIZE 3 2939 #define REG_MI_MBK5_WC7_OF_MASK 0x70000000 2940 2941 #define REG_MI_MBK5_WC7_M_SHIFT 24 2942 #define REG_MI_MBK5_WC7_M_SIZE 2 2943 #define REG_MI_MBK5_WC7_M_MASK 0x03000000 2944 2945 #define REG_MI_MBK5_WC6_E_SHIFT 23 2946 #define REG_MI_MBK5_WC6_E_SIZE 1 2947 #define REG_MI_MBK5_WC6_E_MASK 0x00800000 2948 2949 #define REG_MI_MBK5_WC6_OF_SHIFT 18 2950 #define REG_MI_MBK5_WC6_OF_SIZE 3 2951 #define REG_MI_MBK5_WC6_OF_MASK 0x001c0000 2952 2953 #define REG_MI_MBK5_WC6_M_SHIFT 16 2954 #define REG_MI_MBK5_WC6_M_SIZE 2 2955 #define REG_MI_MBK5_WC6_M_MASK 0x00030000 2956 2957 #define REG_MI_MBK5_WC5_E_SHIFT 15 2958 #define REG_MI_MBK5_WC5_E_SIZE 1 2959 #define REG_MI_MBK5_WC5_E_MASK 0x00008000 2960 2961 #define REG_MI_MBK5_WC5_OF_SHIFT 10 2962 #define REG_MI_MBK5_WC5_OF_SIZE 3 2963 #define REG_MI_MBK5_WC5_OF_MASK 0x00001c00 2964 2965 #define REG_MI_MBK5_WC5_M_SHIFT 8 2966 #define REG_MI_MBK5_WC5_M_SIZE 2 2967 #define REG_MI_MBK5_WC5_M_MASK 0x00000300 2968 2969 #define REG_MI_MBK5_WC4_E_SHIFT 7 2970 #define REG_MI_MBK5_WC4_E_SIZE 1 2971 #define REG_MI_MBK5_WC4_E_MASK 0x00000080 2972 2973 #define REG_MI_MBK5_WC4_OF_SHIFT 2 2974 #define REG_MI_MBK5_WC4_OF_SIZE 3 2975 #define REG_MI_MBK5_WC4_OF_MASK 0x0000001c 2976 2977 #define REG_MI_MBK5_WC4_M_SHIFT 0 2978 #define REG_MI_MBK5_WC4_M_SIZE 2 2979 #define REG_MI_MBK5_WC4_M_MASK 0x00000003 2980 2981 #ifndef SDK_ASM 2982 #define REG_MI_MBK5_FIELD( wc7_e, wc7_of, wc7_m, wc6_e, wc6_of, wc6_m, wc5_e, wc5_of, wc5_m, wc4_e, wc4_of, wc4_m ) \ 2983 (u32)( \ 2984 ((u32)(wc7_e) << REG_MI_MBK5_WC7_E_SHIFT) | \ 2985 ((u32)(wc7_of) << REG_MI_MBK5_WC7_OF_SHIFT) | \ 2986 ((u32)(wc7_m) << REG_MI_MBK5_WC7_M_SHIFT) | \ 2987 ((u32)(wc6_e) << REG_MI_MBK5_WC6_E_SHIFT) | \ 2988 ((u32)(wc6_of) << REG_MI_MBK5_WC6_OF_SHIFT) | \ 2989 ((u32)(wc6_m) << REG_MI_MBK5_WC6_M_SHIFT) | \ 2990 ((u32)(wc5_e) << REG_MI_MBK5_WC5_E_SHIFT) | \ 2991 ((u32)(wc5_of) << REG_MI_MBK5_WC5_OF_SHIFT) | \ 2992 ((u32)(wc5_m) << REG_MI_MBK5_WC5_M_SHIFT) | \ 2993 ((u32)(wc4_e) << REG_MI_MBK5_WC4_E_SHIFT) | \ 2994 ((u32)(wc4_of) << REG_MI_MBK5_WC4_OF_SHIFT) | \ 2995 ((u32)(wc4_m) << REG_MI_MBK5_WC4_M_SHIFT)) 2996 #endif 2997 2998 2999 /* MBK_C4 */ 3000 3001 #define REG_MI_MBK_C4_E_SHIFT 7 3002 #define REG_MI_MBK_C4_E_SIZE 1 3003 #define REG_MI_MBK_C4_E_MASK 0x80 3004 3005 #define REG_MI_MBK_C4_OF_SHIFT 2 3006 #define REG_MI_MBK_C4_OF_SIZE 3 3007 #define REG_MI_MBK_C4_OF_MASK 0x1c 3008 3009 #define REG_MI_MBK_C4_M_SHIFT 0 3010 #define REG_MI_MBK_C4_M_SIZE 2 3011 #define REG_MI_MBK_C4_M_MASK 0x03 3012 3013 #ifndef SDK_ASM 3014 #define REG_MI_MBK_C4_FIELD( e, of, m ) \ 3015 (u8)( \ 3016 ((u32)(e) << REG_MI_MBK_C4_E_SHIFT) | \ 3017 ((u32)(of) << REG_MI_MBK_C4_OF_SHIFT) | \ 3018 ((u32)(m) << REG_MI_MBK_C4_M_SHIFT)) 3019 #endif 3020 3021 3022 /* MBK_C5 */ 3023 3024 #define REG_MI_MBK_C5_E_SHIFT 7 3025 #define REG_MI_MBK_C5_E_SIZE 1 3026 #define REG_MI_MBK_C5_E_MASK 0x80 3027 3028 #define REG_MI_MBK_C5_OF_SHIFT 2 3029 #define REG_MI_MBK_C5_OF_SIZE 3 3030 #define REG_MI_MBK_C5_OF_MASK 0x1c 3031 3032 #define REG_MI_MBK_C5_M_SHIFT 0 3033 #define REG_MI_MBK_C5_M_SIZE 2 3034 #define REG_MI_MBK_C5_M_MASK 0x03 3035 3036 #ifndef SDK_ASM 3037 #define REG_MI_MBK_C5_FIELD( e, of, m ) \ 3038 (u8)( \ 3039 ((u32)(e) << REG_MI_MBK_C5_E_SHIFT) | \ 3040 ((u32)(of) << REG_MI_MBK_C5_OF_SHIFT) | \ 3041 ((u32)(m) << REG_MI_MBK_C5_M_SHIFT)) 3042 #endif 3043 3044 3045 /* MBK_C6 */ 3046 3047 #define REG_MI_MBK_C6_E_SHIFT 7 3048 #define REG_MI_MBK_C6_E_SIZE 1 3049 #define REG_MI_MBK_C6_E_MASK 0x80 3050 3051 #define REG_MI_MBK_C6_OF_SHIFT 2 3052 #define REG_MI_MBK_C6_OF_SIZE 3 3053 #define REG_MI_MBK_C6_OF_MASK 0x1c 3054 3055 #define REG_MI_MBK_C6_M_SHIFT 0 3056 #define REG_MI_MBK_C6_M_SIZE 2 3057 #define REG_MI_MBK_C6_M_MASK 0x03 3058 3059 #ifndef SDK_ASM 3060 #define REG_MI_MBK_C6_FIELD( e, of, m ) \ 3061 (u8)( \ 3062 ((u32)(e) << REG_MI_MBK_C6_E_SHIFT) | \ 3063 ((u32)(of) << REG_MI_MBK_C6_OF_SHIFT) | \ 3064 ((u32)(m) << REG_MI_MBK_C6_M_SHIFT)) 3065 #endif 3066 3067 3068 /* MBK_C7 */ 3069 3070 #define REG_MI_MBK_C7_E_SHIFT 7 3071 #define REG_MI_MBK_C7_E_SIZE 1 3072 #define REG_MI_MBK_C7_E_MASK 0x80 3073 3074 #define REG_MI_MBK_C7_OF_SHIFT 2 3075 #define REG_MI_MBK_C7_OF_SIZE 3 3076 #define REG_MI_MBK_C7_OF_MASK 0x1c 3077 3078 #define REG_MI_MBK_C7_M_SHIFT 0 3079 #define REG_MI_MBK_C7_M_SIZE 2 3080 #define REG_MI_MBK_C7_M_MASK 0x03 3081 3082 #ifndef SDK_ASM 3083 #define REG_MI_MBK_C7_FIELD( e, of, m ) \ 3084 (u8)( \ 3085 ((u32)(e) << REG_MI_MBK_C7_E_SHIFT) | \ 3086 ((u32)(of) << REG_MI_MBK_C7_OF_SHIFT) | \ 3087 ((u32)(m) << REG_MI_MBK_C7_M_SHIFT)) 3088 #endif 3089 3090 3091 /* MBK6 */ 3092 3093 #define REG_MI_MBK6_WA_EADDR_SHIFT 20 3094 #define REG_MI_MBK6_WA_EADDR_SIZE 9 3095 #define REG_MI_MBK6_WA_EADDR_MASK 0x1ff00000 3096 3097 #define REG_MI_MBK6_WA_ISIZE_SHIFT 12 3098 #define REG_MI_MBK6_WA_ISIZE_SIZE 2 3099 #define REG_MI_MBK6_WA_ISIZE_MASK 0x00003000 3100 3101 #define REG_MI_MBK6_WA_SADDR_SHIFT 4 3102 #define REG_MI_MBK6_WA_SADDR_SIZE 8 3103 #define REG_MI_MBK6_WA_SADDR_MASK 0x00000ff0 3104 3105 #ifndef SDK_ASM 3106 #define REG_MI_MBK6_FIELD( wa_eaddr, wa_isize, wa_saddr ) \ 3107 (u32)( \ 3108 ((u32)(wa_eaddr) << REG_MI_MBK6_WA_EADDR_SHIFT) | \ 3109 ((u32)(wa_isize) << REG_MI_MBK6_WA_ISIZE_SHIFT) | \ 3110 ((u32)(wa_saddr) << REG_MI_MBK6_WA_SADDR_SHIFT)) 3111 #endif 3112 3113 3114 /* MBK7 */ 3115 3116 #define REG_MI_MBK7_WB_EADDR_SHIFT 19 3117 #define REG_MI_MBK7_WB_EADDR_SIZE 10 3118 #define REG_MI_MBK7_WB_EADDR_MASK 0x1ff80000 3119 3120 #define REG_MI_MBK7_WB_ISIZE_SHIFT 12 3121 #define REG_MI_MBK7_WB_ISIZE_SIZE 2 3122 #define REG_MI_MBK7_WB_ISIZE_MASK 0x00003000 3123 3124 #define REG_MI_MBK7_WB_SADDR_SHIFT 3 3125 #define REG_MI_MBK7_WB_SADDR_SIZE 9 3126 #define REG_MI_MBK7_WB_SADDR_MASK 0x00000ff8 3127 3128 #ifndef SDK_ASM 3129 #define REG_MI_MBK7_FIELD( wb_eaddr, wb_isize, wb_saddr ) \ 3130 (u32)( \ 3131 ((u32)(wb_eaddr) << REG_MI_MBK7_WB_EADDR_SHIFT) | \ 3132 ((u32)(wb_isize) << REG_MI_MBK7_WB_ISIZE_SHIFT) | \ 3133 ((u32)(wb_saddr) << REG_MI_MBK7_WB_SADDR_SHIFT)) 3134 #endif 3135 3136 3137 /* MBK8 */ 3138 3139 #define REG_MI_MBK8_WC_EADDR_SHIFT 19 3140 #define REG_MI_MBK8_WC_EADDR_SIZE 10 3141 #define REG_MI_MBK8_WC_EADDR_MASK 0x1ff80000 3142 3143 #define REG_MI_MBK8_WC_ISIZE_SHIFT 12 3144 #define REG_MI_MBK8_WC_ISIZE_SIZE 2 3145 #define REG_MI_MBK8_WC_ISIZE_MASK 0x00003000 3146 3147 #define REG_MI_MBK8_WC_SADDR_SHIFT 3 3148 #define REG_MI_MBK8_WC_SADDR_SIZE 9 3149 #define REG_MI_MBK8_WC_SADDR_MASK 0x00000ff8 3150 3151 #ifndef SDK_ASM 3152 #define REG_MI_MBK8_FIELD( wc_eaddr, wc_isize, wc_saddr ) \ 3153 (u32)( \ 3154 ((u32)(wc_eaddr) << REG_MI_MBK8_WC_EADDR_SHIFT) | \ 3155 ((u32)(wc_isize) << REG_MI_MBK8_WC_ISIZE_SHIFT) | \ 3156 ((u32)(wc_saddr) << REG_MI_MBK8_WC_SADDR_SHIFT)) 3157 #endif 3158 3159 3160 /* MBK9 */ 3161 3162 #define REG_MI_MBK9_WC_LOCKST_SHIFT 16 3163 #define REG_MI_MBK9_WC_LOCKST_SIZE 8 3164 #define REG_MI_MBK9_WC_LOCKST_MASK 0x00ff0000 3165 3166 #define REG_MI_MBK9_WB_LOCLST_SHIFT 8 3167 #define REG_MI_MBK9_WB_LOCLST_SIZE 8 3168 #define REG_MI_MBK9_WB_LOCLST_MASK 0x0000ff00 3169 3170 #define REG_MI_MBK9_WA_LOCKST_SHIFT 0 3171 #define REG_MI_MBK9_WA_LOCKST_SIZE 4 3172 #define REG_MI_MBK9_WA_LOCKST_MASK 0x0000000f 3173 3174 #ifndef SDK_ASM 3175 #define REG_MI_MBK9_FIELD( wc_lockst, wb_loclst, wa_lockst ) \ 3176 (u32)( \ 3177 ((u32)(wc_lockst) << REG_MI_MBK9_WC_LOCKST_SHIFT) | \ 3178 ((u32)(wb_loclst) << REG_MI_MBK9_WB_LOCLST_SHIFT) | \ 3179 ((u32)(wa_lockst) << REG_MI_MBK9_WA_LOCKST_SHIFT)) 3180 #endif 3181 3182 3183 /* MBK_A_LOCK */ 3184 3185 #define REG_MI_MBK_A_LOCK_A3_SHIFT 3 3186 #define REG_MI_MBK_A_LOCK_A3_SIZE 1 3187 #define REG_MI_MBK_A_LOCK_A3_MASK 0x08 3188 3189 #define REG_MI_MBK_A_LOCK_A2_SHIFT 2 3190 #define REG_MI_MBK_A_LOCK_A2_SIZE 1 3191 #define REG_MI_MBK_A_LOCK_A2_MASK 0x04 3192 3193 #define REG_MI_MBK_A_LOCK_A1_SHIFT 1 3194 #define REG_MI_MBK_A_LOCK_A1_SIZE 1 3195 #define REG_MI_MBK_A_LOCK_A1_MASK 0x02 3196 3197 #define REG_MI_MBK_A_LOCK_A0_SHIFT 0 3198 #define REG_MI_MBK_A_LOCK_A0_SIZE 1 3199 #define REG_MI_MBK_A_LOCK_A0_MASK 0x01 3200 3201 #ifndef SDK_ASM 3202 #define REG_MI_MBK_A_LOCK_FIELD( a3, a2, a1, a0 ) \ 3203 (u8)( \ 3204 ((u32)(a3) << REG_MI_MBK_A_LOCK_A3_SHIFT) | \ 3205 ((u32)(a2) << REG_MI_MBK_A_LOCK_A2_SHIFT) | \ 3206 ((u32)(a1) << REG_MI_MBK_A_LOCK_A1_SHIFT) | \ 3207 ((u32)(a0) << REG_MI_MBK_A_LOCK_A0_SHIFT)) 3208 #endif 3209 3210 3211 /* MBK_B_LOCK */ 3212 3213 #define REG_MI_MBK_B_LOCK_B7_SHIFT 7 3214 #define REG_MI_MBK_B_LOCK_B7_SIZE 1 3215 #define REG_MI_MBK_B_LOCK_B7_MASK 0x80 3216 3217 #define REG_MI_MBK_B_LOCK_B6_SHIFT 6 3218 #define REG_MI_MBK_B_LOCK_B6_SIZE 1 3219 #define REG_MI_MBK_B_LOCK_B6_MASK 0x40 3220 3221 #define REG_MI_MBK_B_LOCK_B5_SHIFT 5 3222 #define REG_MI_MBK_B_LOCK_B5_SIZE 1 3223 #define REG_MI_MBK_B_LOCK_B5_MASK 0x20 3224 3225 #define REG_MI_MBK_B_LOCK_B4_SHIFT 4 3226 #define REG_MI_MBK_B_LOCK_B4_SIZE 1 3227 #define REG_MI_MBK_B_LOCK_B4_MASK 0x10 3228 3229 #define REG_MI_MBK_B_LOCK_B3_SHIFT 3 3230 #define REG_MI_MBK_B_LOCK_B3_SIZE 1 3231 #define REG_MI_MBK_B_LOCK_B3_MASK 0x08 3232 3233 #define REG_MI_MBK_B_LOCK_B2_SHIFT 2 3234 #define REG_MI_MBK_B_LOCK_B2_SIZE 1 3235 #define REG_MI_MBK_B_LOCK_B2_MASK 0x04 3236 3237 #define REG_MI_MBK_B_LOCK_B1_SHIFT 1 3238 #define REG_MI_MBK_B_LOCK_B1_SIZE 1 3239 #define REG_MI_MBK_B_LOCK_B1_MASK 0x02 3240 3241 #define REG_MI_MBK_B_LOCK_B0_SHIFT 0 3242 #define REG_MI_MBK_B_LOCK_B0_SIZE 1 3243 #define REG_MI_MBK_B_LOCK_B0_MASK 0x01 3244 3245 #ifndef SDK_ASM 3246 #define REG_MI_MBK_B_LOCK_FIELD( b7, b6, b5, b4, b3, b2, b1, b0 ) \ 3247 (u8)( \ 3248 ((u32)(b7) << REG_MI_MBK_B_LOCK_B7_SHIFT) | \ 3249 ((u32)(b6) << REG_MI_MBK_B_LOCK_B6_SHIFT) | \ 3250 ((u32)(b5) << REG_MI_MBK_B_LOCK_B5_SHIFT) | \ 3251 ((u32)(b4) << REG_MI_MBK_B_LOCK_B4_SHIFT) | \ 3252 ((u32)(b3) << REG_MI_MBK_B_LOCK_B3_SHIFT) | \ 3253 ((u32)(b2) << REG_MI_MBK_B_LOCK_B2_SHIFT) | \ 3254 ((u32)(b1) << REG_MI_MBK_B_LOCK_B1_SHIFT) | \ 3255 ((u32)(b0) << REG_MI_MBK_B_LOCK_B0_SHIFT)) 3256 #endif 3257 3258 3259 /* MBK_C_LOCK */ 3260 3261 #define REG_MI_MBK_C_LOCK_C7_SHIFT 7 3262 #define REG_MI_MBK_C_LOCK_C7_SIZE 1 3263 #define REG_MI_MBK_C_LOCK_C7_MASK 0x80 3264 3265 #define REG_MI_MBK_C_LOCK_C6_SHIFT 6 3266 #define REG_MI_MBK_C_LOCK_C6_SIZE 1 3267 #define REG_MI_MBK_C_LOCK_C6_MASK 0x40 3268 3269 #define REG_MI_MBK_C_LOCK_C5_SHIFT 5 3270 #define REG_MI_MBK_C_LOCK_C5_SIZE 1 3271 #define REG_MI_MBK_C_LOCK_C5_MASK 0x20 3272 3273 #define REG_MI_MBK_C_LOCK_C4_SHIFT 4 3274 #define REG_MI_MBK_C_LOCK_C4_SIZE 1 3275 #define REG_MI_MBK_C_LOCK_C4_MASK 0x10 3276 3277 #define REG_MI_MBK_C_LOCK_C3_SHIFT 3 3278 #define REG_MI_MBK_C_LOCK_C3_SIZE 1 3279 #define REG_MI_MBK_C_LOCK_C3_MASK 0x08 3280 3281 #define REG_MI_MBK_C_LOCK_C2_SHIFT 2 3282 #define REG_MI_MBK_C_LOCK_C2_SIZE 1 3283 #define REG_MI_MBK_C_LOCK_C2_MASK 0x04 3284 3285 #define REG_MI_MBK_C_LOCK_C1_SHIFT 1 3286 #define REG_MI_MBK_C_LOCK_C1_SIZE 1 3287 #define REG_MI_MBK_C_LOCK_C1_MASK 0x02 3288 3289 #define REG_MI_MBK_C_LOCK_C0_SHIFT 0 3290 #define REG_MI_MBK_C_LOCK_C0_SIZE 1 3291 #define REG_MI_MBK_C_LOCK_C0_MASK 0x01 3292 3293 #ifndef SDK_ASM 3294 #define REG_MI_MBK_C_LOCK_FIELD( c7, c6, c5, c4, c3, c2, c1, c0 ) \ 3295 (u8)( \ 3296 ((u32)(c7) << REG_MI_MBK_C_LOCK_C7_SHIFT) | \ 3297 ((u32)(c6) << REG_MI_MBK_C_LOCK_C6_SHIFT) | \ 3298 ((u32)(c5) << REG_MI_MBK_C_LOCK_C5_SHIFT) | \ 3299 ((u32)(c4) << REG_MI_MBK_C_LOCK_C4_SHIFT) | \ 3300 ((u32)(c3) << REG_MI_MBK_C_LOCK_C3_SHIFT) | \ 3301 ((u32)(c2) << REG_MI_MBK_C_LOCK_C2_SHIFT) | \ 3302 ((u32)(c1) << REG_MI_MBK_C_LOCK_C1_SHIFT) | \ 3303 ((u32)(c0) << REG_MI_MBK_C_LOCK_C0_SHIFT)) 3304 #endif 3305 3306 3307 #ifdef __cplusplus 3308 } /* extern "C" */ 3309 #endif 3310 3311 /* TWL_HW_ARM9_IOREG_MI_H_ */ 3312 #endif 3313