1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - HW - include 3 File: armArch.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-09-18#$ 14 $Rev: 8573 $ 15 $Author: okubata_ryoma $ 16 17 *---------------------------------------------------------------------------*/ 18 19 #ifndef NITRO_HW_SYSTEMCONTROL_H_ 20 #define NITRO_HW_SYSTEMCONTROL_H_ 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 #define HW_ICACHE_SIZE 0x2000 // Instruction cache 27 #define HW_DCACHE_SIZE 0x1000 // Data cache 28 #define HW_CACHE_LINE_SIZE 32 29 30 #define HW_SYSTEM_CLOCK 33514000 // More accurately 33513982? 31 32 #define HW_CPU_CLOCK_ARM7 33513982 33 #define HW_CPU_CLOCK_ARM9 67027964 34 35 #ifdef SDK_ARM7 36 #define HW_CPU_CLOCK HW_CPU_CLOCK_ARM7 37 #else 38 #define HW_CPU_CLOCK HW_CPU_CLOCK_ARM9 39 #endif 40 41 //********************************************************************** 42 // IRIS register control bits 43 //********************************************************************** 44 45 //---------------------------------------------------------------------- 46 // Programs status registers 47 //---------------------------------------------------------------------- 48 49 #define HW_PSR_CPU_MODE_MASK 0x1f // CPU mode 50 51 #define HW_PSR_USER_MODE 0x10 // USER 52 #define HW_PSR_FIQ_MODE 0x11 // FIQ 53 #define HW_PSR_IRQ_MODE 0x12 // IRQ 54 #define HW_PSR_SVC_MODE 0x13 // Supervisor 55 #define HW_PSR_ABORT_MODE 0x17 // Abort (prefetch/data) 56 #define HW_PSR_UNDEF_MODE 0x1b // Undefined instruction 57 #define HW_PSR_SYS_MODE 0x1f // System 58 59 #define HW_PSR_ARM_STATE 0x0 // ARM state 60 #define HW_PSR_THUMB_STATE 0x20 // Thumb state 61 62 #define HW_PSR_FIQ_DISABLE 0x40 // Disable FIQ 63 #define HW_PSR_IRQ_DISABLE 0x80 // Disable IRQ 64 #define HW_PSR_IRQ_FIQ_DISABLE 0xc0 // Disable FIQ and IRQ 65 66 #define HW_PSR_Q_FLAG 0x08000000 // Sticky overflow 67 #define HW_PSR_V_FLAG 0x10000000 // Overflow 68 #define HW_PSR_C_FLAG 0x20000000 // Carry / borrow / extend 69 #define HW_PSR_Z_FLAG 0x40000000 // Zero 70 #define HW_PSR_N_FLAG 0x80000000 // Minus / less than 71 72 73 //---------------------------------------------------------------------- 74 // System control coprocessor 75 //---------------------------------------------------------------------- 76 77 // Register 1 (Master control) 78 79 #define HW_C1_SB1_BITSET 0x00000078 // 1 fixed bit row for register 1 80 81 #define HW_C1_ITCM_LOAD_MODE 0x00080000 // Instruction TCM load mode 82 #define HW_C1_DTCM_LOAD_MODE 0x00020000 // Data TCM load mode 83 #define HW_C1_ITCM_ENABLE 0x00040000 // Enable instruction TCM 84 #define HW_C1_DTCM_ENABLE 0x00010000 // Enable data TCM 85 #define HW_C1_LD_INTERWORK_DISABLE 0x00008000 // Disable interworking with Load instruction 86 #define HW_C1_CACHE_ROUND_ROBIN 0x00004000 // Cache replacement algorithm, round robin (Worst time bit ratio is stable) 87 #define HW_C1_CACHE_PSEUDO_RANDOM 0x00000000 // Pseudo random 88 #define HW_C1_EXCEPT_VEC_UPPER 0x00002000 // Exception vector, High-order address (set to this) 89 #define HW_C1_EXCEPT_VEC_LOWER 0x00000000 // Lower-order address 90 #define HW_C1_ICACHE_ENABLE 0x00001000 // Enable instruction cache 91 #define HW_C1_DCACHE_ENABLE 0x00000004 // Enable data cache 92 #define HW_C1_LITTLE_ENDIAN 0x00000000 // Little-endian 93 #define HW_C1_BIG_ENDIAN 0x00000080 // Big-endian 94 #define HW_C1_PROTECT_UNIT_ENABLE 0x00000001 // Enable protection unit 95 96 #define HW_C1_ICACHE_ENABLE_SHIFT 12 97 #define HW_C1_DCACHE_ENABLE_SHIFT 2 98 99 100 // Register 2 (Protection region cache setting) 101 102 #define HW_C2_PR0_SFT 0 // Protection region 0 103 #define HW_C2_PR1_SFT 1 // �P 104 #define HW_C2_PR2_SFT 2 // �Q 105 #define HW_C2_PR3_SFT 3 // �R 106 #define HW_C2_PR4_SFT 4 // �S 107 #define HW_C2_PR5_SFT 5 // �T 108 #define HW_C2_PR6_SFT 6 // �U 109 #define HW_C2_PR7_SFT 7 // �V 110 111 112 // Register 3 (Protection region write buffer settings) 113 114 #define HW_C3_PR0_SFT 0 // Protection region 0 115 #define HW_C3_PR1_SFT 1 // �P 116 #define HW_C3_PR2_SFT 2 // �Q 117 #define HW_C3_PR3_SFT 3 // �R 118 #define HW_C3_PR4_SFT 4 // �S 119 #define HW_C3_PR5_SFT 5 // �T 120 #define HW_C3_PR6_SFT 6 // �U 121 #define HW_C3_PR7_SFT 7 // �V 122 123 124 // Register 5 (Protection region access permission) 125 126 #define HW_C5_PERMIT_MASK 0xf // Protection region access permission mask 127 128 #define HW_C5_PERMIT_NA 0 // Access not permitted 129 #define HW_C5_PERMIT_RW 1 // Read write permitted 130 #define HW_C5_PERMIT_RO 5 // Read only permitted 131 132 #define HW_C5_PR0_SFT 0 // Protection region 0 133 #define HW_C5_PR1_SFT 4 // �P 134 #define HW_C5_PR2_SFT 8 // �Q 135 #define HW_C5_PR3_SFT 12 // �R 136 #define HW_C5_PR4_SFT 16 // �S 137 #define HW_C5_PR5_SFT 20 // �T 138 #define HW_C5_PR6_SFT 24 // �U 139 #define HW_C5_PR7_SFT 28 // �V 140 141 142 // Register 6 (protection region base address / size) 143 144 #define HW_C6_PR_SIZE_MASK 0x0000003e // Protection region size 145 #define HW_C6_PR_BASE_MASK 0xfffff000 // Base address 146 147 #define HW_C6_PR_SIZE_SHIFT 1 148 #define HW_C6_PR_BASE_SHIFT 12 149 150 #define HW_C6_PR_ENABLE 1 // Enable Protection region 151 #define HW_C6_PR_DISABLE 0 // disable 152 153 #define HW_C6_PR_4KB 0x16 // Region size 4 KByte 154 #define HW_C6_PR_8KB 0x18 // 8KB 155 #define HW_C6_PR_16KB 0x1a // 16KB 156 #define HW_C6_PR_32KB 0x1c // 32KB 157 #define HW_C6_PR_64KB 0x1e // 64KB 158 #define HW_C6_PR_128KB 0x20 // 128KB 159 #define HW_C6_PR_256KB 0x22 // 256KB 160 #define HW_C6_PR_512KB 0x24 // 512KB 161 #define HW_C6_PR_1MB 0x26 // 1MB 162 #define HW_C6_PR_2MB 0x28 // 2MB 163 #define HW_C6_PR_4MB 0x2a // 4MB 164 #define HW_C6_PR_8MB 0x2c // 8MB 165 #define HW_C6_PR_16MB 0x2e // 16MB 166 #define HW_C6_PR_32MB 0x30 // 32MB 167 #define HW_C6_PR_64MB 0x32 // 64MB 168 #define HW_C6_PR_128MB 0x34 // 128MB 169 #define HW_C6_PR_256MB 0x36 // 256MB 170 #define HW_C6_PR_512MB 0x38 // 512MB 171 #define HW_C6_PR_1GB 0x3a // 1GB 172 #define HW_C6_PR_2GB 0x3c // 2GB 173 #define HW_C6_PR_4GB 0x3e // 4GB 174 175 176 // Register 7.13 (Instruction cache prefetch) 177 178 #define HW_C7_ICACHE_PREFCHP_MASK 0xffffffe0 // Instruction cache prefetch address 179 180 181 // Registers 7.10, 7.14 (Cache index operation) 182 183 #define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 // Instruction cache index 184 #define HW_C7_DCACHE_INDEX_MASK 0x000003e0 // Data cache index 185 #define HW_C7_CACHE_SET_NO_MASK 0xc0000000 // Cache set No. 186 187 #define HW_C7_CACHE_INDEX_SHIFT 5 188 #define HW_C7_CACHE_SET_NO_SHIFT 30 189 190 191 // Register 9.0 (cache lockdown) 192 193 #define HW_C9_LOCKDOWN_SET_NO_MASK 0x00000003 // Cache lockdown set No. 194 195 #define HW_C9_LOCKDOWN_SET_NO_SHIFT 0 196 197 #define HW_C9_LOCKDOWN_LOAD_MODE 0x80000000 // Cache lockdown load mode 198 199 200 // Register 9.1 (TCM base address / size) 201 202 #define HW_C9_TCMR_SIZE_MASK 0x0000003e // TCM region size 203 #define HW_C9_TCMR_BASE_MASK 0xfffff000 // Base address 204 205 #define HW_C9_TCMR_SIZE_SHIFT 1 206 #define HW_C9_TCMR_BASE_SHIFT 12 207 208 #define HW_C9_TCMR_4KB 0x06 // Region size 4 KByte 209 #define HW_C9_TCMR_8KB 0x08 // 8KB 210 #define HW_C9_TCMR_16KB 0x0a // 16KB 211 #define HW_C9_TCMR_32KB 0x0c // 32KB 212 #define HW_C9_TCMR_64KB 0x0e // 64KB 213 #define HW_C9_TCMR_128KB 0x10 // 128KB 214 #define HW_C9_TCMR_256KB 0x12 // 256KB 215 #define HW_C9_TCMR_512KB 0x14 // 512KB 216 #define HW_C9_TCMR_1MB 0x16 // 1MB 217 #define HW_C9_TCMR_2MB 0x18 // 2MB 218 #define HW_C9_TCMR_4MB 0x1a // 4MB 219 #define HW_C9_TCMR_8MB 0x1c // 8MB 220 #define HW_C9_TCMR_16MB 0x1e // 16MB 221 #define HW_C9_TCMR_32MB 0x20 // 32MB 222 #define HW_C9_TCMR_64MB 0x22 // 64MB 223 #define HW_C9_TCMR_128MB 0x24 // 128MB 224 #define HW_C9_TCMR_256MB 0x26 // 256MB 225 #define HW_C9_TCMR_512MB 0x28 // 512MB 226 #define HW_C9_TCMR_1GB 0x2a // 1GB 227 #define HW_C9_TCMR_2GB 0x2c // 2GB 228 #define HW_C9_TCMR_4GB 0x2e // 4GB 229 230 #ifdef __cplusplus 231 } /* extern "C" */ 232 #endif 233 234 /* NITRO_HW_SYSTEMCONTROL_H_ */ 235 #endif 236