1 /*---------------------------------------------------------------------------*
2 Project: NintendoWare
3 File: ut_CmdCache.cpp
4
5 Copyright (C)2009-2011 Nintendo/HAL Laboratory, Inc. All rights reserved.
6
7 These coded instructions, statements, and computer programs contain proprietary
8 information of Nintendo and/or its licensed developers and are protected by
9 national and international copyright laws. They may not be disclosed to third
10 parties or copied or duplicated in any form, in whole or in part, without the
11 prior written consent of Nintendo.
12
13 The content herein is highly confidential and should be handled accordingly.
14
15 $Revision: 31311 $
16 *---------------------------------------------------------------------------*/
17
18 #include "precompiled.h"
19
20 #include <nn/assert.h>
21 #include <nw/ut/ut_Inlines.h>
22 #include <nw/ut/ut_CmdCache.h>
23
24 namespace nw {
25 namespace ut {
26 namespace internal {
27
28 namespace {
29
30 #if !defined(NW_RELEASE)
31 struct PicaRegMnemonic
32 {
33 u16 address;
34 const char* mnemonic;
35 };
36
37 const PicaRegMnemonic s_PicaRegMnemonic[] =
38 {
39 { 0x040, "PICA_REG_CULL_FACE" },
40 { 0x041, "PICA_REG_VIEWPORT_WIDTH1" },
41 { 0x042, "PICA_REG_VIEWPORT_WIDTH2" },
42 { 0x043, "PICA_REG_VIEWPORT_HEIGHT1" },
43 { 0x044, "PICA_REG_VIEWPORT_HEIGHT2" },
44 { 0x047, "PICA_REG_FRAG_OP_CLIP" },
45 { 0x048, "PICA_REG_FRAG_OP_CLIP_DATA1" },
46 { 0x049, "PICA_REG_FRAG_OP_CLIP_DATA2" },
47 { 0x04a, "PICA_REG_FRAG_OP_CLIP_DATA3" },
48 { 0x04b, "PICA_REG_FRAG_OP_CLIP_DATA4" },
49 { 0x04d, "PICA_REG_FRAG_OP_WSCALE_DATA1" },
50 { 0x04e, "PICA_REG_FRAG_OP_WSCALE_DATA2" },
51 { 0x04f, "PICA_REG_GS_OUT_REG_NUM0" },
52 { 0x04f, "PICA_REG_VS_OUT_REG_NUM0" },
53 { 0x050, "PICA_REG_GS_OUT_ATTR0" },
54 { 0x050, "PICA_REG_VS_OUT_ATTR0" },
55 { 0x051, "PICA_REG_GS_OUT_ATTR1" },
56 { 0x051, "PICA_REG_VS_OUT_ATTR1" },
57 { 0x052, "PICA_REG_GS_OUT_ATTR2" },
58 { 0x052, "PICA_REG_VS_OUT_ATTR2" },
59 { 0x053, "PICA_REG_GS_OUT_ATTR3" },
60 { 0x053, "PICA_REG_VS_OUT_ATTR3" },
61 { 0x054, "PICA_REG_GS_OUT_ATTR4" },
62 { 0x054, "PICA_REG_VS_OUT_ATTR4" },
63 { 0x055, "PICA_REG_GS_OUT_ATTR5" },
64 { 0x055, "PICA_REG_VS_OUT_ATTR5" },
65 { 0x056, "PICA_REG_GS_OUT_ATTR6" },
66 { 0x056, "PICA_REG_VS_OUT_ATTR6" },
67 { 0x061, "PICA_REG_EARLY_DEPTH_FUNC" },
68 { 0x062, "PICA_REG_EARLY_DEPTH_TEST1" },
69 { 0x064, "PICA_REG_GS_OUT_ATTR_MODE" },
70 { 0x064, "PICA_REG_VS_OUT_ATTR_MODE" },
71 { 0x065, "PICA_REG_SCISSOR" },
72 { 0x066, "PICA_REG_SCISSOR_XY" },
73 { 0x067, "PICA_REG_SCISSOR_SIZE" },
74 { 0x068, "PICA_REG_VIEWPORT_XY" },
75 { 0x06a, "PICA_REG_EARLY_DEPTH_DATA" },
76 { 0x06d, "PICA_REG_FRAG_OP_WSCALE" },
77 { 0x06e, "PICA_REG_RENDER_BUF_RESOLUTION1" },
78 { 0x06f, "PICA_REG_GS_OUT_ATTR_CLK" },
79 { 0x06f, "PICA_REG_VS_OUT_ATTR_CLK" },
80 { 0x080, "PICA_REG_TEXTURE_FUNC" },
81 { 0x081, "PICA_REG_TEXTURE0_BORDER_COLOR" },
82 { 0x082, "PICA_REG_TEXTURE0_SIZE" },
83 { 0x083, "PICA_REG_TEXTURE0_WRAP_FILTER" },
84 { 0x084, "PICA_REG_TEXTURE0_LOD" },
85 { 0x085, "PICA_REG_TEXTURE0_ADDR1" },
86 { 0x086, "PICA_REG_TEXTURE0_ADDR2" },
87 { 0x087, "PICA_REG_TEXTURE0_ADDR3" },
88 { 0x088, "PICA_REG_TEXTURE0_ADDR4" },
89 { 0x089, "PICA_REG_TEXTURE0_ADDR5" },
90 { 0x08a, "PICA_REG_TEXTURE0_ADDR6" },
91 { 0x08b, "PICA_REG_TEXTURE0_SHADOW" },
92 { 0x08e, "PICA_REG_TEXTURE0_FORMAT" },
93 { 0x08f, "PICA_REG_FRAG_LIGHT_EN0" },
94 { 0x091, "PICA_REG_TEXTURE1_BORDER_COLOR" },
95 { 0x092, "PICA_REG_TEXTURE1_SIZE" },
96 { 0x093, "PICA_REG_TEXTURE1_WRAP_FILTER" },
97 { 0x094, "PICA_REG_TEXTURE1_LOD" },
98 { 0x095, "PICA_REG_TEXTURE1_ADDR" },
99 { 0x096, "PICA_REG_TEXTURE1_FORMAT" },
100 { 0x099, "PICA_REG_TEXTURE2_BORDER_COLOR" },
101 { 0x09a, "PICA_REG_TEXTURE2_SIZE" },
102 { 0x09b, "PICA_REG_TEXTURE2_WRAP_FILTER" },
103 { 0x09c, "PICA_REG_TEXTURE2_LOD" },
104 { 0x09d, "PICA_REG_TEXTURE2_ADDR" },
105 { 0x09e, "PICA_REG_TEXTURE2_FORMAT" },
106 { 0x0a8, "PICA_REG_TEXTURE3_PROTEX0" },
107 { 0x0a9, "PICA_REG_TEXTURE3_PROTEX1" },
108 { 0x0aa, "PICA_REG_TEXTURE3_PROTEX2" },
109 { 0x0ab, "PICA_REG_TEXTURE3_PROTEX3" },
110 { 0x0ac, "PICA_REG_TEXTURE3_PROTEX4" },
111 { 0x0ad, "PICA_REG_TEXTURE3_PROTEX5" },
112 { 0x0af, "PICA_REG_PROTEX_LUT" },
113 { 0x0b0, "PICA_REG_PROTEX_LUT_DATA0" },
114 { 0x0b1, "PICA_REG_PROTEX_LUT_DATA1" },
115 { 0x0b2, "PICA_REG_PROTEX_LUT_DATA2" },
116 { 0x0b3, "PICA_REG_PROTEX_LUT_DATA3" },
117 { 0x0b4, "PICA_REG_PROTEX_LUT_DATA4" },
118 { 0x0b5, "PICA_REG_PROTEX_LUT_DATA5" },
119 { 0x0b6, "PICA_REG_PROTEX_LUT_DATA6" },
120 { 0x0b7, "PICA_REG_PROTEX_LUT_DATA7" },
121 { 0x0c0, "PICA_REG_TEX_ENV_0" },
122 { 0x0c1, "PICA_REG_TEX_ENV_0_OPERAND" },
123 { 0x0c2, "PICA_REG_TEX_ENV_0_COMBINE" },
124 { 0x0c3, "PICA_REG_TEX_ENV_0_COLOR" },
125 { 0x0c4, "PICA_REG_TEX_ENV_0_SCALE" },
126 { 0x0c8, "PICA_REG_TEX_ENV_1" },
127 { 0x0c9, "PICA_REG_TEX_ENV_1_OPERAND" },
128 { 0x0ca, "PICA_REG_TEX_ENV_1_COMBINE" },
129 { 0x0cb, "PICA_REG_TEX_ENV_1_COLOR" },
130 { 0x0cc, "PICA_REG_TEX_ENV_1_SCALE" },
131 { 0x0d0, "PICA_REG_TEX_ENV_2" },
132 { 0x0d1, "PICA_REG_TEX_ENV_2_OPERAND" },
133 { 0x0d2, "PICA_REG_TEX_ENV_2_COMBINE" },
134 { 0x0d3, "PICA_REG_TEX_ENV_2_COLOR" },
135 { 0x0d4, "PICA_REG_TEX_ENV_2_SCALE" },
136 { 0x0d8, "PICA_REG_TEX_ENV_3" },
137 { 0x0d9, "PICA_REG_TEX_ENV_3_OPERAND" },
138 { 0x0da, "PICA_REG_TEX_ENV_3_COMBINE" },
139 { 0x0db, "PICA_REG_TEX_ENV_3_COLOR" },
140 { 0x0dc, "PICA_REG_TEX_ENV_3_SCALE" },
141 { 0x0e0, "PICA_REG_GAS_FOG_MODE" },
142 { 0x0e0, "PICA_REG_TEX_ENV_BUF_INPUT" },
143 { 0x0e1, "PICA_REG_FOG_COLOR" },
144 { 0x0e4, "PICA_REG_GAS_ATTENUATION" },
145 { 0x0e5, "PICA_REG_GAS_ACCMAX" },
146 { 0x0e6, "PICA_REG_FOG_LUT_INDEX" },
147 { 0x0e8, "PICA_REG_FOG_LUT_DATA0" },
148 { 0x0e9, "PICA_REG_FOG_LUT_DATA1" },
149 { 0x0ea, "PICA_REG_FOG_LUT_DATA2" },
150 { 0x0eb, "PICA_REG_FOG_LUT_DATA3" },
151 { 0x0ec, "PICA_REG_FOG_LUT_DATA4" },
152 { 0x0ed, "PICA_REG_FOG_LUT_DATA5" },
153 { 0x0ee, "PICA_REG_FOG_LUT_DATA6" },
154 { 0x0ef, "PICA_REG_FOG_LUT_DATA7" },
155 { 0x0f0, "PICA_REG_TEX_ENV_4" },
156 { 0x0f1, "PICA_REG_TEX_ENV_4_OPERAND" },
157 { 0x0f2, "PICA_REG_TEX_ENV_4_COMBINE" },
158 { 0x0f3, "PICA_REG_TEX_ENV_4_COLOR" },
159 { 0x0f4, "PICA_REG_TEX_ENV_4_SCALE" },
160 { 0x0f8, "PICA_REG_TEX_ENV_5" },
161 { 0x0f9, "PICA_REG_TEX_ENV_5_OPERAND" },
162 { 0x0fa, "PICA_REG_TEX_ENV_5_COMBINE" },
163 { 0x0fb, "PICA_REG_TEX_ENV_5_COLOR" },
164 { 0x0fc, "PICA_REG_TEX_ENV_5_SCALE" },
165 { 0x0fd, "PICA_REG_TEX_ENV_BUF_COLOR" },
166 { 0x100, "PICA_REG_COLOR_OPERATION" },
167 { 0x101, "PICA_REG_BLEND_FUNC" },
168 { 0x102, "PICA_REG_LOGIC_OP" },
169 { 0x103, "PICA_REG_BLEND_COLOR" },
170 { 0x104, "PICA_REG_FRAG_OP_ALPHA_TEST" },
171 { 0x105, "PICA_REG_STENCIL_TEST" },
172 { 0x106, "PICA_REG_STENCIL_OP" },
173 { 0x107, "PICA_REG_DEPTH_COLOR_MASK" },
174 { 0x110, "PICA_REG_COLOR_BUFFER_CLEAR0" },
175 { 0x111, "PICA_REG_COLOR_BUFFER_CLEAR1" },
176 { 0x112, "PICA_REG_COLOR_BUFFER_READ" },
177 { 0x113, "PICA_REG_COLOR_BUFFER_WRITE" },
178 { 0x114, "PICA_REG_DEPTH_STENCIL_READ" },
179 { 0x115, "PICA_REG_DEPTH_STENCIL_WRITE" },
180 { 0x116, "PICA_REG_RENDER_BUF_DEPTH_MODE" },
181 { 0x117, "PICA_REG_RENDER_BUF_COLOR_MODE" },
182 { 0x118, "PICA_REG_EARLY_DEPTH_TEST2" },
183 { 0x11b, "PICA_REG_RENDER_BLOCK_FORMAT" },
184 { 0x11c, "PICA_REG_RENDER_BUF_DEPTH_ADDR" },
185 { 0x11d, "PICA_REG_RENDER_BUF_COLOR_ADDR" },
186 { 0x11e, "PICA_REG_RENDER_BUF_RESOLUTION0" },
187 { 0x120, "PICA_REG_GAS_LIGHT_XY" },
188 { 0x121, "PICA_REG_GAS_LIGHT_Z" },
189 { 0x122, "PICA_REG_GAS_LIGHT_Z_COLOR" },
190 { 0x123, "PICA_REG_GAS_LUT_INDEX" },
191 { 0x124, "PICA_REG_GAS_LUT_DATA" },
192 { 0x126, "PICA_REG_GAS_DELTAZ_DEPTH" },
193 { 0x130, "PICA_REG_FRAG_OP_SHADOW" },
194 { 0x140, "PICA_REG_FRAG_LIGHT0_SPECULAR0" },
195 { 0x140, "PICA_REG_FRAG_LIGHT_START" },
196 { 0x141, "PICA_REG_FRAG_LIGHT0_SPECULAR1" },
197 { 0x142, "PICA_REG_FRAG_LIGHT0_DIFFUSE" },
198 { 0x143, "PICA_REG_FRAG_LIGHT0_AMBIENT" },
199 { 0x144, "PICA_REG_FRAG_LIGHT0_POSITION_XY" },
200 { 0x145, "PICA_REG_FRAG_LIGHT0_POSITION_Z" },
201 { 0x146, "PICA_REG_FRAG_LIGHT0_SPOT_XY" },
202 { 0x147, "PICA_REG_FRAG_LIGHT0_SPOT_Z" },
203 { 0x149, "PICA_REG_FRAG_LIGHT0_TYPE" },
204 { 0x14a, "PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS" },
205 { 0x14b, "PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE" },
206 { 0x150, "PICA_REG_FRAG_LIGHT1_SPECULAR0" },
207 { 0x151, "PICA_REG_FRAG_LIGHT1_SPECULAR1" },
208 { 0x152, "PICA_REG_FRAG_LIGHT1_DIFFUSE" },
209 { 0x153, "PICA_REG_FRAG_LIGHT1_AMBIENT" },
210 { 0x154, "PICA_REG_FRAG_LIGHT1_POSITION_XY" },
211 { 0x155, "PICA_REG_FRAG_LIGHT1_POSITION_Z" },
212 { 0x156, "PICA_REG_FRAG_LIGHT1_SPOT_XY" },
213 { 0x157, "PICA_REG_FRAG_LIGHT1_SPOT_Z" },
214 { 0x159, "PICA_REG_FRAG_LIGHT1_TYPE" },
215 { 0x15a, "PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS" },
216 { 0x15b, "PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE" },
217 { 0x160, "PICA_REG_FRAG_LIGHT2_SPECULAR0" },
218 { 0x161, "PICA_REG_FRAG_LIGHT2_SPECULAR1" },
219 { 0x162, "PICA_REG_FRAG_LIGHT2_DIFFUSE" },
220 { 0x163, "PICA_REG_FRAG_LIGHT2_AMBIENT" },
221 { 0x164, "PICA_REG_FRAG_LIGHT2_POSITION_XY" },
222 { 0x165, "PICA_REG_FRAG_LIGHT2_POSITION_Z" },
223 { 0x166, "PICA_REG_FRAG_LIGHT2_SPOT_XY" },
224 { 0x167, "PICA_REG_FRAG_LIGHT2_SPOT_Z" },
225 { 0x169, "PICA_REG_FRAG_LIGHT2_TYPE" },
226 { 0x16a, "PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS" },
227 { 0x16b, "PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE" },
228 { 0x170, "PICA_REG_FRAG_LIGHT3_SPECULAR0" },
229 { 0x171, "PICA_REG_FRAG_LIGHT3_SPECULAR1" },
230 { 0x172, "PICA_REG_FRAG_LIGHT3_DIFFUSE" },
231 { 0x173, "PICA_REG_FRAG_LIGHT3_AMBIENT" },
232 { 0x174, "PICA_REG_FRAG_LIGHT3_POSITION_XY" },
233 { 0x175, "PICA_REG_FRAG_LIGHT3_POSITION_Z" },
234 { 0x176, "PICA_REG_FRAG_LIGHT3_SPOT_XY" },
235 { 0x177, "PICA_REG_FRAG_LIGHT3_SPOT_Z" },
236 { 0x179, "PICA_REG_FRAG_LIGHT3_TYPE" },
237 { 0x17a, "PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS" },
238 { 0x17b, "PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE" },
239 { 0x180, "PICA_REG_FRAG_LIGHT4_SPECULAR0" },
240 { 0x181, "PICA_REG_FRAG_LIGHT4_SPECULAR1" },
241 { 0x182, "PICA_REG_FRAG_LIGHT4_DIFFUSE" },
242 { 0x183, "PICA_REG_FRAG_LIGHT4_AMBIENT" },
243 { 0x184, "PICA_REG_FRAG_LIGHT4_POSITION_XY" },
244 { 0x185, "PICA_REG_FRAG_LIGHT4_POSITION_Z" },
245 { 0x186, "PICA_REG_FRAG_LIGHT4_SPOT_XY" },
246 { 0x187, "PICA_REG_FRAG_LIGHT4_SPOT_Z" },
247 { 0x189, "PICA_REG_FRAG_LIGHT4_TYPE" },
248 { 0x18a, "PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS" },
249 { 0x18b, "PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE" },
250 { 0x190, "PICA_REG_FRAG_LIGHT5_SPECULAR0" },
251 { 0x191, "PICA_REG_FRAG_LIGHT5_SPECULAR1" },
252 { 0x192, "PICA_REG_FRAG_LIGHT5_DIFFUSE" },
253 { 0x193, "PICA_REG_FRAG_LIGHT5_AMBIENT" },
254 { 0x194, "PICA_REG_FRAG_LIGHT5_POSITION_XY" },
255 { 0x195, "PICA_REG_FRAG_LIGHT5_POSITION_Z" },
256 { 0x196, "PICA_REG_FRAG_LIGHT5_SPOT_XY" },
257 { 0x197, "PICA_REG_FRAG_LIGHT5_SPOT_Z" },
258 { 0x199, "PICA_REG_FRAG_LIGHT5_TYPE" },
259 { 0x19a, "PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS" },
260 { 0x19b, "PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE" },
261 { 0x1a0, "PICA_REG_FRAG_LIGHT6_SPECULAR0" },
262 { 0x1a1, "PICA_REG_FRAG_LIGHT6_SPECULAR1" },
263 { 0x1a2, "PICA_REG_FRAG_LIGHT6_DIFFUSE" },
264 { 0x1a3, "PICA_REG_FRAG_LIGHT6_AMBIENT" },
265 { 0x1a4, "PICA_REG_FRAG_LIGHT6_POSITION_XY" },
266 { 0x1a5, "PICA_REG_FRAG_LIGHT6_POSITION_Z" },
267 { 0x1a6, "PICA_REG_FRAG_LIGHT6_SPOT_XY" },
268 { 0x1a7, "PICA_REG_FRAG_LIGHT6_SPOT_Z" },
269 { 0x1a9, "PICA_REG_FRAG_LIGHT6_TYPE" },
270 { 0x1aa, "PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS" },
271 { 0x1ab, "PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE" },
272 { 0x1b0, "PICA_REG_FRAG_LIGHT7_SPECULAR0" },
273 { 0x1b1, "PICA_REG_FRAG_LIGHT7_SPECULAR1" },
274 { 0x1b2, "PICA_REG_FRAG_LIGHT7_DIFFUSE" },
275 { 0x1b3, "PICA_REG_FRAG_LIGHT7_AMBIENT" },
276 { 0x1b4, "PICA_REG_FRAG_LIGHT7_POSITION_XY" },
277 { 0x1b5, "PICA_REG_FRAG_LIGHT7_POSITION_Z" },
278 { 0x1b6, "PICA_REG_FRAG_LIGHT7_SPOT_XY" },
279 { 0x1b7, "PICA_REG_FRAG_LIGHT7_SPOT_Z" },
280 { 0x1b9, "PICA_REG_FRAG_LIGHT7_TYPE" },
281 { 0x1ba, "PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS" },
282 { 0x1bb, "PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE" },
283 { 0x1c0, "PICA_REG_FRAG_LIGHT_AMBIENT" },
284 { 0x1c2, "PICA_REG_FRAG_LIGHT_SRC_NUM" },
285 { 0x1c3, "PICA_REG_FRAG_LIGHT_FUNC_MODE0" },
286 { 0x1c4, "PICA_REG_FRAG_LIGHT_FUNC_MODE1" },
287 { 0x1c5, "PICA_REG_FRAG_LIGHT_LUT" },
288 { 0x1c6, "PICA_REG_FRAG_LIGHT_EN1" },
289 { 0x1c8, "PICA_REG_FRAG_LIGHT_LUT_DATA0" },
290 { 0x1c9, "PICA_REG_FRAG_LIGHT_LUT_DATA1" },
291 { 0x1ca, "PICA_REG_FRAG_LIGHT_LUT_DATA2" },
292 { 0x1cb, "PICA_REG_FRAG_LIGHT_LUT_DATA3" },
293 { 0x1cc, "PICA_REG_FRAG_LIGHT_LUT_DATA4" },
294 { 0x1cd, "PICA_REG_FRAG_LIGHT_LUT_DATA5" },
295 { 0x1ce, "PICA_REG_FRAG_LIGHT_LUT_DATA6" },
296 { 0x1cf, "PICA_REG_FRAG_LIGHT_LUT_DATA7" },
297 { 0x1d0, "PICA_REG_FRAG_LIGHT_ABSLUTINPUT" },
298 { 0x1d1, "PICA_REG_FRAG_LIGHT_LUTINPUT" },
299 { 0x1d2, "PICA_REG_FRAG_LIGHT_LUTSCALE" },
300 { 0x1d9, "PICA_REG_FRAG_LIGHT_SRC_EN_ID" },
301 { 0x200, "PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR" },
302 { 0x201, "PICA_REG_VTX_ATTR_ARRAYS0" },
303 { 0x202, "PICA_REG_VTX_ATTR_ARRAYS1" },
304 { 0x203, "PICA_REG_LOAD_ARRAY0_ATTR_OFFSET" },
305 { 0x204, "PICA_REG_LOAD_ARRAY0_ELEMENT0" },
306 { 0x205, "PICA_REG_LOAD_ARRAY0_ELEMENT1" },
307 { 0x227, "PICA_REG_INDEX_ARRAY_ADDR_OFFSET" },
308 { 0x228, "PICA_REG_DRAW_VERTEX_NUM" },
309 { 0x229, "PICA_REG_DRAW_MODE0" },
310 { 0x22a, "PICA_REG_DRAW_VERTEX_OFFSET" },
311 { 0x22e, "PICA_REG_START_DRAW_ARRAY" },
312 { 0x22f, "PICA_REG_START_DRAW_ELEMENT" },
313 { 0x231, "PICA_REG_VTX_FUNC" },
314 { 0x232, "PICA_REG_VS_FIXED_ATTR" },
315 { 0x233, "PICA_REG_VS_FIXED_ATTR_DATA0" },
316 { 0x234, "PICA_REG_VS_FIXED_ATTR_DATA1" },
317 { 0x235, "PICA_REG_VS_FIXED_ATTR_DATA2" },
318 { 0x242, "PICA_REG_VS_ATTR_NUM1" },
319 { 0x244, "PICA_REG_VS_COM_MODE" },
320 { 0x245, "PICA_REG_START_DRAW_FUNC0" },
321 { 0x24a, "PICA_REG_VS_OUT_REG_NUM1" },
322 { 0x251, "PICA_REG_VS_OUT_REG_NUM2" },
323 { 0x252, "PICA_REG_GS_MISC_REG0" },
324 { 0x253, "PICA_REG_DRAW_MODE1" },
325 { 0x254, "PICA_REG_GS_MISC_REG1" },
326 { 0x25e, "PICA_REG_GS_OUT_REG_NUM3" },
327 { 0x25e, "PICA_REG_VS_OUT_REG_NUM3" },
328 { 0x25f, "PICA_REG_START_DRAW_FUNC1" },
329 { 0x280, "PICA_REG_GS_BOOL" },
330 { 0x281, "PICA_REG_GS_INT0" },
331 { 0x282, "PICA_REG_GS_INT1" },
332 { 0x283, "PICA_REG_GS_INT2" },
333 { 0x284, "PICA_REG_GS_INT3" },
334 { 0x289, "PICA_REG_GS_ATTR_NUM" },
335 { 0x28a, "PICA_REG_GS_START_ADDR" },
336 { 0x28b, "PICA_REG_GS_ATTR_IN_REG_MAP0" },
337 { 0x28c, "PICA_REG_GS_ATTR_IN_REG_MAP1" },
338 { 0x28d, "PICA_REG_GS_OUT_REG_MASK" },
339 { 0x28f, "PICA_REG_GS_PROG_RENEWAL_END" },
340 { 0x290, "PICA_REG_GS_FLOAT_ADDR" },
341 { 0x291, "PICA_REG_GS_FLOAT_DATA1" },
342 { 0x292, "PICA_REG_GS_FLOAT_DATA2" },
343 { 0x293, "PICA_REG_GS_FLOAT_DATA3" },
344 { 0x294, "PICA_REG_GS_FLOAT_DATA4" },
345 { 0x295, "PICA_REG_GS_FLOAT_DATA5" },
346 { 0x296, "PICA_REG_GS_FLOAT_DATA6" },
347 { 0x297, "PICA_REG_GS_FLOAT_DATA7" },
348 { 0x298, "PICA_REG_GS_FLOAT_DATA8" },
349 { 0x29b, "PICA_REG_GS_PROG_ADDR" },
350 { 0x29c, "PICA_REG_GS_PROG_DATA0" },
351 { 0x29d, "PICA_REG_GS_PROG_DATA1" },
352 { 0x29e, "PICA_REG_GS_PROG_DATA2" },
353 { 0x29f, "PICA_REG_GS_PROG_DATA3" },
354 { 0x2a0, "PICA_REG_GS_PROG_DATA4" },
355 { 0x2a1, "PICA_REG_GS_PROG_DATA5" },
356 { 0x2a2, "PICA_REG_GS_PROG_DATA6" },
357 { 0x2a3, "PICA_REG_GS_PROG_DATA7" },
358 { 0x2a5, "PICA_REG_GS_PROG_SWIZZLE_ADDR" },
359 { 0x2a6, "PICA_REG_GS_PROG_SWIZZLE_DATA0" },
360 { 0x2a7, "PICA_REG_GS_PROG_SWIZZLE_DATA1" },
361 { 0x2a8, "PICA_REG_GS_PROG_SWIZZLE_DATA2" },
362 { 0x2a9, "PICA_REG_GS_PROG_SWIZZLE_DATA3" },
363 { 0x2aa, "PICA_REG_GS_PROG_SWIZZLE_DATA4" },
364 { 0x2ab, "PICA_REG_GS_PROG_SWIZZLE_DATA5" },
365 { 0x2ac, "PICA_REG_GS_PROG_SWIZZLE_DATA6" },
366 { 0x2ad, "PICA_REG_GS_PROG_SWIZZLE_DATA7" },
367 { 0x2b0, "PICA_REG_VS_BOOL" },
368 { 0x2b1, "PICA_REG_VS_INT0" },
369 { 0x2b2, "PICA_REG_VS_INT1" },
370 { 0x2b3, "PICA_REG_VS_INT2" },
371 { 0x2b4, "PICA_REG_VS_INT3" },
372 { 0x2b9, "PICA_REG_VS_ATTR_NUM0" },
373 { 0x2ba, "PICA_REG_VS_START_ADDR" },
374 { 0x2bb, "PICA_REG_VS_ATTR_IN_REG_MAP0" },
375 { 0x2bc, "PICA_REG_VS_ATTR_IN_REG_MAP1" },
376 { 0x2bd, "PICA_REG_VS_OUT_REG_MASK" },
377 { 0x2bf, "PICA_REG_VS_PROG_RENEWAL_END" },
378 { 0x2c0, "PICA_REG_VS_FLOAT_ADDR" },
379 { 0x2c1, "PICA_REG_VS_FLOAT_DATA1" },
380 { 0x2c2, "PICA_REG_VS_FLOAT_DATA2" },
381 { 0x2c3, "PICA_REG_VS_FLOAT_DATA3" },
382 { 0x2c4, "PICA_REG_VS_FLOAT_DATA4" },
383 { 0x2c5, "PICA_REG_VS_FLOAT_DATA5" },
384 { 0x2c6, "PICA_REG_VS_FLOAT_DATA6" },
385 { 0x2c7, "PICA_REG_VS_FLOAT_DATA7" },
386 { 0x2c8, "PICA_REG_VS_FLOAT_DATA8" },
387 { 0x2cb, "PICA_REG_VS_PROG_ADDR" },
388 { 0x2cc, "PICA_REG_VS_PROG_DATA0" },
389 { 0x2cd, "PICA_REG_VS_PROG_DATA1" },
390 { 0x2ce, "PICA_REG_VS_PROG_DATA2" },
391 { 0x2cf, "PICA_REG_VS_PROG_DATA3" },
392 { 0x2d0, "PICA_REG_VS_PROG_DATA4" },
393 { 0x2d1, "PICA_REG_VS_PROG_DATA5" },
394 { 0x2d2, "PICA_REG_VS_PROG_DATA6" },
395 { 0x2d3, "PICA_REG_VS_PROG_DATA7" },
396 { 0x2d5, "PICA_REG_VS_PROG_SWIZZLE_ADDR" },
397 { 0x2d6, "PICA_REG_VS_PROG_SWIZZLE_DATA0" },
398 { 0x2d7, "PICA_REG_VS_PROG_SWIZZLE_DATA1" },
399 { 0x2d8, "PICA_REG_VS_PROG_SWIZZLE_DATA2" },
400 { 0x2d9, "PICA_REG_VS_PROG_SWIZZLE_DATA3" },
401 { 0x2da, "PICA_REG_VS_PROG_SWIZZLE_DATA4" },
402 { 0x2db, "PICA_REG_VS_PROG_SWIZZLE_DATA5" },
403 { 0x2dc, "PICA_REG_VS_PROG_SWIZZLE_DATA6" },
404 { 0x2dd, "PICA_REG_VS_PROG_SWIZZLE_DATA7" },
405 };
406 #endif
407
408 } // namespace {anonymous}
409
CmdCache()410 CmdCache::CmdCache()
411 : m_CmdBuffer(NULL),
412 m_CmdBufferSize(0),
413 m_CmdMaxBufferSize(0),
414 m_IsCopy(false)
415 {
416 }
417
418 void
Init(void * buffer,u32 size,bool isCopy)419 CmdCache::Init(
420 void* buffer,
421 u32 size,
422 bool isCopy
423 )
424 {
425 NW_ASSERT(ut::RoundDown(size, 8) == size);
426
427 m_CmdBuffer = static_cast<u8*>(ut::RoundUp(buffer, 4));
428 void *const bufferEnd = AddOffsetToPtr(buffer, size);
429 m_CmdMaxBufferSize = RoundDown(GetOffsetFromPtr(m_CmdBuffer, bufferEnd), 8);
430 m_IsCopy = isCopy;
431
432 Clear();
433 }
434
435 void
Use() const436 CmdCache::Use() const
437 {
438 #if defined(NW_PLATFORM_CTR)
439 //nngxUseSavedCmdlist(m_CmdListID, 0, m_CmdBufferSize, m_RequestId, m_RequestSize, 0, m_IsCopy ? GL_TRUE: GL_FALSE);
440 nngxAdd3DCommand(m_CmdBuffer, m_CmdBufferSize, m_IsCopy ? GL_TRUE: GL_FALSE);
441 #endif
442 NW_GL_ASSERT();
443 }
444
445 void
Add(const u32 * command,u32 size)446 CmdCache::Add(
447 const u32* command,
448 u32 size
449 )
450 {
451 NW_ASSERT(m_CmdBuffer != NULL);
452 NW_ASSERT(static_cast<GLsizei>(size) + m_CmdBufferSize <= m_CmdMaxBufferSize);
453
454 std::memcpy(m_CmdBuffer + m_CmdBufferSize,
455 command,
456 size);
457
458 m_CmdBufferSize += size;
459 }
460
461 void
RoundUp(u8 align)462 CmdCache::RoundUp(u8 align)
463 {
464 NW_ASSERT(m_CmdBuffer != NULL);
465
466 const GLsizei alignedBufferSize = ut::RoundUp(m_CmdBufferSize, align);
467 NW_ASSERT(alignedBufferSize <= m_CmdMaxBufferSize);
468
469 std::memset(m_CmdBuffer + m_CmdBufferSize, 0, alignedBufferSize - m_CmdBufferSize);
470 m_CmdBufferSize = alignedBufferSize;
471 }
472
473 #if !defined(NW_RELEASE)
474 void
DumpCommon(const void * from,const void * to,bool asF32,bool showMnemonic)475 CmdCache::DumpCommon(
476 const void* from,
477 const void* to,
478 bool asF32,
479 bool showMnemonic )
480 {
481 int dataCount = 0;
482
483 const u8* fromPtr = (const u8 *) from;
484 const u8* toPtr = (const u8 *) to;
485
486 for (; fromPtr < toPtr; fromPtr += 8)
487 {
488 const u32 *const command = reinterpret_cast<const u32*>(fromPtr);
489
490 if (showMnemonic)
491 {
492 if (dataCount <= 0)
493 {
494 // コマンドヘッダを解析
495 const u32 address = internal::GetBits(command[1], 0, 16);
496 dataCount = static_cast<int>(internal::GetBits(command[1], 20, 7));
497 const bool seq = internal::TestBit(command[1], 31);
498
499 u32 addressEnd = address + 1;
500 if (seq && dataCount > 0)
501 {
502 addressEnd = address + dataCount + 1;
503 }
504
505 const u32 num = sizeof(s_PicaRegMnemonic) / sizeof(s_PicaRegMnemonic[0]);
506 bool shown = false;
507 for (u32 i = 0; i < num; ++i)
508 {
509 if ( address <= s_PicaRegMnemonic[i].address &&
510 s_PicaRegMnemonic[i].address < addressEnd )
511 {
512 shown = true;
513 NN_LOG("// (0x%03x) %s\n",
514 s_PicaRegMnemonic[i].address,
515 s_PicaRegMnemonic[i].mnemonic);
516 }
517 }
518
519 if (! shown)
520 {
521 NN_LOG("// (0x%03x) ???\n", address);
522 }
523 }
524 else
525 {
526 dataCount -= 2;
527 }
528 }
529
530 if (asF32)
531 {
532 NN_LOG("%f, %f,\n",
533 math::U32AsF32(command[0]),
534 math::U32AsF32(command[1]));
535 }
536 else
537 {
538 NN_LOG("0x%08x, 0x%08x,\n",
539 command[0],
540 command[1]);
541 }
542 }
543 }
544 #endif
545
546 #if !defined(NW_RELEASE)
547 void
Dump(bool asF32,bool showMnemonic) const548 CmdCache::Dump(
549 bool asF32,
550 bool showMnemonic
551 ) const
552 {
553 NN_LOG("--- 0x%x %4d ---\n", m_CmdBuffer, m_CmdBufferSize);
554 DumpCommon(m_CmdBuffer, m_CmdBuffer + m_CmdBufferSize, asF32, showMnemonic);
555 NN_LOG("--- 0x%x %4d ---\n", m_CmdBuffer, m_CmdBufferSize);
556 }
557 #endif // #if !defined(NW_RELEASE)
558
559 #if !defined(NW_RELEASE)
560 void
Dump(const void * from,const void * to,bool asF32,bool showMnemonic)561 CmdCache::Dump(
562 const void* from,
563 const void* to,
564 bool asF32,
565 bool showMnemonic )
566 {
567 NN_LOG("--- from 0x%p to 0x%p ---\n", from, to);
568 DumpCommon(from, to, asF32, showMnemonic);
569 NN_LOG("--- from 0x%p to 0x%p ---\n", from, to);
570 }
571 #endif // #if !defined(NW_RELEASE)
572
573 } // namespace internal
574 } // namespace ut
575 } // namespace nw
576