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Searched refs:r1 (Results 1 – 25 of 40) sorted by relevance

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/TwlSDK-5.1.0/build/libraries/os/common/src/
Dos_context.c56 ands r1, newpc, #1 in OS_InitContext()
57 movne r1, #HW_PSR_SYS_MODE|HW_PSR_THUMB_STATE in OS_InitContext()
58 moveq r1, #HW_PSR_SYS_MODE|HW_PSR_ARM_STATE in OS_InitContext()
59 str r1, [ context, #OS_CONTEXT_CPSR ] in OS_InitContext()
62 mov r1, #0 in OS_InitContext()
63 str r1, [ context, #OS_CONTEXT_R0 ] in OS_InitContext()
64 str r1, [ context, #OS_CONTEXT_R1 ] in OS_InitContext()
65 str r1, [ context, #OS_CONTEXT_R2 ] in OS_InitContext()
66 str r1, [ context, #OS_CONTEXT_R3 ] in OS_InitContext()
67 str r1, [ context, #OS_CONTEXT_R4 ] in OS_InitContext()
[all …]
Dos_irqHandler_inTCM.c55 ldr r1, [ r12, #REG_IME_ADDR - REG_IE_ADDR ] // r1: IME in OS_IrqHandler()
58 cmp r1, #0 in OS_IrqHandler()
66 ldmia r12, { r1-r2 } // r1: IE, r2: IF in OS_IrqHandler()
67 ands r1, r1, r2 // r1: IE & IF in OS_IrqHandler()
84 @1: clz r0, r1 // Count zero of high bit in OS_IrqHandler()
85 bics r1, r1, r3, LSR r0 in OS_IrqHandler()
89 mov r1, r3, LSR r0 in OS_IrqHandler()
90 str r1, [ r12, #REG_IF_ADDR - REG_IE_ADDR ] in OS_IrqHandler()
100 @1: ands r2, r1, r3, LSL r0 // Count zero of high bit in OS_IrqHandler()
113 ldr r1, =OS_IRQTable in OS_IrqHandler()
[all …]
Dos_irqHandler.c72 ldr r1, [ r12, #REG_IME_ADDR - REG_IE_ADDR ] // r1: IME in OS_IrqHandler()
75 cmp r1, #0 in OS_IrqHandler()
79 ldmia r12, { r1-r2 } // r1: IE, r2: IF in OS_IrqHandler()
80 ands r1, r1, r2 // r1: IE & IF in OS_IrqHandler()
93 @1: clz r0, r1 // Count zero of high bit in OS_IrqHandler()
94 bics r1, r1, r3, LSR r0 in OS_IrqHandler()
98 mov r1, r3, LSR r0 in OS_IrqHandler()
99 str r1, [ r12, #REG_IF_ADDR - REG_IE_ADDR ] in OS_IrqHandler()
109 @1: ands r2, r1, r3, LSL r0 // Count zero of high bit in OS_IrqHandler()
122 ldr r1, =OS_IRQTable in OS_IrqHandler()
[all …]
Dos_exception.c176 ldr r1, [r0, #4] in OSi_DebuggerExceptionHook()
178 tst r1, #0x20 in OSi_DebuggerExceptionHook()
183 ldr r1, =0x0000EFFF in OSi_DebuggerExceptionHook()
184 cmp r0, r1 in OSi_DebuggerExceptionHook()
186 ldr r1, =0x0000DEFE in OSi_DebuggerExceptionHook()
187 cmp r0, r1 in OSi_DebuggerExceptionHook()
189 ldr r1, =0x0000BE00 in OSi_DebuggerExceptionHook()
190 cmp r0, r1 in OSi_DebuggerExceptionHook()
196 ldr r1, =0xE7FFFFFF in OSi_DebuggerExceptionHook()
197 cmp r0, r1 in OSi_DebuggerExceptionHook()
[all …]
Dos_reset.c205 ldr r1, =OSi_TCM_REGION_BASE_MASK in OSi_GetDTCMAddress()
206 and r0, r0, r1 in OSi_GetDTCMAddress()
384 ldr r1, =OSi_HW_DTCM in OSi_DoBoot()
385 add r1, r1, #0x3fc0 in OSi_DoBoot()
386 add r1, r1, #HW_DTCM_SYSRV_OFS_INTR_VECTOR in OSi_DoBoot()
388 str r0, [r1, #0] in OSi_DoBoot()
391 ldr r1, =REG_SUBPINTF_ADDR in OSi_DoBoot()
393 ldrh r0, [r1] in OSi_DoBoot()
398 strh r0, [r1] // mainp status == 1 in OSi_DoBoot()
405 …ldr r1, =HW_BIOS_EXCP_STACK_MAIN // clear system area. (exception, arena, DMA clear buf… in OSi_DoBoot()
[all …]
Dos_callTrace.c72 mov r1, #1 in OS_EnableCallTrace()
73 strh r1, [ r2, #OSCallTraceInfo.enable ] in OS_EnableCallTrace()
100 mov r1, #0 in OS_DisableCallTrace()
101 strh r1, [ r2, #OSCallTraceInfo.enable ] in OS_DisableCallTrace()
122 mov r1, r0 in OS_RestoreCallTrace()
124 cmp r1, #0 in OS_RestoreCallTrace()
127 ldrh r2, [ r1, #OSCallTraceInfo.enable ] in OS_RestoreCallTrace()
128 strh r0, [ r1, #OSCallTraceInfo.enable ] in OS_RestoreCallTrace()
279 p->r1 = 0; in OSi_SetCallTraceEntry()
351 stmfd sp!, {r1-r3} in __PROFILE_ENTRY()
[all …]
Dos_system.c42 bic r1, r0, #HW_PSR_IRQ_DISABLE in OS_EnableInterrupts()
43 msr cpsr_c, r1 in OS_EnableInterrupts()
62 orr r1, r0, #HW_PSR_IRQ_DISABLE in OS_DisableInterrupts()
63 msr cpsr_c, r1 in OS_DisableInterrupts()
81 mrs r1, cpsr in OS_RestoreInterrupts()
82 bic r2, r1, #HW_PSR_IRQ_DISABLE in OS_RestoreInterrupts()
85 and r0, r1, #HW_PSR_IRQ_DISABLE in OS_RestoreInterrupts()
106 bic r1, r0, #HW_PSR_IRQ_FIQ_DISABLE in OS_EnableInterrupts_IrqAndFiq()
107 msr cpsr_c, r1 in OS_EnableInterrupts_IrqAndFiq()
126 orr r1, r0, #HW_PSR_IRQ_FIQ_DISABLE in OS_DisableInterrupts_IrqAndFiq()
[all …]
Dos_functionCost.c68 mov r1, #1 in OS_EnableFunctionCost()
69 strh r1, [ r2, #OSFunctionCostInfo.enable ] in OS_EnableFunctionCost()
96 mov r1, #0 in OS_DisableFunctionCost()
97 strh r1, [ r2, #OSFunctionCostInfo.enable ] in OS_DisableFunctionCost()
119 mov r1, r0 in OS_RestoreFunctionCost()
121 cmp r1, #0 in OS_RestoreFunctionCost()
124 ldrh r2, [ r1, #OSFunctionCostInfo.enable ] in OS_RestoreFunctionCost()
125 strh r0, [ r1, #OSFunctionCostInfo.enable ] in OS_RestoreFunctionCost()
338 stmfd sp!, {r1-r4, lr} in __PROFILE_ENTRY()
342 orr r1, r4, #HW_PSR_IRQ_DISABLE in __PROFILE_ENTRY()
[all …]
/TwlSDK-5.1.0/build/libraries/os/ARM9/src/
Dos_cache.c40 mrc p15, 0, r1, c1, c0, 0 in DC_Enable()
41 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Enable()
43 orr r1, r1, #HW_C1_DCACHE_ENABLE in DC_Enable()
44 mcr p15, 0, r1, c1, c0, 0 in DC_Enable()
59 mrc p15, 0, r1, c1, c0, 0 in DC_Disable()
60 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Disable()
62 bic r1, r1, #HW_C1_DCACHE_ENABLE in DC_Disable()
63 mcr p15, 0, r1, c1, c0, 0 in DC_Disable()
83 mrc p15, 0, r1, c1, c0, 0 in DC_Restore()
84 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Restore()
[all …]
Dos_protectionRegion.c40 mrc p15, 0, r1, c2, c0, 1 in OS_EnableICacheForProtectionRegion()
41 orr r1, r1, r0 in OS_EnableICacheForProtectionRegion()
42 mcr p15, 0, r1, c2, c0, 1 in OS_EnableICacheForProtectionRegion()
49 mrc p15, 0, r1, c2, c0, 1 in OS_DisableICacheForProtectionRegion()
50 bic r1, r1, r0 in OS_DisableICacheForProtectionRegion()
51 mcr p15, 0, r1, c2, c0, 1 in OS_DisableICacheForProtectionRegion()
106 orr r2, r2, r1 in OS_SetIPermissionsForProtectionRegion()
152 mrc p15, 0, r1, c2, c0, 0 in OS_EnableDCacheForProtectionRegion()
153 orr r1, r1, r0 in OS_EnableDCacheForProtectionRegion()
154 mcr p15, 0, r1, c2, c0, 0 in OS_EnableDCacheForProtectionRegion()
[all …]
Dos_tcm.c137 ldr r1, =HW_C9_TCMR_BASE_MASK | HW_C9_TCMR_SIZE_MASK in OS_SetDTCMParam()
138 and r0, r0, r1 in OS_SetDTCMParam()
155 ldr r1, =HW_C9_TCMR_BASE_MASK | HW_C9_TCMR_SIZE_MASK in OS_GetDTCMParam()
156 and r0, r0, r1 in OS_GetDTCMParam()
180 ldr r1, =OSi_TCM_REGION_BASE_MASK in OS_SetDTCMAddress()
181 and r0, r0, r1 in OS_SetDTCMAddress()
203 ldr r1, =OSi_TCM_REGION_BASE_MASK in OS_GetDTCMAddress()
204 and r0, r0, r1 in OS_GetDTCMAddress()
/TwlSDK-5.1.0/build/libraries/init/ARM9.TWL/src/
Dcrt0.FLX.c222 ldr r1, =HW_PXI_SIGNAL_PARAM_ARM9 in _start()
226 ldr r1, =HW_INIT_LOCK_BUF in _start()
231 ldr r1, =HW_WM_BOOT_BUF in _start()
232 ldrh r2, [r1, #OSBootInfo.boot_type] in _start()
235 streqh r2, [r1, #OSBootInfo.boot_type] in _start()
238 ldr r1, =microcode_ShakeHand in _start()
241 @001: ldr r0, [r1], #4 in _start()
248 mov r1, #BOOT_SYNC_PHASE_1 in _start()
249 strh r1, [r0] in _start()
251 ldr r1, =HW_BOOT_SHAKEHAND_7 in _start()
[all …]
/TwlSDK-5.1.0/build/libraries/mi/common/src/
Dmi_memory.c109 strlth r0, [r1, r3] // *((vu16 *)(destp + n)) = data in MIi_CpuClear16()
141 strlth r3, [r1, r12] in MIi_CpuCopy16()
174 strlth r3, [r1, #0] in MIi_CpuSend16()
200 strlth r3, [r1, r12] in MIi_CpuRecv16()
226 strlth r3, [r1] in MIi_CpuPipe16()
246 mov r12, r1 // r12: destEndp = destp in CpuCopy16Reverse()
248 add r1, r1, r2 // r1: destp += size in CpuCopy16Reverse()
251 cmp r12, r1 // while (destEndp < destp) in CpuCopy16Reverse()
253 strlth r2, [r1, #-2]! in CpuCopy16Reverse()
346 add r12, r1, r2 // r12: destEndp = destp + size in MIi_CpuClear32()
[all …]
Dmi_uncompress.c100 str r14, [r1], #4 // *destp++ = destBak; in MI_UnpackBits()
163 … swpb r6, r6, [r1] // r1: *destp++; (Byte-writing countermeasure) in MI_UncompressLZ8()
164 add r1, r1, #1 in MI_UncompressLZ8()
200 @24: ldrb r5, [r1, -r12] // *destp++ = destp[-offset] in MI_UncompressLZ8()
201 swpb r5, r5, [r1] // (Byte-writing countermeasure) in MI_UncompressLZ8()
202 add r1, r1, #1 in MI_UncompressLZ8()
275 streqh r3, [r1], #2 // *destp++ = destTmp; in MI_UncompressLZ16()
323 ldrh r9, [r1, -r8] in MI_UncompressLZ16()
333 streqh r3, [r1], #2 // *destp++ = destTmp; in MI_UncompressLZ16()
450 streq r3, [r1], #4 // *destp++ = destTmp; in MI_UncompressHuffman()
[all …]
/TwlSDK-5.1.0/build/libraries/cp/common/src/
Dcp_context.c36 ldr r1, =REG_DIV_NUMER_ADDR in CP_SaveContext()
38 ldmia r1, {r2-r4,r12} in CP_SaveContext()
40 ldrh r12, [r1, #REG_DIVCNT_OFFSET - REG_DIV_NUMER_OFFSET] in CP_SaveContext()
42 add r1, r1, #REG_SQRT_PARAM_OFFSET - REG_DIV_NUMER_OFFSET in CP_SaveContext()
43 ldmia r1, {r2-r3} in CP_SaveContext()
47 ldrh r2, [r1, #REG_SQRTCNT_OFFSET - REG_SQRT_PARAM_OFFSET] in CP_SaveContext()
69 ldr r1, =REG_DIV_NUMER_ADDR in CPi_RestoreContext()
71 stmia r1, {r2-r4,r12} in CPi_RestoreContext()
75 strh r2, [r1, #REG_DIVCNT_OFFSET - REG_DIV_NUMER_OFFSET] in CPi_RestoreContext()
76 strh r3, [r1, #REG_SQRTCNT_OFFSET - REG_DIV_NUMER_OFFSET] in CPi_RestoreContext()
[all …]
/TwlSDK-5.1.0/build/libraries/math/common/src/
Dqsort.c93 mov r1, right in MATH_QSort()
102 ldrb r1, [left] in MATH_QSort()
104 swpb r1, r1, [right] in MATH_QSort()
106 strb r1, [left], #1 in MATH_QSort()
111 ldr r1, [left] in MATH_QSort()
113 swp r1, r1, [right] in MATH_QSort()
115 str r1, [left], #4 in MATH_QSort()
136 ldrb r1, [r2] in MATH_QSort()
138 swpb r1, r1, [r3] in MATH_QSort()
140 strb r1, [r2], #1 in MATH_QSort()
[all …]
/TwlSDK-5.1.0/build/libraries/gx/ARM9/src/
Dgxasm.c24 stmia r1, {r2,r3,r12} in GX_SendFifo48B()
26 stmia r1, {r2,r3,r12} in GX_SendFifo48B()
28 stmia r1, {r2,r3,r12} in GX_SendFifo48B()
30 stmia r1, {r2,r3,r12} in GX_SendFifo48B()
40 stmia r1, {r2-r8, r12} in GX_SendFifo64B()
42 stmia r1, {r2-r8, r12} in GX_SendFifo64B()
53 stmia r1, {r2-r8, r12} in GX_SendFifo128B()
55 stmia r1, {r2-r8, r12} in GX_SendFifo128B()
57 stmia r1, {r2-r8, r12} in GX_SendFifo128B()
59 stmia r1, {r2-r8, r12} in GX_SendFifo128B()
Dg3x.c767 mov r1, #0 // r0-r3, r12 need not be saved. in GXi_NopClearFifo128_()
774 stmia r0, {r1-r3, r12} // 0 - 15 in GXi_NopClearFifo128_()
775 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
776 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
777 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
779 stmia r0, {r1-r3, r12} // 16 - 31 in GXi_NopClearFifo128_()
780 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
781 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
782 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
784 stmia r0, {r1-r3, r12} // 32 - 47 in GXi_NopClearFifo128_()
[all …]
/TwlSDK-5.1.0/build/demos/os/exceptionDisplay-2/src/
Dmain.c82 cmp r1,#0 in _s32_div_f()
86 ldr r11, [r1,#0] in _s32_div_f()
88 eor r4,r0,r1 in _s32_div_f()
93 cmp r1,#0 in _s32_div_f()
94 rsblt r1,r1,#0 in _s32_div_f()
99 rsbne r1,r1,#0 in _s32_div_f()
/TwlSDK-5.1.0/build/libraries/init/ARM9/src/
Dcrt0.c117 ldr r1, =SDK_IRQ_STACKSIZE in _start()
118 sub r1, r0, r1 in _start()
121 sub sp, r1, #4 // 4 bytes for stack check code in _start()
128 ldr r1, =INITi_HW_DTCM in _start()
134 ldr r1, =HW_PLTT in _start()
140 ldr r1, =HW_OAM in _start()
145 ldr r1, =_start_ModuleParams in _start()
146 ldr r0, [r1, #20] // r0 = bottom of compressed data in _start()
152 ldr r1, [r0, #12] // BSS segment start in _start()
154 mov r3, r1 // For next step (flush bss) in _start()
[all …]
/TwlSDK-5.1.0/build/libraries/math/common/src/asm/
Dsha1.s78 ; r1, r8 : w[t], context->block[t] �̃A�h���X
79 ; r0,r1,r2,r8,r10 : not use
82 mov r1, r12
111 stmia r1!, {r4, r5, r6, r7}
129 ldr r1, [r8]
135 eor r1, r1, lr
137 eor r1, r1, r3
138 eor r1, r1, r2
140 mov r4, r1, ror #31
143 ldr r1, [r8, #4]
[all …]
/TwlSDK-5.1.0/build/libraries/fx/common/src/
Dfx_mtx43.c31 mov r1, #0 in MTX_Identity43_()
32 stmia r0!, {r1, r3} in MTX_Identity43_()
34 stmia r0!, {r1, r3} in MTX_Identity43_()
36 stmia r0!, {r1, r3} in MTX_Identity43_()
47 stmia r1!, {r2-r4, r12} in MTX_Copy43To44_()
49 stmia r1!, {r2-r4, r12} in MTX_Copy43To44_()
51 stmia r1!, {r2-r4, r12} in MTX_Copy43To44_()
54 stmia r1!, {r2-r4, r12} in MTX_Copy43To44_()
66 stmia r1!, {r2, r5, r8} in MTX_Transpose43_()
67 stmia r1!, {r3, r6, r9} in MTX_Transpose43_()
[all …]
Dfx_mtx33.c34 mov r1, #0 in MTX_Identity33_()
35 stmia r0!, {r1, r3} in MTX_Identity33_()
37 stmia r0!, {r1, r3} in MTX_Identity33_()
44 stmia r1!, {r2-r3, r12} in MTX_Copy33To43_()
46 stmia r1!, {r2-r3, r12} in MTX_Copy33To43_()
48 stmia r1!, {r2-r3, r12} in MTX_Copy33To43_()
51 str r2, [r1, #0] in MTX_Copy33To43_()
52 str r2, [r1, #4] in MTX_Copy33To43_()
53 str r2, [r1, #8] in MTX_Copy33To43_()
65 stmia r1!, {r2-r4, r12} in MTX_Copy33To44_()
[all …]
Dfx_mtx44.c35 mov r1, #0 in MTX_Identity44_()
36 stmia r0!, {r1,r3} in MTX_Identity44_()
37 stmia r0!, {r1,r2,r3} in MTX_Identity44_()
38 stmia r0!, {r1,r3} in MTX_Identity44_()
39 stmia r0!, {r1,r2,r3} in MTX_Identity44_()
40 stmia r0!, {r1,r3} in MTX_Identity44_()
41 stmia r0!, {r1,r2} in MTX_Identity44_()
50 stmia r1!, {r2-r3, r12} in MTX_Copy44To33_()
54 stmia r1!, {r2-r3, r12} in MTX_Copy44To33_()
58 stmia r1!, {r2-r3, r12} in MTX_Copy44To33_()
[all …]
Dfx_mtx22.c31 mov r1, #0 in MTX_Identity22_()
35 stmia r0!, {r1, r2} in MTX_Identity22_()
44 stmia r1!, {r2, r4} in MTX_Transpose22_()
45 stmia r1!, {r3, r12} in MTX_Transpose22_()
54 stmia r0!, {r1} in MTX_Scale22_()
55 mov r1, #0 in MTX_Scale22_()
58 stmia r0!, {r1, r2} in MTX_Scale22_()
66 str r1, [r0, #4] in MTX_Rot22_()
67 neg r1, r1 in MTX_Rot22_()
68 str r1, [r0, #8] in MTX_Rot22_()

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