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Searched refs:MI_DMA_TIMING_IMM (Results 1 – 4 of 4) sorted by relevance

/TwlSDK-5.1.0/build/libraries/mi/common/include/
Ddma_red.h106 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
115 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
155 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
162 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
307 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
/TwlSDK-5.1.0/build/libraries/os/common/include/
Ddma_red.h106 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
115 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
155 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
162 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
307 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
/TwlSDK-5.1.0/build/libraries/init/common/include/
Ddma_red.h106 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
115 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
155 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
162 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
307 MI_DMA_ENABLE | MI_DMA_TIMING_IMM | \
/TwlSDK-5.1.0/include/nitro/mi/
Ddma.h53 # define MI_DMA_TIMING_IMM (0UL << REG_MI_DMA0CNT_MODE_SHIFT) // start immediately macro
65 # define MI_DMA_TIMING_IMM (0UL << REG_MI_DMA0CNT_TIMING_SHIFT) // start immediately
117 #define MI_DMA_IMM16ENABLE ( MI_DMA_ENABLE | MI_DMA_TIMING_IMM | MI_DMA_16BIT_BUS )
118 #define MI_DMA_IMM32ENABLE ( MI_DMA_ENABLE | MI_DMA_TIMING_IMM | MI_DMA_32BIT_BUS )
119 #define MI_DMA_IMM16DISABLE ( MI_DMA_DISABLE | MI_DMA_TIMING_IMM | MI_DMA_16BIT_BUS )
120 #define MI_DMA_IMM32DISABLE ( MI_DMA_DISABLE | MI_DMA_TIMING_IMM | MI_DMA_32BIT_BUS )