Searched refs:REGType8v (Results 1 – 12 of 12) sorted by relevance
144 REGType8v *reg = (REGType8v *)(REG_SNDCAP0CNT_ADDR + capture); in SND_StartCapture()174 (*(REGType8v *)(REG_SNDCAP0CNT_ADDR + capture)) = 0; in SND_StopCapture()
211 *((REGType8v *)(REG_SOUND0CNT_8_ADDR + SND_CHANNEL_REG_OFFSET(chNo))) in SND_StartChannel()
38 #define reg_CFG_A9ROM (*( REGType8v *) REG_A9ROM_ADDR)50 #define reg_CFG_DSP_RST (*( REGType8v *) REG_DSP_RST_ADDR)56 #define reg_CFG_DS_MDFY (*( REGType8v *) REG_DS_MDFY_ADDR)62 #define reg_CFG_DS_EX (*( REGType8v *) REG_DS_EX_ADDR)
98 #define reg_GX_VRAMCNT_A (*( REGType8v *) REG_VRAMCNT_A_ADDR)104 #define reg_GX_VRAMCNT_B (*( REGType8v *) REG_VRAMCNT_B_ADDR)110 #define reg_GX_VRAMCNT_C (*( REGType8v *) REG_VRAMCNT_C_ADDR)116 #define reg_GX_VRAMCNT_D (*( REGType8v *) REG_VRAMCNT_D_ADDR)128 #define reg_GX_VRAMCNT_E (*( REGType8v *) REG_VRAMCNT_E_ADDR)134 #define reg_GX_VRAMCNT_F (*( REGType8v *) REG_VRAMCNT_F_ADDR)140 #define reg_GX_VRAMCNT_G (*( REGType8v *) REG_VRAMCNT_G_ADDR)146 #define reg_GX_VRAMCNT_WRAM (*( REGType8v *) REG_VRAMCNT_WRAM_ADDR)158 #define reg_GX_VRAMCNT_H (*( REGType8v *) REG_VRAMCNT_H_ADDR)164 #define reg_GX_VRAMCNT_I (*( REGType8v *) REG_VRAMCNT_I_ADDR)
470 #define reg_MI_MBK_A0 (*( REGType8v *) REG_MBK_A0_ADDR)476 #define reg_MI_MBK_A1 (*( REGType8v *) REG_MBK_A1_ADDR)482 #define reg_MI_MBK_A2 (*( REGType8v *) REG_MBK_A2_ADDR)488 #define reg_MI_MBK_A3 (*( REGType8v *) REG_MBK_A3_ADDR)500 #define reg_MI_MBK_B0 (*( REGType8v *) REG_MBK_B0_ADDR)506 #define reg_MI_MBK_B1 (*( REGType8v *) REG_MBK_B1_ADDR)512 #define reg_MI_MBK_B2 (*( REGType8v *) REG_MBK_B2_ADDR)518 #define reg_MI_MBK_B3 (*( REGType8v *) REG_MBK_B3_ADDR)530 #define reg_MI_MBK_B4 (*( REGType8v *) REG_MBK_B4_ADDR)536 #define reg_MI_MBK_B5 (*( REGType8v *) REG_MBK_B5_ADDR)[all …]
38 #define reg_SCFG_A9ROM (*(const REGType8v *) REG_A9ROM_ADDR)
74 typedef vu8 REGType8v; typedef
79 typedef vu8 REGType8v; typedef
272 return (MIWramProc)( *(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_MASTER_MASK_A ); in MI_GetWramBankMaster_A()277 return (MIWramProc)( *(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_MASTER_MASK_B ); in MI_GetWramBankMaster_B()282 return (MIWramProc)( *(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_MASTER_MASK_C ); in MI_GetWramBankMaster_C()324 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_OFFSET_MASK_A) >> MI_WRAM_O… in MI_GetWramBankOffset_A()329 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_OFFSET_MASK_B) >> MI_WRAM_O… in MI_GetWramBankOffset_B()334 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_OFFSET_MASK_C) >> MI_WRAM_O… in MI_GetWramBankOffset_C()363 …return (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_ENABLE_MASK_A)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_A()368 …return (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_ENABLE_MASK_B)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_B()373 …return (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_ENABLE_MASK_C)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_C()
41 #define reg_OS_EMU_CONSOLE_OUT (*((REGType8v *)REG_EMU_CONSOLE_OUT))