Home
last modified time | relevance | path

Searched refs:reg_G3X_GXSTAT (Results 1 – 7 of 7) sorted by relevance

/TwlSDK-5.4/include/nitro/gx/
Dg3x.h330 reg_G3X_GXSTAT = ((reg_G3X_GXSTAT & ~REG_G3X_GXSTAT_FI_MASK) | in G3X_SetFifoIntrCond()
390 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_SB_MASK) in G3X_IsMtxStackOverflow()
395 *overflow = (s32)(reg_G3X_GXSTAT & REG_G3X_GXSTAT_SE_MASK); in G3X_IsMtxStackOverflow()
446 return (s32)(reg_G3X_GXSTAT & REG_G3X_GXSTAT_B_MASK); in G3X_IsGeometryBusy()
461 reg_G3X_GXSTAT |= REG_G3X_GXSTAT_SE_MASK; in G3X_ResetMtxStackOverflow()
553 return (s32)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_FIFOCNT_MASK) >> REG_G3X_GXSTAT_FIFOCNT_SHIFT); in G3X_GetCommandFifoCount()
568 return (GXFifoStat)((reg_G3X_GXSTAT & (REG_G3X_GXSTAT_F_MASK | in G3X_GetCommandFifoStatus()
/TwlSDK-5.4/build/libraries/os/common/src/
Dos_entropy.c43 #ifdef reg_G3X_GXSTAT in OS_GetLowEntropyData()
44 buffer[2] ^= reg_G3X_GXSTAT; in OS_GetLowEntropyData()
/TwlSDK-5.4/build/libraries/gx/ARM9/src/
Dg3x.c73 reg_G3X_GXSTAT = 0; in G3X_Init()
596 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_SB_MASK) in G3X_GetMtxStackLevelPV()
602 *level = (s32)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_PV_MASK) >> REG_G3X_GXSTAT_PV_SHIFT); in G3X_GetMtxStackLevelPV()
622 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_SB_MASK) in G3X_GetMtxStackLevelPJ()
628 *level = (s32)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_PJ_MASK) >> REG_G3X_GXSTAT_PJ_SHIFT); in G3X_GetMtxStackLevelPJ()
668 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_TB_MASK) in G3X_GetBoxTestResult()
672 *in = (s32)(reg_G3X_GXSTAT & REG_G3X_GXSTAT_TR_MASK); in G3X_GetBoxTestResult()
693 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_TB_MASK) in G3X_GetPositionTestResult()
721 if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_TB_MASK) in G3X_GetVectorTestResult()
/TwlSDK-5.4/build/libraries/mi/common.TWL/src/
Dmi_ndma_gxcommand.c150 …MIi_GXNDmaParams.fifoCond = (GXFifoIntrCond)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_FI_MASK) >> REG_G3X_… in MI_SendNDmaGXCommandAsync()
/TwlSDK-5.4/build/libraries/mi/common/src/
Dmi_dma_gxcommand.c150 …MIi_GXDmaParams.fifoCond = (GXFifoIntrCond)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_FI_MASK) >> REG_G3X_G… in MI_SendGXCommandAsync()
/TwlSDK-5.4/include/nitro/hw/ARM9/
Dioreg_G3X.h596 #define reg_G3X_GXSTAT (*( REGType32v *) REG_GXSTAT_ADDR) macro
/TwlSDK-5.4/include/twl/hw/ARM9/
Dioreg_G3X.h596 #define reg_G3X_GXSTAT (*( REGType32v *) REG_GXSTAT_ADDR) macro