Searched refs:reg_G3X_DISP3DCNT (Results 1 – 5 of 5) sorted by relevance
196 reg_G3X_DISP3DCNT = (u16)((reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_THS_MASK | in G3X_SetShading()221 reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & in G3X_AlphaTest()228 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_ATE_MASK | in G3X_AlphaTest()250 reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & in G3X_AlphaBlend()256 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_ABE_MASK | in G3X_AlphaBlend()277 reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & in G3X_AntiAlias()283 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_AAE_MASK | in G3X_AntiAlias()304 reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & in G3X_EdgeMarking()310 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_EME_MASK | in G3X_EdgeMarking()414 return (reg_G3X_DISP3DCNT & REG_G3X_DISP3DCNT_RO_MASK); in G3X_IsLineBufferUnderflow()[all …]
72 reg_G3X_DISP3DCNT = 0; in G3X_Init()304 reg_G3X_DISP3DCNT = (u16)((reg_G3X_DISP3DCNT & in G3X_SetFog()315 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_FME_MASK in G3X_SetFog()
741 reg_G3X_DISP3DCNT = (u16)((reg_G3X_DISP3DCNT & in texOn_()748 reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_TME_MASK | in texOff_()843 reg_G3X_DISP3DCNT |= REG_G3X_DISP3DCNT_PRI_MASK; in clearImageOn_()848 reg_G3X_DISP3DCNT &= ~REG_G3X_DISP3DCNT_PRI_MASK; in clearImageOff_()
38 #define reg_G3X_DISP3DCNT (*( REGType16v *) REG_DISP3DCNT_ADDR) macro