Searched refs:reg_DSP_PSTS (Results 1 – 3 of 3) sorted by relevance
115 while ( reg_DSP_PSTS & REG_DSP_PSTS_PRST_MASK ) in DSP_ResetOnCore()132 while ( reg_DSP_PSTS & REG_DSP_PSTS_PRST_MASK ) in DSP_ResetOffCore()152 while ( reg_DSP_PSTS & REG_DSP_PSTS_PRST_MASK ) in DSP_ResetOffExCore()226 return (reg_DSP_PSTS & ((1 << dataNo) << REG_DSP_PSTS_RCOMIM_SHIFT)) ? FALSE : TRUE; in DSP_SendDataIsEmptyCore()241 return (reg_DSP_PSTS & ((1 << dataNo) << REG_DSP_PSTS_RRI_SHIFT)) ? TRUE : FALSE; in DSP_RecvDataIsReadyCore()340 while (reg_DSP_PSTS & REG_DSP_PSTS_WFFI_MASK) in DSP_SendFifoExCore()352 while (reg_DSP_PSTS & REG_DSP_PSTS_WFFI_MASK) in DSP_SendFifoExCore()413 while ((reg_DSP_PSTS & REG_DSP_PSTS_RFNEI_MASK) == 0) in DSP_RecvFifoExCore()423 while ((reg_DSP_PSTS & REG_DSP_PSTS_RFNEI_MASK) == 0) in DSP_RecvFifoExCore()533 return (reg_DSP_PSTS & REG_DSP_PSTS_PSEMI_MASK) >> REG_DSP_PSTS_PSEMI_SHIFT; in DSP_CheckSemaphoreRequestCore()
56 #define reg_DSP_PSTS (*(const REGType16v *) REG_PSTS_ADDR) macro
142 int ready = (reg_DSP_SEM | (((reg_DSP_PSTS >> REG_DSP_PSTS_RRI0_SHIFT) & 7) << 16)); in DSPi_MasterInterrupts()