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Searched refs:REGType16v (Results 1 – 25 of 29) sorted by relevance

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/TwlSDK-5.4/include/twl/hw/ARM9/
Dioreg_DSP.h38 #define reg_DSP_PDATA (*( REGType16v *) REG_PDATA_ADDR)
44 #define reg_DSP_PADR (*( REGType16v *) REG_PADR_ADDR)
50 #define reg_DSP_PCFG (*( REGType16v *) REG_PCFG_ADDR)
56 #define reg_DSP_PSTS (*(const REGType16v *) REG_PSTS_ADDR)
62 #define reg_DSP_PSEM (*( REGType16v *) REG_PSEM_ADDR)
68 #define reg_DSP_PMASK (*( REGType16v *) REG_PMASK_ADDR)
74 #define reg_DSP_PCLEAR (*( REGType16v *) REG_PCLEAR_ADDR)
80 #define reg_DSP_SEM (*(const REGType16v *) REG_SEM_ADDR)
86 #define reg_DSP_COM0 (*( REGType16v *) REG_COM0_ADDR)
92 #define reg_DSP_REP0 (*(const REGType16v *) REG_REP0_ADDR)
[all …]
Dioreg_G2.h38 #define reg_G2_BG0CNT (*( REGType16v *) REG_BG0CNT_ADDR)
44 #define reg_G2_BG1CNT (*( REGType16v *) REG_BG1CNT_ADDR)
50 #define reg_G2_BG2CNT (*( REGType16v *) REG_BG2CNT_ADDR)
56 #define reg_G2_BG3CNT (*( REGType16v *) REG_BG3CNT_ADDR)
68 #define reg_G2_BG0HOFS (*( REGType16v *) REG_BG0HOFS_ADDR)
74 #define reg_G2_BG0VOFS (*( REGType16v *) REG_BG0VOFS_ADDR)
86 #define reg_G2_BG1HOFS (*( REGType16v *) REG_BG1HOFS_ADDR)
92 #define reg_G2_BG1VOFS (*( REGType16v *) REG_BG1VOFS_ADDR)
104 #define reg_G2_BG2HOFS (*( REGType16v *) REG_BG2HOFS_ADDR)
110 #define reg_G2_BG2VOFS (*( REGType16v *) REG_BG2VOFS_ADDR)
[all …]
Dioreg_G2S.h38 #define reg_G2S_DB_BG0CNT (*( REGType16v *) REG_DB_BG0CNT_ADDR)
44 #define reg_G2S_DB_BG1CNT (*( REGType16v *) REG_DB_BG1CNT_ADDR)
50 #define reg_G2S_DB_BG2CNT (*( REGType16v *) REG_DB_BG2CNT_ADDR)
56 #define reg_G2S_DB_BG3CNT (*( REGType16v *) REG_DB_BG3CNT_ADDR)
68 #define reg_G2S_DB_BG0HOFS (*( REGType16v *) REG_DB_BG0HOFS_ADDR)
74 #define reg_G2S_DB_BG0VOFS (*( REGType16v *) REG_DB_BG0VOFS_ADDR)
86 #define reg_G2S_DB_BG1HOFS (*( REGType16v *) REG_DB_BG1HOFS_ADDR)
92 #define reg_G2S_DB_BG1VOFS (*( REGType16v *) REG_DB_BG1VOFS_ADDR)
104 #define reg_G2S_DB_BG2HOFS (*( REGType16v *) REG_DB_BG2HOFS_ADDR)
110 #define reg_G2S_DB_BG2VOFS (*( REGType16v *) REG_DB_BG2VOFS_ADDR)
[all …]
Dioreg_G3X.h38 #define reg_G3X_DISP3DCNT (*( REGType16v *) REG_DISP3DCNT_ADDR)
44 #define reg_G3X_RDLINES_COUNT (*(const REGType16v *) REG_RDLINES_COUNT…
56 #define reg_G3X_EDGE_COLOR_0_L (*( REGType16v *) REG_EDGE_COLOR_0_L_ADD…
62 #define reg_G3X_EDGE_COLOR_0_H (*( REGType16v *) REG_EDGE_COLOR_0_H_ADD…
74 #define reg_G3X_EDGE_COLOR_1_L (*( REGType16v *) REG_EDGE_COLOR_1_L_ADD…
80 #define reg_G3X_EDGE_COLOR_1_H (*( REGType16v *) REG_EDGE_COLOR_1_H_ADD…
92 #define reg_G3X_EDGE_COLOR_2_L (*( REGType16v *) REG_EDGE_COLOR_2_L_ADD…
98 #define reg_G3X_EDGE_COLOR_2_H (*( REGType16v *) REG_EDGE_COLOR_2_H_ADD…
110 #define reg_G3X_EDGE_COLOR_3_L (*( REGType16v *) REG_EDGE_COLOR_3_L_ADD…
116 #define reg_G3X_EDGE_COLOR_3_H (*( REGType16v *) REG_EDGE_COLOR_3_H_ADD…
[all …]
Dioreg_EXI.h44 #define reg_EXI_SIOCNT (*( REGType16v *) REG_SIOCNT_ADDR)
50 #define reg_EXI_SIOSEL (*( REGType16v *) REG_SIOSEL_ADDR)
Dioreg_OS.h38 #define reg_OS_TM0CNT_L (*( REGType16v *) REG_TM0CNT_L_ADDR)
44 #define reg_OS_TM0CNT_H (*( REGType16v *) REG_TM0CNT_H_ADDR)
50 #define reg_OS_TM1CNT_L (*( REGType16v *) REG_TM1CNT_L_ADDR)
56 #define reg_OS_TM1CNT_H (*( REGType16v *) REG_TM1CNT_H_ADDR)
62 #define reg_OS_TM2CNT_L (*( REGType16v *) REG_TM2CNT_L_ADDR)
68 #define reg_OS_TM2CNT_H (*( REGType16v *) REG_TM2CNT_H_ADDR)
74 #define reg_OS_TM3CNT_L (*( REGType16v *) REG_TM3CNT_L_ADDR)
80 #define reg_OS_TM3CNT_H (*( REGType16v *) REG_TM3CNT_H_ADDR)
86 #define reg_OS_IME (*( REGType16v *) REG_IME_ADDR)
104 #define reg_OS_PAUSE (*( REGType16v *) REG_PAUSE_ADDR)
Dioreg_PXI.h38 #define reg_PXI_SUBPINTF (*( REGType16v *) REG_SUBPINTF_ADDR)
44 #define reg_PXI_SUBP_FIFO_CNT (*( REGType16v *) REG_SUBP_FIFO_CNT_ADDR)
Dioreg_GX.h44 #define reg_GX_DISPSTAT (*( REGType16v *) REG_DISPSTAT_ADDR)
50 #define reg_GX_VCOUNT (*( REGType16v *) REG_VCOUNT_ADDR)
68 #define reg_GX_DISP_MMEM_FIFO_L (*( REGType16v *) REG_DISP_MMEM_FIFO_L_A…
74 #define reg_GX_DISP_MMEM_FIFO_H (*( REGType16v *) REG_DISP_MMEM_FIFO_H_A…
80 #define reg_GX_MASTER_BRIGHT (*( REGType16v *) REG_MASTER_BRIGHT_ADDR)
86 #define reg_GX_TVOUTCNT (*( REGType16v *) REG_TVOUTCNT_ADDR)
152 #define reg_GX_VRAM_HI_CNT (*( REGType16v *) REG_VRAM_HI_CNT_ADDR)
170 #define reg_GX_POWCNT (*( REGType16v *) REG_POWCNT_ADDR)
Dioreg_CP.h38 #define reg_CP_DIVCNT (*( REGType16v *) REG_DIVCNT_ADDR)
116 #define reg_CP_SQRTCNT (*( REGType16v *) REG_SQRTCNT_ADDR)
Dioreg_PAD.h38 #define reg_PAD_KEYINPUT (*(const REGType16v *) REG_KEYINPUT_ADDR)
44 #define reg_PAD_KEYCNT (*( REGType16v *) REG_KEYCNT_ADDR)
Dioreg_SCFG.h44 #define reg_SCFG_CLK (*( REGType16v *) REG_CLK_ADDR)
50 #define reg_SCFG_RST (*( REGType16v *) REG_RST_ADDR)
Dioreg_CAM.h38 #define reg_CAM_MCNT (*( REGType16v *) REG_MCNT_ADDR)
44 #define reg_CAM_CNT (*( REGType16v *) REG_CNT_ADDR)
/TwlSDK-5.4/include/nitro/hw/ARM9/
Dioreg_G2S.h38 #define reg_G2S_DB_BG0CNT (*( REGType16v *) REG_DB_BG0CNT_ADDR)
44 #define reg_G2S_DB_BG1CNT (*( REGType16v *) REG_DB_BG1CNT_ADDR)
50 #define reg_G2S_DB_BG2CNT (*( REGType16v *) REG_DB_BG2CNT_ADDR)
56 #define reg_G2S_DB_BG3CNT (*( REGType16v *) REG_DB_BG3CNT_ADDR)
68 #define reg_G2S_DB_BG0HOFS (*( REGType16v *) REG_DB_BG0HOFS_ADDR)
74 #define reg_G2S_DB_BG0VOFS (*( REGType16v *) REG_DB_BG0VOFS_ADDR)
86 #define reg_G2S_DB_BG1HOFS (*( REGType16v *) REG_DB_BG1HOFS_ADDR)
92 #define reg_G2S_DB_BG1VOFS (*( REGType16v *) REG_DB_BG1VOFS_ADDR)
104 #define reg_G2S_DB_BG2HOFS (*( REGType16v *) REG_DB_BG2HOFS_ADDR)
110 #define reg_G2S_DB_BG2VOFS (*( REGType16v *) REG_DB_BG2VOFS_ADDR)
[all …]
Dioreg_G2.h38 #define reg_G2_BG0CNT (*( REGType16v *) REG_BG0CNT_ADDR)
44 #define reg_G2_BG1CNT (*( REGType16v *) REG_BG1CNT_ADDR)
50 #define reg_G2_BG2CNT (*( REGType16v *) REG_BG2CNT_ADDR)
56 #define reg_G2_BG3CNT (*( REGType16v *) REG_BG3CNT_ADDR)
68 #define reg_G2_BG0HOFS (*( REGType16v *) REG_BG0HOFS_ADDR)
74 #define reg_G2_BG0VOFS (*( REGType16v *) REG_BG0VOFS_ADDR)
86 #define reg_G2_BG1HOFS (*( REGType16v *) REG_BG1HOFS_ADDR)
92 #define reg_G2_BG1VOFS (*( REGType16v *) REG_BG1VOFS_ADDR)
104 #define reg_G2_BG2HOFS (*( REGType16v *) REG_BG2HOFS_ADDR)
110 #define reg_G2_BG2VOFS (*( REGType16v *) REG_BG2VOFS_ADDR)
[all …]
Dioreg_G3X.h38 #define reg_G3X_DISP3DCNT (*( REGType16v *) REG_DISP3DCNT_ADDR)
44 #define reg_G3X_RDLINES_COUNT (*(const REGType16v *) REG_RDLINES_COUNT…
56 #define reg_G3X_EDGE_COLOR_0_L (*( REGType16v *) REG_EDGE_COLOR_0_L_ADD…
62 #define reg_G3X_EDGE_COLOR_0_H (*( REGType16v *) REG_EDGE_COLOR_0_H_ADD…
74 #define reg_G3X_EDGE_COLOR_1_L (*( REGType16v *) REG_EDGE_COLOR_1_L_ADD…
80 #define reg_G3X_EDGE_COLOR_1_H (*( REGType16v *) REG_EDGE_COLOR_1_H_ADD…
92 #define reg_G3X_EDGE_COLOR_2_L (*( REGType16v *) REG_EDGE_COLOR_2_L_ADD…
98 #define reg_G3X_EDGE_COLOR_2_H (*( REGType16v *) REG_EDGE_COLOR_2_H_ADD…
110 #define reg_G3X_EDGE_COLOR_3_L (*( REGType16v *) REG_EDGE_COLOR_3_L_ADD…
116 #define reg_G3X_EDGE_COLOR_3_H (*( REGType16v *) REG_EDGE_COLOR_3_H_ADD…
[all …]
Dioreg_OS.h38 #define reg_OS_TM0CNT_L (*( REGType16v *) REG_TM0CNT_L_ADDR)
44 #define reg_OS_TM0CNT_H (*( REGType16v *) REG_TM0CNT_H_ADDR)
50 #define reg_OS_TM1CNT_L (*( REGType16v *) REG_TM1CNT_L_ADDR)
56 #define reg_OS_TM1CNT_H (*( REGType16v *) REG_TM1CNT_H_ADDR)
62 #define reg_OS_TM2CNT_L (*( REGType16v *) REG_TM2CNT_L_ADDR)
68 #define reg_OS_TM2CNT_H (*( REGType16v *) REG_TM2CNT_H_ADDR)
74 #define reg_OS_TM3CNT_L (*( REGType16v *) REG_TM3CNT_L_ADDR)
80 #define reg_OS_TM3CNT_H (*( REGType16v *) REG_TM3CNT_H_ADDR)
86 #define reg_OS_IME (*( REGType16v *) REG_IME_ADDR)
104 #define reg_OS_PAUSE (*( REGType16v *) REG_PAUSE_ADDR)
Dioreg_EXI.h44 #define reg_EXI_SIOCNT (*( REGType16v *) REG_SIOCNT_ADDR)
50 #define reg_EXI_SIOSEL (*( REGType16v *) REG_SIOSEL_ADDR)
Dioreg_PXI.h38 #define reg_PXI_SUBPINTF (*( REGType16v *) REG_SUBPINTF_ADDR)
44 #define reg_PXI_SUBP_FIFO_CNT (*( REGType16v *) REG_SUBP_FIFO_CNT_ADDR)
Dioreg_GX.h44 #define reg_GX_DISPSTAT (*( REGType16v *) REG_DISPSTAT_ADDR)
50 #define reg_GX_VCOUNT (*( REGType16v *) REG_VCOUNT_ADDR)
68 #define reg_GX_DISP_MMEM_FIFO_L (*( REGType16v *) REG_DISP_MMEM_FIFO_L_A…
74 #define reg_GX_DISP_MMEM_FIFO_H (*( REGType16v *) REG_DISP_MMEM_FIFO_H_A…
80 #define reg_GX_MASTER_BRIGHT (*( REGType16v *) REG_MASTER_BRIGHT_ADDR)
86 #define reg_GX_TVOUTCNT (*( REGType16v *) REG_TVOUTCNT_ADDR)
152 #define reg_GX_VRAM_HI_CNT (*( REGType16v *) REG_VRAM_HI_CNT_ADDR)
170 #define reg_GX_POWCNT (*( REGType16v *) REG_POWCNT_ADDR)
Dioreg_CP.h38 #define reg_CP_DIVCNT (*( REGType16v *) REG_DIVCNT_ADDR)
116 #define reg_CP_SQRTCNT (*( REGType16v *) REG_SQRTCNT_ADDR)
Dioreg_PAD.h38 #define reg_PAD_KEYINPUT (*(const REGType16v *) REG_KEYINPUT_ADDR)
44 #define reg_PAD_KEYCNT (*( REGType16v *) REG_KEYCNT_ADDR)
/TwlSDK-5.4/include/twl/hw/ARM9/tmp/
Dioreg_CFG.h44 #define reg_CFG_CLK (*( REGType16v *) REG_CLK_ADDR)
68 #define reg_CFG_TWL_EX (*( REGType16v *) REG_TWL_EX_ADDR)
/TwlSDK-5.4/build/tools/stripdebug/
Dtypes.h75 typedef vu16 REGType16v; typedef
/TwlSDK-5.4/build/tools/makelst/
Dtypes.h75 typedef vu16 REGType16v; typedef
/TwlSDK-5.4/include/nitro/
Dtypes.h80 typedef vu16 REGType16v; typedef

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