Home
last modified time | relevance | path

Searched refs:r0 (Results 1 – 25 of 49) sorted by relevance

12

/TwlSDK-5.3.1/build/libraries/os/ARM9/src/
Dos_cache.c41 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Enable()
42 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Enable()
60 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Disable()
61 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Disable()
79 cmp r0, #0 in DC_Restore()
84 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Restore()
85 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Restore()
106 mov r0, #0 in DC_InvalidateAll()
107 mcr p15, 0, r0, c7, c6, 0 in DC_InvalidateAll()
125 mov r0, #0 in DC_StoreAll()
[all …]
Dos_tcm.c34 mrc p15, 0, r0, c1, c0, 0 in OS_EnableITCM()
35 orr r0, r0, #HW_C1_ITCM_ENABLE in OS_EnableITCM()
36 mcr p15, 0, r0, c1, c0, 0 in OS_EnableITCM()
51 mrc p15, 0, r0, c1, c0, 0 in OS_DisableITCM()
52 bic r0, r0, #HW_C1_ITCM_ENABLE in OS_DisableITCM()
53 mcr p15, 0, r0, c1, c0, 0 in OS_DisableITCM()
68 and r0, r0, #HW_C9_TCMR_SIZE_MASK in OS_SetITCMParam()
69 mcr p15, 0, r0, c9, c1, 1 in OS_SetITCMParam()
84 mrc p15, 0, r0, c9, c1, 1 in OS_GetITCMParam()
85 and r0, r0, #HW_C9_TCMR_SIZE_MASK in OS_GetITCMParam()
[all …]
Dos_protectionUnit.c34 mrc p15, 0, r0, c1, c0, 0 in OS_EnableProtectionUnit()
35 orr r0, r0, #HW_C1_PROTECT_UNIT_ENABLE in OS_EnableProtectionUnit()
36 mcr p15, 0, r0, c1, c0, 0 in OS_EnableProtectionUnit()
51 mrc p15, 0, r0, c1, c0, 0 in OS_DisableProtectionUnit()
52 bic r0, r0, #HW_C1_PROTECT_UNIT_ENABLE in OS_DisableProtectionUnit()
53 mcr p15, 0, r0, c1, c0, 0 in OS_DisableProtectionUnit()
Dos_protectionRegion.c41 orr r1, r1, r0 in OS_EnableICacheForProtectionRegion()
50 bic r1, r1, r0 in OS_DisableICacheForProtectionRegion()
73 mrc p15, 0, r0, c2, c0, 1 in OS_GetICacheEnableFlagsForProtectionRegion()
105 bic r2, r2, r0 in OS_SetIPermissionsForProtectionRegion()
129 mrc p15, 0, r0, c5, c0, 3 in OS_GetIPermissionsForProtectionRegion()
153 orr r1, r1, r0 in OS_EnableDCacheForProtectionRegion()
162 bic r1, r1, r0 in OS_DisableDCacheForProtectionRegion()
185 mrc p15, 0, r0, c2, c0, 0 in OS_GetDCacheEnableFlagsForProtectionRegion()
217 bic r2, r2, r0 in OS_SetDPermissionsForProtectionRegion()
241 mrc p15, 0, r0, c5, c0, 2 in OS_GetDPermissionsForProtectionRegion()
[all …]
/TwlSDK-5.3.1/build/libraries/os/common/src/
Dos_exception.c72 mrc p15, 0, r0, c1, c0, 0 in OS_SetExceptionVectorUpper()
73 orr r0, r0, #HW_C1_EXCEPT_VEC_UPPER in OS_SetExceptionVectorUpper()
74 mcr p15, 0, r0, c1, c0, 0 in OS_SetExceptionVectorUpper()
89 mrc p15, 0, r0, c1, c0, 0 in OS_SetExceptionVectorLower()
90 bic r0, r0, #HW_C1_EXCEPT_VEC_UPPER in OS_SetExceptionVectorLower()
91 mcr p15, 0, r0, c1, c0, 0 in OS_SetExceptionVectorLower()
163 stmia r12, {r0-r4,sp,lr} in OSi_DebuggerExceptionHook()
171 mrs r0, CPSR in OSi_DebuggerExceptionHook()
172 and r0, r0, #0x1f in OSi_DebuggerExceptionHook()
173 teq r0, #0x17 in OSi_DebuggerExceptionHook()
[all …]
Dos_system.c41 mrs r0, cpsr in OS_EnableInterrupts()
42 bic r1, r0, #HW_PSR_IRQ_DISABLE in OS_EnableInterrupts()
44 and r0, r0, #HW_PSR_IRQ_DISABLE in OS_EnableInterrupts()
61 mrs r0, cpsr in OS_DisableInterrupts()
62 orr r1, r0, #HW_PSR_IRQ_DISABLE in OS_DisableInterrupts()
64 and r0, r0, #HW_PSR_IRQ_DISABLE in OS_DisableInterrupts()
83 orr r2, r2, r0 in OS_RestoreInterrupts()
85 and r0, r1, #HW_PSR_IRQ_DISABLE in OS_RestoreInterrupts()
105 mrs r0, cpsr in OS_EnableInterrupts_IrqAndFiq()
106 bic r1, r0, #HW_PSR_IRQ_FIQ_DISABLE in OS_EnableInterrupts_IrqAndFiq()
[all …]
Dos_irqHandler_inTCM.c84 @1: clz r0, r1 // Count zero of high bit in OS_IrqHandler()
85 bics r1, r1, r3, LSR r0 in OS_IrqHandler()
89 mov r1, r3, LSR r0 in OS_IrqHandler()
92 rsbs r0, r0, #31 in OS_IrqHandler()
99 mov r0, #0 in OS_IrqHandler()
100 @1: ands r2, r1, r3, LSL r0 // Count zero of high bit in OS_IrqHandler()
101 addeq r0, r0, #1 in OS_IrqHandler()
110 cmp r0, #OS_IRQ_TABLE_MAX in OS_IrqHandler()
114 ldr r0, [ r1, r0, LSL #2 ] in OS_IrqHandler()
117 bx r0 in OS_IrqHandler()
[all …]
Dos_callTrace.c37 void OSi_Abort_CallTraceFull(u32 name, u32 returnAddress, u32 r0, u32 sp);
67 cmp r0, #0 in OS_EnableCallTrace()
70 mov r2, r0 in OS_EnableCallTrace()
71 ldrh r0, [ r2, #OSCallTraceInfo.enable ] in OS_EnableCallTrace()
95 cmp r0, #0 in OS_DisableCallTrace()
98 mov r2, r0 in OS_DisableCallTrace()
99 ldrh r0, [ r2, #OSCallTraceInfo.enable ] in OS_DisableCallTrace()
120 stmfd sp!, {r0, lr} in OS_RestoreCallTrace()
122 mov r1, r0 in OS_RestoreCallTrace()
123 ldmfd sp!, {r0, lr} in OS_RestoreCallTrace()
[all …]
Dos_reset.c324 mrc p15, 0, r0, c9, c1, 0 in OSi_GetDTCMAddress()
326 and r0, r0, r1 in OSi_GetDTCMAddress()
518 mov r0, #0 in OSi_DoBoot()
519 str r0, [r1, #0] in OSi_DoBoot()
524 ldrh r0, [r1] in OSi_DoBoot()
525 and r0, r0, #0x000f in OSi_DoBoot()
526 cmp r0, #0x0001 in OSi_DoBoot()
528 mov r0, #0x0100 in OSi_DoBoot()
529 strh r0, [r1] // mainp status == 1 in OSi_DoBoot()
532 mov r0, #0 in OSi_DoBoot()
[all …]
Dos_irqHandler.c93 @1: clz r0, r1 // Count zero of high bit in OS_IrqHandler()
94 bics r1, r1, r3, LSR r0 in OS_IrqHandler()
98 mov r1, r3, LSR r0 in OS_IrqHandler()
101 rsbs r0, r0, #31 in OS_IrqHandler()
108 mov r0, #0 in OS_IrqHandler()
109 @1: ands r2, r1, r3, LSL r0 // Count zero of high bit in OS_IrqHandler()
110 addeq r0, r0, #1 in OS_IrqHandler()
119 cmp r0, #OS_IRQ_TABLE_MAX in OS_IrqHandler()
123 ldr r0, [ r1, r0, LSL #2 ] in OS_IrqHandler()
126 bx r0 // Set return address for thread rescheduling in OS_IrqHandler()
[all …]
Dos_context.c97 stmfd sp!, { lr, r0 } in OS_SaveContext()
98 add r0, r0, #OS_CONTEXT_CP_CONTEXT in OS_SaveContext()
101 ldmfd sp!, { lr, r0 } in OS_SaveContext()
104 add r1, r0, #OS_CONTEXT_CPSR in OS_SaveContext()
112 mov r0, #HW_PSR_SVC_MODE|HW_PSR_IRQ_DISABLE|HW_PSR_FIQ_DISABLE|HW_PSR_ARM_STATE in OS_SaveContext()
113 msr cpsr_c, r0 in OS_SaveContext()
119 mov r0, #1 // Return value via OS_LoadContext in OS_SaveContext()
120 stmia r1, {r0-r14} // Save R0-R14 in OS_SaveContext()
121 add r0, pc, #8 // Set PC_plus4 to do ("bx lr" + 4) in OS_SaveContext()
122 str r0, [r1, #OS_CONTEXT_PC_PLUS4 - OS_CONTEXT_R0 ] in OS_SaveContext()
[all …]
Dos_functionCost.c63 cmp r0, #0 in OS_EnableFunctionCost()
66 mov r2, r0 in OS_EnableFunctionCost()
67 ldrh r0, [ r2, #OSFunctionCostInfo.enable ] in OS_EnableFunctionCost()
91 cmp r0, #0 in OS_DisableFunctionCost()
94 mov r2, r0 in OS_DisableFunctionCost()
95 ldrh r0, [ r2, #OSFunctionCostInfo.enable ] in OS_DisableFunctionCost()
117 stmfd sp!, {r0, lr} in OS_RestoreFunctionCost()
119 mov r1, r0 in OS_RestoreFunctionCost()
120 ldmfd sp!, {r0, lr} in OS_RestoreFunctionCost()
125 strh r0, [ r1, #OSFunctionCostInfo.enable ] in OS_RestoreFunctionCost()
[all …]
/TwlSDK-5.3.1/build/libraries/init/ARM9.TWL/src/
Dcrt0.FLX.c208 #define SET_PROTECTION_A(id, adr, siz) ldr r0, =(adr|HW_C6_PR_##siz|HW_C6_PR_ENABLE)
209 #define SET_PROTECTION_B(id, adr, siz) mcr p15, 0, r0, c6, id, 0
226 mov r0, #0 in _start()
230 mov r0, #0 in _start()
246 @001: ldr r0, [r1], #4 in _start()
247 str r0, [r2], #4 in _start()
252 ldr r0, =HW_BOOT_SYNC_PHASE in _start()
254 strh r1, [r0] in _start()
255 ldr r0, =HW_BOOT_SHAKEHAND_9 in _start()
270 @002: ldr r0, [r1], #4 in _start()
[all …]
/TwlSDK-5.3.1/build/libraries/init/ARM9/src/
Dcrt0.c91 ldrh r0, [r12, #REG_VCOUNT_OFFSET] in _start()
92 cmp r0, #0 in _start()
100 mov r0, #HW_PSR_SVC_MODE in _start()
101 msr cpsr_c, r0 in _start()
102 ldr r0, =INITi_HW_DTCM in _start()
103 add r0, r0, #0x3fc0 in _start()
104 mov sp, r0 in _start()
107 mov r0, #HW_PSR_IRQ_MODE in _start()
108 msr cpsr_c, r0 in _start()
109 ldr r0, =INITi_HW_DTCM in _start()
[all …]
/TwlSDK-5.3.1/build/libraries/mi/common/src/
Dmi_uncomp_stream.c116 ldr r3, [r0, #MIUncompContextRL.destp] // r3: destp = context->destp; in MI_ReadUncompRL8()
117 … ldr r4, [r0, #MIUncompContextRL.destCount] // r4: destCount = context->destCount; in MI_ReadUncompRL8()
118 ldrb r5, [r0, #MIUncompContextRL.flags] // r5: flags = context->flags; in MI_ReadUncompRL8()
119 ldrh r6, [r0, #MIUncompContextRL.length] // r6: length = context->length in MI_ReadUncompRL8()
175 str r3, [r0, #MIUncompContextRL.destp] // context->destp = destp; in MI_ReadUncompRL8()
176 str r4, [r0, #MIUncompContextRL.destCount] // context->destCount = destCount; in MI_ReadUncompRL8()
177 strb r5, [r0, #MIUncompContextRL.flags] // context->flags = flags; in MI_ReadUncompRL8()
178 strh r6, [r0, #MIUncompContextRL.length] // context->length = length; in MI_ReadUncompRL8()
179 mov r0, r4 in MI_ReadUncompRL8()
204 ldr r3, [r0, #MIUncompContextRL.destp] // r3: destp = context->destp; in MI_ReadUncompRL16()
[all …]
Dmi_memory.c109 strlth r0, [r1, r3] // *((vu16 *)(destp + n)) = data in MIi_CpuClear16()
136 ldrlth r3, [r0, r12] // *((vu16 *)(destp + n)) = *((vu16 *)(srcp + n)) in MIi_CpuCopy16()
170 ldrlth r3, [r0, r12] // *((vu16 *)(destp + n)) = *((vu16 *)(srcp + n)) in MIi_CpuSend16()
199 ldrlth r3, [r0] // *((vu16 *)(destp + n)) = *((vu16 *)(srcp + n)) in MIi_CpuRecv16()
225 ldrlth r3, [r0] // *((vu32 *)(destp)) = *((vu32 *)(srcp)) in MIi_CpuPipe16()
247 add r0, r0, r2 // r0: srcp += size in CpuCopy16Reverse()
252 ldrlth r2, [r0, #-2]! // *(--(vu32 *)(destp)) = *(--(vu32 *)(srcp)) in CpuCopy16Reverse()
350 stmltia r1!, {r0} // *((vu32 *)(destp++)) = data in MIi_CpuClear32()
373 ldmltia r0!, {r2} // *((vu32 *)(destp)++) = *((vu32 *)(srcp)++) in MIi_CpuCopy32()
394 add r12, r0, r2 // r12: srcEndp = srcp + size in MIi_CpuSend32()
[all …]
Dmi_uncompress.c81 ldrb r9, [r0], #1 // r9: srcTmp = *srcp++; in MI_UnpackBits()
145 ldr r5, [r0], #4 // r2: destCount = *(u32 *)srcp >> 8 in MI_UncompressLZ8()
154 ldrb r14, [r0], #1 // r14: flags = *srcp++ in MI_UncompressLZ8()
162 ldrb r6, [r0], #1 // *srcp++; in MI_UncompressLZ8()
168 @23: ldrb r5, [r0, #0] // r3: length = (*srcp >> 4); in MI_UncompressLZ8()
177 … add r0, r0, #1 // isWide = (length == 1)? 1 : 0; in MI_UncompressLZ8()
184 … ldrb r5, [r0], #1 // length += (*srcp++) << 4; in MI_UncompressLZ8()
189 ldrb r5, [r0, #0] // length += (*srcp >> 4); in MI_UncompressLZ8()
192 add r0, r0, #1 // r12: offset = (*srcp++ & 0x0f) << 8; in MI_UncompressLZ8()
195 ldrb r6, [r0], #1 // offset = (offset | *srcp++) + 1; in MI_UncompressLZ8()
[all …]
Dmi_swap.c45 swp r0, r0, [r1] in MI_SwapWord()
61 swpb r0, r0, [r1] in MI_SwapByte()
/TwlSDK-5.3.1/build/libraries/math/common/src/
Dqsort.c92 mov r0, left in MATH_QSort()
95 cmp r0, #0 // if ( comp( left, right ) > 0 ) { in MATH_QSort()
98 mov r0, width_ in MATH_QSort()
99 tst r0, #3 in MATH_QSort()
103 subs r0, r0, #1 in MATH_QSort()
112 subs r0, r0, #4 in MATH_QSort()
131 mov r0, width_ in MATH_QSort()
133 tst r0, #3 in MATH_QSort()
137 subs r0, r0, #1 in MATH_QSort()
146 subs r0, r0, #4 in MATH_QSort()
[all …]
/TwlSDK-5.3.1/build/libraries/fx/common/src/
Dfx_mtx44.c34 stmia r0!, {r2,r3} in MTX_Identity44_()
36 stmia r0!, {r1,r3} in MTX_Identity44_()
37 stmia r0!, {r1,r2,r3} in MTX_Identity44_()
38 stmia r0!, {r1,r3} in MTX_Identity44_()
39 stmia r0!, {r1,r2,r3} in MTX_Identity44_()
40 stmia r0!, {r1,r3} in MTX_Identity44_()
41 stmia r0!, {r1,r2} in MTX_Identity44_()
48 ldmia r0!, {r2-r3, r12} in MTX_Copy44To33_()
49 add r0, r0, #4 in MTX_Copy44To33_()
52 ldmia r0!, {r2-r3, r12} in MTX_Copy44To33_()
[all …]
Dfx_mtx33.c31 str r2, [r0, #32] in MTX_Identity33_()
33 stmia r0!, {r2, r3} in MTX_Identity33_()
35 stmia r0!, {r1, r3} in MTX_Identity33_()
36 stmia r0!, {r2, r3} in MTX_Identity33_()
37 stmia r0!, {r1, r3} in MTX_Identity33_()
43 ldmia r0!, {r2-r3, r12} in MTX_Copy33To43_()
45 ldmia r0!, {r2-r3, r12} in MTX_Copy33To43_()
47 ldmia r0!, {r2-r3, r12} in MTX_Copy33To43_()
64 ldmia r0!, {r2-r4} in MTX_Copy33To44_()
66 ldmia r0!, {r2-r4} in MTX_Copy33To44_()
[all …]
Dfx_mtx43.c30 stmia r0!, {r2, r3} in MTX_Identity43_()
32 stmia r0!, {r1, r3} in MTX_Identity43_()
33 stmia r0!, {r2, r3} in MTX_Identity43_()
34 stmia r0!, {r1, r3} in MTX_Identity43_()
35 stmia r0!, {r2, r3} in MTX_Identity43_()
36 stmia r0!, {r1, r3} in MTX_Identity43_()
46 ldmia r0!, {r2-r4} in MTX_Copy43To44_()
48 ldmia r0!, {r2-r4} in MTX_Copy43To44_()
50 ldmia r0!, {r2-r4} in MTX_Copy43To44_()
53 ldmia r0!, {r2-r4} in MTX_Copy43To44_()
[all …]
/TwlSDK-5.3.1/build/libraries/cp/common/src/
Dcp_context.c39 stmia r0!, {r2-r4,r12} in CP_SaveContext()
44 stmia r0!, {r2-r3} in CP_SaveContext()
48 strh r12, [r0] in CP_SaveContext()
50 strh r2, [r0, #2] in CP_SaveContext()
70 ldmia r0, {r2-r4,r12} in CPi_RestoreContext()
72 ldrh r2, [r0, #CPContext.div_mode] in CPi_RestoreContext()
73 ldrh r3, [r0, #CPContext.sqrt_mode] in CPi_RestoreContext()
78 add r0, r0, #CPContext.sqrt in CPi_RestoreContext()
81 ldmia r0, {r2-r3} in CPi_RestoreContext()
/TwlSDK-5.3.1/build/libraries/gx/ARM9/src/
Dgxasm.c23 ldmia r0!, {r2,r3,r12} // r0-r3, r12 need not be saved. in GX_SendFifo48B()
25 ldmia r0!, {r2,r3,r12} in GX_SendFifo48B()
27 ldmia r0!, {r2,r3,r12} in GX_SendFifo48B()
29 ldmia r0!, {r2,r3,r12} in GX_SendFifo48B()
39 ldmia r0!, {r2-r8, r12} in GX_SendFifo64B()
41 ldmia r0!, {r2-r8, r12} in GX_SendFifo64B()
52 ldmia r0!, {r2-r8, r12} in GX_SendFifo128B()
54 ldmia r0!, {r2-r8, r12} in GX_SendFifo128B()
56 ldmia r0!, {r2-r8, r12} in GX_SendFifo128B()
58 ldmia r0!, {r2-r8, r12} in GX_SendFifo128B()
Dg3x.c774 stmia r0, {r1-r3, r12} // 0 - 15 in GXi_NopClearFifo128_()
775 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
776 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
777 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
779 stmia r0, {r1-r3, r12} // 16 - 31 in GXi_NopClearFifo128_()
780 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
781 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
782 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
784 stmia r0, {r1-r3, r12} // 32 - 47 in GXi_NopClearFifo128_()
785 stmia r0, {r1-r3, r12} in GXi_NopClearFifo128_()
[all …]

12