Searched refs:vu8 (Results 1 – 16 of 16) sorted by relevance
120 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreMX()121 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreMX()122 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; in CTRDGi_EraseFlashChipCoreMX()123 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreMX()124 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreMX()125 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x10; in CTRDGi_EraseFlashChipCoreMX()174 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashSectorCoreMX()175 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashSectorCoreMX()176 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; in CTRDGi_EraseFlashSectorCoreMX()177 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashSectorCoreMX()[all …]
137 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreLE()138 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreLE()139 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; in CTRDGi_EraseFlashChipCoreLE()140 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreLE()141 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreLE()142 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x10; in CTRDGi_EraseFlashChipCoreLE()183 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashSectorCoreLE()184 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashSectorCoreLE()185 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; in CTRDGi_EraseFlashSectorCoreLE()186 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashSectorCoreLE()[all …]
58 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_SetFlashBankMx()59 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_SetFlashBankMx()60 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xb0; in CTRDGi_SetFlashBankMx()61 *(vu8 *)CTRDG_AGB_FLASH_ADR = (u8)bank; in CTRDGi_SetFlashBankMx()72 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_ReadFlashID()73 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_ReadFlashID()74 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x90; in CTRDGi_ReadFlashID()91 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_ReadFlashID()92 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_ReadFlashID()93 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xf0; in CTRDGi_ReadFlashID()[all …]
132 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreAT()133 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreAT()134 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; in CTRDGi_EraseFlashChipCoreAT()135 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashChipCoreAT()136 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashChipCoreAT()137 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x10; in CTRDGi_EraseFlashChipCoreAT()183 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_EraseFlashSectorCoreAT()184 *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; in CTRDGi_EraseFlashSectorCoreAT()185 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xa0; in CTRDGi_EraseFlashSectorCoreAT()265 *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; in CTRDGi_WriteFlashSectorCoreAT()[all …]
52 typedef volatile u8 vu8; typedef74 typedef vu8 REGType8v;
57 typedef volatile u8 vu8; typedef79 typedef vu8 REGType8v;
84 vu8* ptr1 = (vu8*)syncBuf; in OSi_SyncWithOtherProc()85 vu8* ptr2 = (vu8*)syncBuf +1; in OSi_SyncWithOtherProc()86 vu8* pfinish = (vu8*)syncBuf +2; in OSi_SyncWithOtherProc()87 vu8* pconf = (vu8*)syncBuf +3; in OSi_SyncWithOtherProc()
621 vu8 *const reg_CARD_MASTERCNT = (vu8 *)(HW_REG_BASE + 0x1a1); in OSi_ReadCardRom32()622 vu8 *const reg_CARD_CMD = (vu8 *)(HW_REG_BASE + 0x1a8); in OSi_ReadCardRom32()
85 *(vu8*)(REG_MBK_A0_ADDR + num) in MIi_SetWramBank_A()86 = (vu8)((enable? REG_MI_MBK_A0_E_MASK: 0) | proc | ((offset>>1)<<REG_MI_MBK_A0_OF_SHIFT)); in MIi_SetWramBank_A()94 *(vu8*)(REG_MBK_B0_ADDR + num) in MIi_SetWramBank_B()95 = (vu8)((enable? REG_MI_MBK_B0_E_MASK: 0) | proc | (offset<<REG_MI_MBK_B0_OF_SHIFT)); in MIi_SetWramBank_B()103 *(vu8*)(REG_MBK_C0_ADDR + num) in MIi_SetWramBank_C()104 = (vu8)((enable? REG_MI_MBK_C0_E_MASK: 0) | proc | (offset<<REG_MI_MBK_C0_OF_SHIFT)); in MIi_SetWramBank_C()128 vu8 MIi_GetWramBank_A( int num ) in MIi_GetWramBank_A()131 return *(vu8*)(REG_MBK_A0_ADDR + num); in MIi_GetWramBank_A()134 vu8 MIi_GetWramBank_B( int num ) in MIi_GetWramBank_B()137 return *(vu8*)(REG_MBK_B0_ADDR + num); in MIi_GetWramBank_B()[all …]
248 *(vu8*)(HW_INIT_LOCK_BUF+4) = n; in OSi_SetSyncValue()252 return *(vu8*)(HW_INIT_LOCK_BUF+4); in OSi_GetSyncValue()
59 asm u8 MI_SwapByte( register u32 setData, register vu8* destp ) in MI_SwapByte()
197 vu8 MIi_GetWramBank_A( int num );198 vu8 MIi_GetWramBank_B( int num );199 vu8 MIi_GetWramBank_C( int num );200 vu8 MIi_GetWramBank( MIWramPos wram, int num );
509 *((vu8 *)REG_MOSAIC_ADDR) = (u8)((hSize << REG_G2_MOSAIC_BGHSIZE_SHIFT) | in G2_SetBGMosaicSize()529 *((vu8 *)(REG_MOSAIC_ADDR + 1)) = (u8)((hSize << (REG_G2_MOSAIC_OBJHSIZE_SHIFT - 8)) | in G2_SetOBJMosaicSize()1012 *((vu8 *)REG_DB_MOSAIC_ADDR) = (u8)((hSize << REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT) | in G2S_SetBGMosaicSize()1033 *((vu8 *)(REG_DB_MOSAIC_ADDR + 1)) = (u8)((hSize << (REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT - 8)) | in G2S_SetOBJMosaicSize()
27 #define reg_CFG_DSP_RST *(vu8*)REG_RST_ADDR
207 … vu8 *bank = &((vu8*)((wram == MI_WRAM_B) ? REG_MBK_B0_ADDR : REG_MBK_C0_ADDR))[slot]; in DSPi_CommitWram()