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Searched refs:MI_CTRDG_RAMCYCLE_18 (Results 1 – 7 of 7) sorted by relevance

/TwlSDK-5.2.1/build/libraries/ctrdg/ARM9/src/
Dctrdg_flash_LE26FV10N1TS-10.c60 {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_8}, // agb read cycle=8, write cycle=3
Dctrdg_sram.c49 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDGi_ReadAgbSramCore()
79 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDGi_WriteAgbSramCore()
110 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDGi_VerifyAgbSramCore()
Dctrdg_flash_AT29LV512.c85 {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_18}, // agb read cycle=8, write cycle=8
109 {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_18}, // agb read cycle=8, write cycle=8
Dctrdg_backup.c87 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDG_IdentifyAgbBackup()
Dctrdg_flash_MX29L010.c62 {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_8}, // agb read cycle=8, write cycle=3
86 {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_8}, // agb read cycle=8, write cycle=3
Dctrdg_flash_common.c262 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDGi_ReadAgbFlashCore()
311 MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); in CTRDGi_VerifyAgbFlashCore()
/TwlSDK-5.2.1/include/nitro/mi/
DexMemory.h113 MI_CTRDG_RAMCYCLE_18 = 3 // 18 cycle enumerator
171 #define MI_RAMCYCLE_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_RAMCYCLE_18 )