1 /*---------------------------------------------------------------------------*
2 Project: TwlSDK - libraries - spi
3 File: spi.h
4
5 Copyright 2003-2008 Nintendo. All rights reserved.
6
7 These coded instructions, statements, and computer programs contain
8 proprietary information of Nintendo of America Inc. and/or Nintendo
9 Company Ltd., and are protected by Federal copyright law. They may
10 not be disclosed to third parties or copied or duplicated in any form,
11 in whole or in part, without the prior written consent of Nintendo.
12
13 $Date:: 2008-09-18#$
14 $Rev: 8573 $
15 $Author: okubata_ryoma $
16 *---------------------------------------------------------------------------*/
17
18 #ifndef LIBRARIES_SPI_H_
19 #define LIBRARIES_SPI_H_
20
21 #include <nitro/types.h>
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /*===========================================================================*/
28
29 /*---------------------------------------------------------------------------*
30 Inline Function Definitions
31 Temporarily defined for ARM9.
32 Should be defined in ARM9 library as static functions.
33 *---------------------------------------------------------------------------*/
34 #ifdef SDK_ARM9
35
36 /*---------------------------------------------------------------------------*
37 Name: SPI_TpSamplingNow
38
39 Description: Samples touch panel once.
40
41 Arguments: None.
42
43 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
44
45 *---------------------------------------------------------------------------*/
SPI_TpSamplingNow(void)46 static inline BOOL SPI_TpSamplingNow(void)
47 {
48 // Send packet [0]
49 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_TOUCHPANEL,
50 SPI_PXI_START_BIT |
51 SPI_PXI_END_BIT |
52 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_TP_SAMPLING << 8), 0))
53 {
54 return FALSE;
55 }
56
57 return TRUE;
58 }
59
60 /*---------------------------------------------------------------------------*
61 Name: SPI_TpAutoSamplingOn
62
63 Description: Starts auto-sampling of touch panel.
64
65 Arguments: vCount - V Count to carry out sampling.
66 When sampling multiple times per frame, a single frame's time divisions will start here.
67
68 frequency - Frequency of sampling for 1 frame.
69
70 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
71
72 *---------------------------------------------------------------------------*/
SPI_TpAutoSamplingOn(u16 vCount,u8 frequency)73 static inline BOOL SPI_TpAutoSamplingOn(u16 vCount, u8 frequency)
74 {
75 // Send packet [0]
76 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_TOUCHPANEL,
77 SPI_PXI_START_BIT |
78 (0 << SPI_PXI_INDEX_SHIFT) |
79 (SPI_PXI_COMMAND_TP_AUTO_ON << 8) | (u32)frequency, 0))
80 {
81 return FALSE;
82 }
83
84 // Send packet [1]
85 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_TOUCHPANEL,
86 SPI_PXI_END_BIT | (1 << SPI_PXI_INDEX_SHIFT) | (u32)vCount, 0))
87 {
88 return FALSE;
89 }
90
91 return TRUE;
92 }
93
94 /*---------------------------------------------------------------------------*
95 Name: SPI_TpAutoSamplingOff
96
97 Description: Stops auto-sampling of touch panel.
98
99 Arguments: None.
100
101 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
102
103 *---------------------------------------------------------------------------*/
SPI_TpAutoSamplingOff(void)104 static inline BOOL SPI_TpAutoSamplingOff(void)
105 {
106 // Send packet [0]
107 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_TOUCHPANEL,
108 SPI_PXI_START_BIT |
109 SPI_PXI_END_BIT |
110 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_TP_AUTO_OFF << 8), 0))
111 {
112 return FALSE;
113 }
114
115 return TRUE;
116 }
117
118 /*---------------------------------------------------------------------------*
119 Name: SPI_TpSetupStability
120
121 Description: Sets stability determination parameters for sampling
122
123 Arguments: range - For continuous sampling, error for which detected voltage is considered stable.
124 The detection value is 12 bits, 0 - 4095.
125
126 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
127
128 *---------------------------------------------------------------------------*/
SPI_TpSetupStability(u16 range)129 static inline BOOL SPI_TpSetupStability(u16 range)
130 {
131 // Send packet [0]
132 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_TOUCHPANEL,
133 SPI_PXI_START_BIT |
134 SPI_PXI_END_BIT |
135 (0 << SPI_PXI_INDEX_SHIFT) |
136 (SPI_PXI_COMMAND_TP_SETUP_STABILITY << 8) | (u32)range, 0))
137 {
138 return FALSE;
139 }
140
141 return TRUE;
142 }
143
144 /*---------------------------------------------------------------------------*
145 Name: SPI_NvramWriteEnable
146
147 Description: Issues "write permitted" instruction to NVRAM.
148
149 Arguments: None.
150
151 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
152
153 *---------------------------------------------------------------------------*/
SPI_NvramWriteEnable(void)154 static inline BOOL SPI_NvramWriteEnable(void)
155 {
156 // Send packet [0]
157 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
158 SPI_PXI_START_BIT |
159 SPI_PXI_END_BIT |
160 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_WREN << 8), 0))
161 {
162 return FALSE;
163 }
164
165 return TRUE;
166 }
167
168 /*---------------------------------------------------------------------------*
169 Name: SPI_NvramWriteDisable
170
171 Description: Issues "write prohibited" instruction to NVRAM.
172
173 Arguments: None.
174
175 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
176
177 *---------------------------------------------------------------------------*/
SPI_NvramWriteDisable(void)178 static inline BOOL SPI_NvramWriteDisable(void)
179 {
180 // Send packet [0]
181 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
182 SPI_PXI_START_BIT |
183 SPI_PXI_END_BIT |
184 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_WRDI << 8), 0))
185 {
186 return FALSE;
187 }
188
189 return TRUE;
190 }
191
192 /*---------------------------------------------------------------------------*
193 Name: SPI_NvramReadStatusRegister
194
195 Description: Issues "status register read" command to NVRAM.
196
197 Arguments: pData - Pointer to variable storing read value.
198 The ARM7 directly writes the value so be careful of the cache.
199
200 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
201
202 *---------------------------------------------------------------------------*/
SPI_NvramReadStatusRegister(u8 * pData)203 static inline BOOL SPI_NvramReadStatusRegister(u8 *pData)
204 {
205 // Send packet [0]
206 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
207 SPI_PXI_START_BIT |
208 (0 << SPI_PXI_INDEX_SHIFT) |
209 (SPI_PXI_COMMAND_NVRAM_RDSR << 8) | ((u32)pData >> 24), 0))
210 {
211 return FALSE;
212 }
213
214 // Send packet [1]
215 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
216 (1 << SPI_PXI_INDEX_SHIFT) | (((u32)pData >> 8) & 0x0000ffff), 0))
217 {
218 return FALSE;
219 }
220
221 // Send packet [2]
222 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
223 SPI_PXI_END_BIT |
224 (2 << SPI_PXI_INDEX_SHIFT) | (((u32)pData << 8) & 0x0000ff00), 0))
225 {
226 return FALSE;
227 }
228
229 return TRUE;
230 }
231
232 /*---------------------------------------------------------------------------*
233 Name: SPI_NvramReadDataBytes
234
235 Description: Issues a read command to NVRAM.
236
237 Arguments: address - Read start address on NVRAM. Only 24 bits valid.
238 size - Byte size to consecutively read.
239 pData - Pointer to array storing read value.
240 The ARM7 directly writes the value so be careful of the cache.
241
242 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
243
244 *---------------------------------------------------------------------------*/
SPI_NvramReadDataBytes(u32 address,u32 size,u8 * pData)245 static inline BOOL SPI_NvramReadDataBytes(u32 address, u32 size, u8 *pData)
246 {
247 // Send packet [0]
248 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
249 SPI_PXI_START_BIT |
250 (0 << SPI_PXI_INDEX_SHIFT) |
251 (SPI_PXI_COMMAND_NVRAM_READ << 8) |
252 ((address >> 16) & 0x000000ff), 0))
253 {
254 return FALSE;
255 }
256
257 // Send packet [1]
258 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
259 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
260 {
261 return FALSE;
262 }
263
264 // Send packet [2]
265 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM, (2 << SPI_PXI_INDEX_SHIFT) | (size >> 16), 0))
266 {
267 return FALSE;
268 }
269
270 // Send packet [3]
271 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
272 (3 << SPI_PXI_INDEX_SHIFT) | (size & 0x0000ffff), 0))
273 {
274 return FALSE;
275 }
276
277 // Send packet [4]
278 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
279 (4 << SPI_PXI_INDEX_SHIFT) | ((u32)pData >> 16), 0))
280 {
281 return FALSE;
282 }
283
284 // Send packet [5]
285 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
286 SPI_PXI_END_BIT |
287 (5 << SPI_PXI_INDEX_SHIFT) | ((u32)pData & 0x0000ffff), 0))
288 {
289 return FALSE;
290 }
291
292 return TRUE;
293 }
294
295 /*---------------------------------------------------------------------------*
296 Name: SPI_NvramReadHigherSpeed
297
298 Description: Issues 'high speed read' command to NVRAM.
299 After a 'high speed read' command is issued, ticks from an 8-bit dummy clock are used before data is read. This allows you to read with a clock as fast as 25 MHz.
300
301 However, the SPI clock maximum is up to 4 MHz so using it there is meaningless.
302 The normal 'read' command supports clocks up to a maximum of 20 MHz.
303 The description above applies to M45PE40 devices. For the LE25FW203T, both a 'read' and a 'high-speed read' operate at 30 MHz.
304
305
306 Arguments: address - Read start address on NVRAM. Only 24 bits valid.
307 size - Byte size to consecutively read.
308 pData - Pointer to array storing read value.
309 The ARM7 directly writes the value so be careful of the cache.
310
311 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
312
313 *---------------------------------------------------------------------------*/
SPI_NvramReadHigherSpeed(u32 address,u32 size,u8 * pData)314 static inline BOOL SPI_NvramReadHigherSpeed(u32 address, u32 size, u8 *pData)
315 {
316 // Send packet [0]
317 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
318 SPI_PXI_START_BIT |
319 (0 << SPI_PXI_INDEX_SHIFT) |
320 (SPI_PXI_COMMAND_NVRAM_FAST_READ << 8) |
321 ((address >> 16) & 0x000000ff), 0))
322 {
323 return FALSE;
324 }
325
326 // Send packet [1]
327 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
328 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
329 {
330 return FALSE;
331 }
332
333 // Send packet [2]
334 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM, (2 << SPI_PXI_INDEX_SHIFT) | (size >> 16), 0))
335 {
336 return FALSE;
337 }
338
339 // Send packet [3]
340 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
341 (3 << SPI_PXI_INDEX_SHIFT) | (size & 0x0000ffff), 0))
342 {
343 return FALSE;
344 }
345
346 // Send packet [4]
347 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
348 (4 << SPI_PXI_INDEX_SHIFT) | ((u32)pData >> 16), 0))
349 {
350 return FALSE;
351 }
352
353 // Send packet [5]
354 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
355 SPI_PXI_END_BIT |
356 (5 << SPI_PXI_INDEX_SHIFT) | ((u32)pData & 0x0000ffff), 0))
357 {
358 return FALSE;
359 }
360
361 return TRUE;
362 }
363
364 /*---------------------------------------------------------------------------*
365 Name: SPI_NvramPageWrite
366
367 Description: Issues 'page write' command to NVRAM.
368 In NVRAM, a 'page erase' and a 'conditional page write' occur in succession.
369
370
371 Arguments: address - Write start address on NVRAM. Only 24 bits valid.
372 size - Consecutively written byte size.
373 If the sum of address and size exceeds the page boundary (256 bytes), the excess data is ignored.
374
375 pData - Array where written value is stored.
376 The ARM7 loads directly, so you must ensure that data is written from the cache to memory in advance.
377
378
379 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
380
381 *---------------------------------------------------------------------------*/
SPI_NvramPageWrite(u32 address,u16 size,const u8 * pData)382 static inline BOOL SPI_NvramPageWrite(u32 address, u16 size, const u8 *pData)
383 {
384 // Send packet [0]
385 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
386 SPI_PXI_START_BIT |
387 (0 << SPI_PXI_INDEX_SHIFT) |
388 (SPI_PXI_COMMAND_NVRAM_PW << 8) | ((address >> 16) & 0x000000ff), 0))
389 {
390 return FALSE;
391 }
392
393 // Send packet [1]
394 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
395 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
396 {
397 return FALSE;
398 }
399
400 // Send packet [2]
401 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM, (2 << SPI_PXI_INDEX_SHIFT) | (u32)size, 0))
402 {
403 return FALSE;
404 }
405
406 // Send packet [3]
407 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
408 (3 << SPI_PXI_INDEX_SHIFT) | ((u32)pData >> 16), 0))
409 {
410 return FALSE;
411 }
412
413 // Send packet [4]
414 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
415 SPI_PXI_END_BIT |
416 (4 << SPI_PXI_INDEX_SHIFT) | ((u32)pData & 0x0000ffff), 0))
417 {
418 return FALSE;
419 }
420
421 return TRUE;
422 }
423
424 /*---------------------------------------------------------------------------*
425 Name: SPI_NvramPageWrite
426
427 Description: Issues "page write (conditional)" command to NVRAM.
428 Writes overwhelmingly faster than normal "page write", but the only operation you can do is lower the bit.
429 The '0' bit stays a '0' even if a '1' is written to it.
430
431 Arguments: address - Write start address on NVRAM. Only 24 bits valid.
432 size - Consecutively written byte size.
433 If the sum of address and size exceeds the page boundary (256 bytes), the excess data is ignored.
434
435 pData - Array where written value is stored.
436 The ARM7 loads directly, so you must ensure that data is written from the cache to memory in advance.
437
438
439 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
440
441 *---------------------------------------------------------------------------*/
SPI_NvramPageProgram(u32 address,u16 size,const u8 * pData)442 static inline BOOL SPI_NvramPageProgram(u32 address, u16 size, const u8 *pData)
443 {
444 // Send packet [0]
445 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
446 SPI_PXI_START_BIT |
447 (0 << SPI_PXI_INDEX_SHIFT) |
448 (SPI_PXI_COMMAND_NVRAM_PP << 8) | ((address >> 16) & 0x000000ff), 0))
449 {
450 return FALSE;
451 }
452
453 // Send packet [1]
454 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
455 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
456 {
457 return FALSE;
458 }
459
460 // Send packet [2]
461 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM, (2 << SPI_PXI_INDEX_SHIFT) | (u32)size, 0))
462 {
463 return FALSE;
464 }
465
466 // Send packet [3]
467 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
468 (3 << SPI_PXI_INDEX_SHIFT) | ((u32)pData >> 16), 0))
469 {
470 return FALSE;
471 }
472
473 // Send packet [4]
474 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
475 SPI_PXI_END_BIT |
476 (4 << SPI_PXI_INDEX_SHIFT) | ((u32)pData & 0x0000ffff), 0))
477 {
478 return FALSE;
479 }
480
481 return TRUE;
482 }
483
484 /*---------------------------------------------------------------------------*
485 Name: SPI_NvramPageErase
486
487 Description: Issues "page erase" instruction to NVRAM.
488 All bits for erased page are all '1'.
489
490 Arguments: address - Address on NVRAM of page erased. Only 24 bits valid.
491 All of the 256 bytes of the page included in this address are erased.
492 In NVRAM, it is thought that an address with the lower 8 bits cleared will be the address to erase.
493
494
495 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
496
497 *---------------------------------------------------------------------------*/
SPI_NvramPageErase(u32 address)498 static inline BOOL SPI_NvramPageErase(u32 address)
499 {
500 // Send packet [0]
501 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
502 SPI_PXI_START_BIT |
503 (0 << SPI_PXI_INDEX_SHIFT) |
504 (SPI_PXI_COMMAND_NVRAM_PE << 8) | ((address >> 16) & 0x000000ff), 0))
505 {
506 return FALSE;
507 }
508
509 // Send packet [1]
510 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
511 SPI_PXI_END_BIT |
512 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
513 {
514 return FALSE;
515 }
516
517 return TRUE;
518 }
519
520 /*---------------------------------------------------------------------------*
521 Name: SPI_NvramSectorErase
522
523 Description: Issues "sector erase" instruction to NVRAM.
524 All bits for erased sector are all '1'.
525
526 Arguments: address - Address on NVRAM of sector erased. Only 24 bits valid.
527 All of the 64 bytes of the sector included in this address are erased.
528 In NVRAM, it is thought that an address with the lower 16 bits cleared will be the address to erase.
529
530
531 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
532
533 *---------------------------------------------------------------------------*/
SPI_NvramSectorErase(u32 address)534 static inline BOOL SPI_NvramSectorErase(u32 address)
535 {
536 // Send packet [0]
537 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
538 SPI_PXI_START_BIT |
539 (0 << SPI_PXI_INDEX_SHIFT) |
540 (SPI_PXI_COMMAND_NVRAM_SE << 8) | ((address >> 16) & 0x000000ff), 0))
541 {
542 return FALSE;
543 }
544
545 // Send packet [1]
546 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
547 SPI_PXI_END_BIT |
548 (1 << SPI_PXI_INDEX_SHIFT) | (address & 0x0000ffff), 0))
549 {
550 return FALSE;
551 }
552
553 return TRUE;
554 }
555
556 /* Use prohibited in conjunction with introduction of new model number device (2007/4/3 terui@nintendo.co.jp) */
557 #if 0
558 /*---------------------------------------------------------------------------*
559 Name: SPI_NvramPowerDown
560
561 Description: Issues "power save" instruction to NVRAM.
562 Will not receive instruction other than "return from power save".
563
564 Arguments: None.
565
566 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
567
568 *---------------------------------------------------------------------------*/
569 static inline BOOL SPI_NvramPowerDown(void)
570 {
571 // Send packet [0]
572 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
573 SPI_PXI_START_BIT |
574 SPI_PXI_END_BIT |
575 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_DP << 8), 0))
576 {
577 return FALSE;
578 }
579
580 return TRUE;
581 }
582
583 /*---------------------------------------------------------------------------*
584 Name: SPI_NvramReleasePowerDown
585
586 Description: Issues "return from power save" instruction to NVRAM.
587 This is ignored if the system is not in power-save mode.
588
589 Arguments: None.
590
591 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
592
593 *---------------------------------------------------------------------------*/
594 static inline BOOL SPI_NvramReleasePowerDown(void)
595 {
596 // Send packet [0]
597 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
598 SPI_PXI_START_BIT |
599 SPI_PXI_END_BIT |
600 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_RDP << 8), 0))
601 {
602 return FALSE;
603 }
604
605 return TRUE;
606 }
607 #endif
608
609 /*---------------------------------------------------------------------------*
610 Name: SPI_NvramChipErase
611
612 Description: Issues "chip erase" command to NVRAM.
613 This is enabled for LE25FW203T devices.
614 Ignored when device is M45PE40.
615
616 Arguments: None.
617
618 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
619
620 *---------------------------------------------------------------------------*/
SPI_NvramChipErase(void)621 static inline BOOL SPI_NvramChipErase(void)
622 {
623 // Send packet [0]
624 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
625 SPI_PXI_START_BIT |
626 SPI_PXI_END_BIT |
627 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_CE << 8), 0))
628 {
629 return FALSE;
630 }
631
632 return TRUE;
633 }
634
635 /*---------------------------------------------------------------------------*
636 Name: SPI_NvramReadSiliconId
637
638 Description: Issues "read silicon ID" command to NVRAM.
639 This is enabled for LE25FW203T devices.
640 Ignored when device is M45PE40.
641
642 Arguments: pData - Specifies a 2-byte buffer for storing the silicon ID.
643 The ARM7 directly writes the value so be careful of the cache.
644
645 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
646
647 *---------------------------------------------------------------------------*/
SPI_NvramReadSiliconId(u8 * pData)648 static inline BOOL SPI_NvramReadSiliconId(u8 *pData)
649 {
650 // Send packet [0]
651 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
652 SPI_PXI_START_BIT |
653 (0 << SPI_PXI_INDEX_SHIFT) |
654 (SPI_PXI_COMMAND_NVRAM_RSI << 8) | ((u32)pData >> 24), 0))
655 {
656 return FALSE;
657 }
658
659 // Send packet [1]
660 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
661 (1 << SPI_PXI_INDEX_SHIFT) | (((u32)pData >> 8) & 0x0000ffff), 0))
662 {
663 return FALSE;
664 }
665
666 // Send packet [2]
667 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
668 SPI_PXI_END_BIT |
669 (2 << SPI_PXI_INDEX_SHIFT) | (((u32)pData << 8) & 0x0000ff00), 0))
670 {
671 return FALSE;
672 }
673
674 return TRUE;
675 }
676
677 /*---------------------------------------------------------------------------*
678 Name: SPI_NvramSoftwareReset
679
680 Description: Issues "software reset" command to NVRAM.
681 This is enabled for LE25FW203T devices.
682 Ignored when device is M45PE40.
683
684 Arguments: None.
685
686 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
687
688 *---------------------------------------------------------------------------*/
SPI_NvramSoftwareReset(void)689 static inline BOOL SPI_NvramSoftwareReset(void)
690 {
691 // Send packet [0]
692 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_NVRAM,
693 SPI_PXI_START_BIT |
694 SPI_PXI_END_BIT |
695 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_NVRAM_SR << 8), 0))
696 {
697 return FALSE;
698 }
699
700 return TRUE;
701 }
702
703 /*---------------------------------------------------------------------------*
704 Name: SPI_MicSamplingNow
705
706 Description: Samples the microphone once.
707
708 Arguments: type - sampling type (0: 8-bit, 1: 12-bit)
709 pData - Memory address that stores sampling results
710 -> Delete
711
712 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
713
714 *---------------------------------------------------------------------------*/
SPI_MicSamplingNow(u8 type)715 static inline BOOL SPI_MicSamplingNow(u8 type)
716 {
717 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
718 SPI_PXI_START_BIT |
719 SPI_PXI_END_BIT |
720 (0 << SPI_PXI_INDEX_SHIFT) |
721 (SPI_PXI_COMMAND_MIC_SAMPLING << 8) | (u32)type, 0))
722 {
723 return FALSE;
724 }
725
726 return TRUE;
727 }
728
729 /*---------------------------------------------------------------------------*
730 Name: SPI_MicAutoSamplingOn
731
732 Description: Starts auto-sampling with the microphone.
733
734 Arguments: pData - Buffer address that stores sampled data
735 size - Buffer size. Specified in byte units.
736 span - sampling interval (specify with ARM7 CPU clock)
737 Timer characteristics allow only 1, 64, 256, or 1024 times 16 bits to be be set accurately.
738 Bits at the end are truncated.
739 middle - Sampling times that returns response during process.
740 -> Delete
741 adMode - specify AD conversion bit ( 8 or 12 ).
742 loopMode - Auto-sampling loop control determination.
743 correct - Tick correction determination during auto-sampling.
744
745 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
746
747 *---------------------------------------------------------------------------*/
SPI_MicAutoSamplingOn(void * pData,u32 size,u32 span,u8 adMode,BOOL loopMode,BOOL correct)748 static inline BOOL SPI_MicAutoSamplingOn(void *pData, u32 size, u32 span,
749 // u32 middle ,
750 u8 adMode, BOOL loopMode, BOOL correct)
751 {
752 u8 temp;
753
754 // Combine flag types in "type" variable
755 switch (adMode) // AD conversion bit width specification
756 {
757 case SPI_MIC_SAMPLING_TYPE_8BIT:
758 case SPI_MIC_SAMPLING_TYPE_12BIT:
759 temp = adMode;
760 break;
761 default:
762 return FALSE;
763 }
764 if (loopMode) // Continuous sampling loop specification
765 {
766 temp |= (u8)SPI_MIC_SAMPLING_TYPE_LOOP_ON;
767 }
768 if (correct) // Apply correction logic specification due to Tick error
769 {
770 temp |= (u8)SPI_MIC_SAMPLING_TYPE_CORRECT_ON;
771 }
772
773 // Send packet [0]
774 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
775 SPI_PXI_START_BIT |
776 (0 << SPI_PXI_INDEX_SHIFT) |
777 (SPI_PXI_COMMAND_MIC_AUTO_ON << 8) | (u32)temp, 0))
778 {
779 return FALSE;
780 }
781
782 // Send packet [1]
783 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
784 (1 << SPI_PXI_INDEX_SHIFT) | ((u32)pData >> 16), 0))
785 {
786 return FALSE;
787 }
788
789 // Send packet [2]
790 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
791 (2 << SPI_PXI_INDEX_SHIFT) | ((u32)pData & 0x0000ffff), 0))
792 {
793 return FALSE;
794 }
795
796 // Send packet [3]
797 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC, (3 << SPI_PXI_INDEX_SHIFT) | (size >> 16), 0))
798 {
799 return FALSE;
800 }
801
802 // Send packet [4]
803 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
804 (4 << SPI_PXI_INDEX_SHIFT) | (size & 0x0000ffff), 0))
805 {
806 return FALSE;
807 }
808
809 // Send packet [5]
810 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC, (5 << SPI_PXI_INDEX_SHIFT) | (span >> 16), 0))
811 {
812 return FALSE;
813 }
814
815 // Send packet [6]
816 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
817 SPI_PXI_END_BIT |
818 (6 << SPI_PXI_INDEX_SHIFT) | (span & 0x0000ffff), 0))
819 {
820 return FALSE;
821 }
822
823 return TRUE;
824 }
825
826 /*---------------------------------------------------------------------------*
827 Name: SPI_MicAutoSamplingOff
828
829 Description: Stops auto-sampling with the microphone.
830 If loop playback was not specified at the beginning, it will stop automatically when the buffer is full.
831
832
833 Arguments: None.
834
835 Returns: BOOL - Returns TRUE when the command was successfully sent via PXI and FALSE on failure.
836
837 *---------------------------------------------------------------------------*/
SPI_MicAutoSamplingOff(void)838 static inline BOOL SPI_MicAutoSamplingOff(void)
839 {
840 // Send packet [0]
841 if (0 > PXI_SendWordByFifo(PXI_FIFO_TAG_MIC,
842 SPI_PXI_START_BIT |
843 SPI_PXI_END_BIT |
844 (0 << SPI_PXI_INDEX_SHIFT) | (SPI_PXI_COMMAND_MIC_AUTO_OFF << 8), 0))
845 {
846 return FALSE;
847 }
848
849 return TRUE;
850 }
851
852 #endif /* SDK_ARM9 */
853
854 /*===========================================================================*/
855
856 #ifdef __cplusplus
857 } /* extern "C" */
858 #endif
859
860 #endif /* LIBRARIES_SPI_H_ */
861
862 /*---------------------------------------------------------------------------*
863 End of file
864 *---------------------------------------------------------------------------*/
865