1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - SPI - include 3 File: type.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-01-11#$ 14 $Rev: 3502 $ 15 $Author: yada $ 16 *---------------------------------------------------------------------------*/ 17 #ifndef NITRO_SPI_COMMON_TYPE_H_ 18 #define NITRO_SPI_COMMON_TYPE_H_ 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /*===========================================================================*/ 25 26 /*---------------------------------------------------------------------------* 27 Constant Definitions 28 *---------------------------------------------------------------------------*/ 29 // Definitions related to PXI communications protocol 30 #define SPI_PXI_START_BIT 0x02000000 // Consecutive packet start bit 31 #define SPI_PXI_END_BIT 0x01000000 // Consecutive packet completion bit 32 #define SPI_PXI_INDEX_MASK 0x000f0000 // Defines the placement of bits that show the index of consecutive packets 33 #define SPI_PXI_INDEX_SHIFT 16 // 34 #define SPI_PXI_DATA_MASK 0x0000ffff // Defines the placement of bits that indicate the data portion of consecutive packets 35 #define SPI_PXI_DATA_SHIFT 0 // 36 #define SPI_PXI_RESULT_COMMAND_BIT 0x00008000 // Bit that indicates response 37 #define SPI_PXI_RESULT_COMMAND_MASK 0x00007f00 // Defines the placement of bits for response command type 38 #define SPI_PXI_RESULT_COMMAND_SHIFT 8 // 39 #define SPI_PXI_RESULT_DATA_MASK 0x000000ff // Defines the placement of bits for response command results 40 #define SPI_PXI_RESULT_DATA_SHIFT 0 // 41 #define SPI_PXI_CONTINUOUS_PACKET_MAX 16 // Maximum number of consecutive packets in succession 42 43 // Instruction group issued by ARM9 via PXI (those with the 0x10 bit set to 1 are notification commands from ARM7) 44 #define SPI_PXI_COMMAND_TP_SAMPLING 0x0000 45 #define SPI_PXI_COMMAND_TP_AUTO_ON 0x0001 46 #define SPI_PXI_COMMAND_TP_AUTO_OFF 0x0002 47 #define SPI_PXI_COMMAND_TP_SETUP_STABILITY 0x0003 48 #define SPI_PXI_COMMAND_TP_AUTO_SAMPLING 0x0010 // For midway notifications during the course of auto sampling 49 50 #define SPI_PXI_COMMAND_NVRAM_WREN 0x0020 51 #define SPI_PXI_COMMAND_NVRAM_WRDI 0x0021 52 #define SPI_PXI_COMMAND_NVRAM_RDSR 0x0022 53 #define SPI_PXI_COMMAND_NVRAM_READ 0x0023 54 #define SPI_PXI_COMMAND_NVRAM_FAST_READ 0x0024 55 #define SPI_PXI_COMMAND_NVRAM_PW 0x0025 56 #define SPI_PXI_COMMAND_NVRAM_PP 0x0026 57 #define SPI_PXI_COMMAND_NVRAM_PE 0x0027 58 #define SPI_PXI_COMMAND_NVRAM_SE 0x0028 59 #define SPI_PXI_COMMAND_NVRAM_DP 0x0029 60 #define SPI_PXI_COMMAND_NVRAM_RDP 0x002a 61 #define SPI_PXI_COMMAND_NVRAM_CE 0x002b 62 #define SPI_PXI_COMMAND_NVRAM_RSI 0x002c 63 #define SPI_PXI_COMMAND_NVRAM_SR 0x002d 64 65 #define SPI_PXI_COMMAND_MIC_SAMPLING 0x0040 66 #define SPI_PXI_COMMAND_MIC_AUTO_ON 0x0041 67 #define SPI_PXI_COMMAND_MIC_AUTO_OFF 0x0042 68 #define SPI_PXI_COMMAND_MIC_AUTO_ADJUST 0x0043 69 #ifdef SDK_TWL 70 #define SPI_PXI_COMMAND_MIC_LTDAUTO_ON 0x0044 71 #define SPI_PXI_COMMAND_MIC_LTDAUTO_OFF 0x0045 72 #define SPI_PXI_COMMAND_MIC_LTDAUTO_ADJUST 0x0046 73 #endif 74 #define SPI_PXI_COMMAND_MIC_BUFFER_FULL 0x0051 75 76 // for PM 77 #define SPI_PXI_COMMAND_PM_SYNC 0x0060 78 #define SPI_PXI_COMMAND_PM_UTILITY 0x0061 79 #define SPI_PXI_COMMAND_PM_SLEEP_START 0x0062 80 #define SPI_PXI_COMMAND_PM_SLEEP_END 0x0063 81 #define SPI_PXI_COMMAND_PM_SET_LED 0x0064 82 #ifdef SDK_TWL 83 #define SPI_PXI_COMMAND_PM_NOTIFY 0x0070 84 #endif 85 86 87 // Response groups returned by ARM7 via PXI 88 #define SPI_PXI_RESULT_SUCCESS 0x0000 // Success 89 #define SPI_PXI_RESULT_INVALID_COMMAND 0x0001 // Instruction is abnormal 90 #define SPI_PXI_RESULT_INVALID_PARAMETER 0x0002 // Parameter is abnormal 91 #define SPI_PXI_RESULT_ILLEGAL_STATUS 0x0003 // State that cannot receive instructions 92 #define SPI_PXI_RESULT_EXCLUSIVE 0x0004 // SPI device is in exclusion 93 94 95 // Touch panel-related definitions 96 #define SPI_TP_SAMPLING_FREQUENCY_MAX 4 // Max value of auto sampling frequency 97 #define SPI_TP_DEFAULT_STABILITY_RANGE 20 // Output range difference that is permitted when the stability is determined (initial value) 98 #define SPI_TP_VALARM_TAG 0x54505641 // "TPVA" --V alarm tag for TP-use 99 100 // NVRAM (Flash ROM)-related definitions 101 #define SPI_NVRAM_PAGE_SIZE 256 102 #define SPI_NVRAM_SECTOR_SIZE ( SPI_NVRAM_PAGE_SIZE * 256 ) 103 #define SPI_NVRAM_ALL_SIZE ( SPI_NVRAM_SECTOR_SIZE * 8 ) 104 105 // Microphone-related definitions 106 #define SPI_MIC_SAMPLING_TYPE_8BIT 0x0000 107 #define SPI_MIC_SAMPLING_TYPE_12BIT 0x0001 108 #define SPI_MIC_SAMPLING_TYPE_S8BIT 0x0002 109 #define SPI_MIC_SAMPLING_TYPE_S12BIT 0x0003 110 #define SPI_MIC_SAMPLING_TYPE_FILTER_ON 0x0000 111 #define SPI_MIC_SAMPLING_TYPE_FILTER_OFF 0x0004 112 #define SPI_MIC_SAMPLING_TYPE_ADMODE_MASK 0x0007 113 #define SPI_MIC_SAMPLING_TYPE_BIT_MASK 0x0001 114 #define SPI_MIC_SAMPLING_TYPE_SIGNED_MASK 0x0002 115 #define SPI_MIC_SAMPLING_TYPE_FILTER_MASK 0x0004 116 117 #define SPI_MIC_SAMPLING_TYPE_LOOP_OFF 0x0000 118 #define SPI_MIC_SAMPLING_TYPE_LOOP_ON 0x0010 119 #define SPI_MIC_SAMPLING_TYPE_LOOP_MASK 0x0010 120 121 #define SPI_MIC_SAMPLING_TYPE_CORRECT_OFF 0x0000 122 #define SPI_MIC_SAMPLING_TYPE_CORRECT_ON 0x0020 123 #define SPI_MIC_SAMPLING_TYPE_CORRECT_MASK 0x0020 124 125 #define SPI_MIC_SAMPLING_TYPE_MIX_TP_OFF 0x0000 126 #define SPI_MIC_SAMPLING_TYPE_MIX_TP_ON 0x0040 127 #define SPI_MIC_SAMPLING_TYPE_MIX_TP_MASK 0x0040 128 129 130 /*---------------------------------------------------------------------------* 131 Structure Definitions 132 *---------------------------------------------------------------------------*/ 133 // SPI-related Device Types 134 typedef enum SPIDeviceType 135 { 136 SPI_DEVICE_TYPE_TP = 0, // Touch panel 137 SPI_DEVICE_TYPE_NVRAM, // NVRAM (Flash ROM) 138 SPI_DEVICE_TYPE_MIC, // Microphone 139 SPI_DEVICE_TYPE_PM, // Power management IC 140 SPI_DEVICE_TYPE_ARM7, 141 SPI_DEVICE_TYPE_MAX 142 } 143 SPIDeviceType; 144 145 // Touch panel contact yes/no 146 typedef enum SPITpTouch 147 { 148 SPI_TP_TOUCH_OFF = 0, 149 SPI_TP_TOUCH_ON 150 } 151 SPITpTouch; 152 153 // Touch panel data validity yes/no 154 typedef enum SPITpValidity 155 { 156 SPI_TP_VALIDITY_VALID = 0, 157 SPI_TP_VALIDITY_INVALID_X, 158 SPI_TP_VALIDITY_INVALID_Y, 159 SPI_TP_VALIDITY_INVALID_XY 160 } 161 SPITpValidity; 162 163 // Touch panel input structure 164 typedef union SPITpData 165 { 166 struct 167 { 168 u32 x:12; 169 u32 y:12; 170 u32 touch:1; 171 u32 validity:2; 172 u32 dummy:5; 173 174 } 175 e; 176 u32 raw; 177 u8 bytes[4]; 178 u16 halfs[2]; 179 180 } 181 SPITpData; 182 183 184 /*===========================================================================*/ 185 186 #ifdef __cplusplus 187 } /* extern "C" */ 188 #endif 189 190 #endif /* NITRO_SPI_COMMON_TYPE_H_ */ 191 192 /*---------------------------------------------------------------------------* 193 End of file 194 *---------------------------------------------------------------------------*/ 195