1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_SCFG.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_SCFG_H_ 18 #define TWL_HW_ARM9_IOREG_SCFG_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* A9ROM */ 35 36 #define REG_A9ROM_OFFSET 0x4000 37 #define REG_A9ROM_ADDR (HW_REG_BASE + REG_A9ROM_OFFSET) 38 #define reg_SCFG_A9ROM (*(const REGType8v *) REG_A9ROM_ADDR) 39 40 /* CLK */ 41 42 #define REG_CLK_OFFSET 0x4004 43 #define REG_CLK_ADDR (HW_REG_BASE + REG_CLK_OFFSET) 44 #define reg_SCFG_CLK (*( REGType16v *) REG_CLK_ADDR) 45 46 /* RST */ 47 48 #define REG_RST_OFFSET 0x4006 49 #define REG_RST_ADDR (HW_REG_BASE + REG_RST_OFFSET) 50 #define reg_SCFG_RST (*( REGType16v *) REG_RST_ADDR) 51 52 /* EXT */ 53 54 #define REG_EXT_OFFSET 0x4008 55 #define REG_EXT_ADDR (HW_REG_BASE + REG_EXT_OFFSET) 56 #define reg_SCFG_EXT (*( REGType32v *) REG_EXT_ADDR) 57 58 59 /* 60 * Definitions of Register fields 61 */ 62 63 64 /* A9ROM */ 65 66 #define REG_SCFG_A9ROM_RSEL_SHIFT 1 67 #define REG_SCFG_A9ROM_RSEL_SIZE 1 68 #define REG_SCFG_A9ROM_RSEL_MASK 0x02 69 70 #define REG_SCFG_A9ROM_SEC_SHIFT 0 71 #define REG_SCFG_A9ROM_SEC_SIZE 1 72 #define REG_SCFG_A9ROM_SEC_MASK 0x01 73 74 #ifndef SDK_ASM 75 #define REG_SCFG_A9ROM_FIELD( rsel, sec ) \ 76 (u8)( \ 77 ((u32)(rsel) << REG_SCFG_A9ROM_RSEL_SHIFT) | \ 78 ((u32)(sec) << REG_SCFG_A9ROM_SEC_SHIFT)) 79 #endif 80 81 82 /* CLK */ 83 84 #define REG_SCFG_CLK_CAMCKI_SHIFT 8 85 #define REG_SCFG_CLK_CAMCKI_SIZE 1 86 #define REG_SCFG_CLK_CAMCKI_MASK 0x0100 87 88 #define REG_SCFG_CLK_WRAMHCLK_SHIFT 7 89 #define REG_SCFG_CLK_WRAMHCLK_SIZE 1 90 #define REG_SCFG_CLK_WRAMHCLK_MASK 0x0080 91 92 #define REG_SCFG_CLK_CAMHCLK_SHIFT 2 93 #define REG_SCFG_CLK_CAMHCLK_SIZE 1 94 #define REG_SCFG_CLK_CAMHCLK_MASK 0x0004 95 96 #define REG_SCFG_CLK_DSPHCLK_SHIFT 1 97 #define REG_SCFG_CLK_DSPHCLK_SIZE 1 98 #define REG_SCFG_CLK_DSPHCLK_MASK 0x0002 99 100 #define REG_SCFG_CLK_CPUSPD_SHIFT 0 101 #define REG_SCFG_CLK_CPUSPD_SIZE 1 102 #define REG_SCFG_CLK_CPUSPD_MASK 0x0001 103 104 #ifndef SDK_ASM 105 #define REG_SCFG_CLK_FIELD( camcki, wramhclk, camhclk, dsphclk, cpuspd ) \ 106 (u16)( \ 107 ((u32)(camcki) << REG_SCFG_CLK_CAMCKI_SHIFT) | \ 108 ((u32)(wramhclk) << REG_SCFG_CLK_WRAMHCLK_SHIFT) | \ 109 ((u32)(camhclk) << REG_SCFG_CLK_CAMHCLK_SHIFT) | \ 110 ((u32)(dsphclk) << REG_SCFG_CLK_DSPHCLK_SHIFT) | \ 111 ((u32)(cpuspd) << REG_SCFG_CLK_CPUSPD_SHIFT)) 112 #endif 113 114 115 /* RST */ 116 117 #define REG_SCFG_RST_DSPRSTB_SHIFT 0 118 #define REG_SCFG_RST_DSPRSTB_SIZE 1 119 #define REG_SCFG_RST_DSPRSTB_MASK 0x0001 120 121 #ifndef SDK_ASM 122 #define REG_SCFG_RST_FIELD( dsprstb ) \ 123 (u16)( \ 124 ((u32)(dsprstb) << REG_SCFG_RST_DSPRSTB_SHIFT)) 125 #endif 126 127 128 /* EXT */ 129 130 #define REG_SCFG_EXT_CFG_SHIFT 31 131 #define REG_SCFG_EXT_CFG_SIZE 1 132 #define REG_SCFG_EXT_CFG_MASK 0x80000000 133 134 #define REG_SCFG_EXT_WRAM_SHIFT 25 135 #define REG_SCFG_EXT_WRAM_SIZE 1 136 #define REG_SCFG_EXT_WRAM_MASK 0x02000000 137 138 #define REG_SCFG_EXT_MC_B_SHIFT 24 139 #define REG_SCFG_EXT_MC_B_SIZE 1 140 #define REG_SCFG_EXT_MC_B_MASK 0x01000000 141 142 #define REG_SCFG_EXT_DSP_SHIFT 18 143 #define REG_SCFG_EXT_DSP_SIZE 1 144 #define REG_SCFG_EXT_DSP_MASK 0x00040000 145 146 #define REG_SCFG_EXT_CAM_SHIFT 17 147 #define REG_SCFG_EXT_CAM_SIZE 1 148 #define REG_SCFG_EXT_CAM_MASK 0x00020000 149 150 #define REG_SCFG_EXT_DMAC_SHIFT 16 151 #define REG_SCFG_EXT_DMAC_SIZE 1 152 #define REG_SCFG_EXT_DMAC_MASK 0x00010000 153 154 #define REG_SCFG_EXT_PSRAM_SHIFT 14 155 #define REG_SCFG_EXT_PSRAM_SIZE 2 156 #define REG_SCFG_EXT_PSRAM_MASK 0x0000c000 157 158 #define REG_SCFG_EXT_VRAM_SHIFT 13 159 #define REG_SCFG_EXT_VRAM_SIZE 1 160 #define REG_SCFG_EXT_VRAM_MASK 0x00002000 161 162 #define REG_SCFG_EXT_LCDC_SHIFT 12 163 #define REG_SCFG_EXT_LCDC_SIZE 1 164 #define REG_SCFG_EXT_LCDC_MASK 0x00001000 165 166 #define REG_SCFG_EXT_INTC_SHIFT 8 167 #define REG_SCFG_EXT_INTC_SIZE 1 168 #define REG_SCFG_EXT_INTC_MASK 0x00000100 169 170 #define REG_SCFG_EXT_MC_SHIFT 7 171 #define REG_SCFG_EXT_MC_SIZE 1 172 #define REG_SCFG_EXT_MC_MASK 0x00000080 173 174 #define REG_SCFG_EXT_DIV_SHIFT 4 175 #define REG_SCFG_EXT_DIV_SIZE 1 176 #define REG_SCFG_EXT_DIV_MASK 0x00000010 177 178 #define REG_SCFG_EXT_G2DE_SHIFT 3 179 #define REG_SCFG_EXT_G2DE_SIZE 1 180 #define REG_SCFG_EXT_G2DE_MASK 0x00000008 181 182 #define REG_SCFG_EXT_REN_SHIFT 2 183 #define REG_SCFG_EXT_REN_SIZE 1 184 #define REG_SCFG_EXT_REN_MASK 0x00000004 185 186 #define REG_SCFG_EXT_GEO_SHIFT 1 187 #define REG_SCFG_EXT_GEO_SIZE 1 188 #define REG_SCFG_EXT_GEO_MASK 0x00000002 189 190 #define REG_SCFG_EXT_DMA_SHIFT 0 191 #define REG_SCFG_EXT_DMA_SIZE 1 192 #define REG_SCFG_EXT_DMA_MASK 0x00000001 193 194 #ifndef SDK_ASM 195 #define REG_SCFG_EXT_FIELD( cfg, wram, mc_b, dsp, cam, dmac, psram, vram, lcdc, intc, mc, div, g2de, ren, geo, dma ) \ 196 (u32)( \ 197 ((u32)(cfg) << REG_SCFG_EXT_CFG_SHIFT) | \ 198 ((u32)(wram) << REG_SCFG_EXT_WRAM_SHIFT) | \ 199 ((u32)(mc_b) << REG_SCFG_EXT_MC_B_SHIFT) | \ 200 ((u32)(dsp) << REG_SCFG_EXT_DSP_SHIFT) | \ 201 ((u32)(cam) << REG_SCFG_EXT_CAM_SHIFT) | \ 202 ((u32)(dmac) << REG_SCFG_EXT_DMAC_SHIFT) | \ 203 ((u32)(psram) << REG_SCFG_EXT_PSRAM_SHIFT) | \ 204 ((u32)(vram) << REG_SCFG_EXT_VRAM_SHIFT) | \ 205 ((u32)(lcdc) << REG_SCFG_EXT_LCDC_SHIFT) | \ 206 ((u32)(intc) << REG_SCFG_EXT_INTC_SHIFT) | \ 207 ((u32)(mc) << REG_SCFG_EXT_MC_SHIFT) | \ 208 ((u32)(div) << REG_SCFG_EXT_DIV_SHIFT) | \ 209 ((u32)(g2de) << REG_SCFG_EXT_G2DE_SHIFT) | \ 210 ((u32)(ren) << REG_SCFG_EXT_REN_SHIFT) | \ 211 ((u32)(geo) << REG_SCFG_EXT_GEO_SHIFT) | \ 212 ((u32)(dma) << REG_SCFG_EXT_DMA_SHIFT)) 213 #endif 214 215 216 #ifdef __cplusplus 217 } /* extern "C" */ 218 #endif 219 220 /* TWL_HW_ARM9_IOREG_SCFG_H_ */ 221 #endif 222