Searched refs:REG_MI_DMA0CNT_SAR_SHIFT (Results 1 – 3 of 3) sorted by relevance
226 #define REG_MI_DMA0CNT_SAR_SHIFT 23 macro246 ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \
81 #define MI_DMA_SRC_INC (0UL << REG_MI_DMA0CNT_SAR_SHIFT) // increment source address82 #define MI_DMA_SRC_DEC (1UL << REG_MI_DMA0CNT_SAR_SHIFT) // decrement source address83 #define MI_DMA_SRC_FIX (2UL << REG_MI_DMA0CNT_SAR_SHIFT) // fix source address
706 #define REG_MI_DMA0CNT_SAR_SHIFT 23 macro726 ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \