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Searched refs:REG_MBK_C0_ADDR (Results 1 – 3 of 3) sorted by relevance

/TwlSDK-5.1.0/build/libraries/mi/common.TWL/src/
Dmi_sharedWram.c103 *(vu8*)(REG_MBK_C0_ADDR + num) in MIi_SetWramBank_C()
143 return *(vu8*)(REG_MBK_C0_ADDR + num); in MIi_GetWramBank_C()
190 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num); in MIi_SetWramBankMaster_C()
238 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num); in MIi_SetWramBankEnable_C()
282 return (MIWramProc)( *(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_MASTER_MASK_C ); in MI_GetWramBankMaster_C()
334 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_OFFSET_MASK_C) >> MI_WRAM_O… in MI_GetWramBankOffset_C()
373 …return (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_ENABLE_MASK_C)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_C()
/TwlSDK-5.1.0/build/libraries/dsp/ARM9.TWL/src/
Ddsp_process.c207 … vu8 *bank = &((vu8*)((wram == MI_WRAM_B) ? REG_MBK_B0_ADDR : REG_MBK_C0_ADDR))[slot]; in DSPi_CommitWram()
/TwlSDK-5.1.0/include/twl/hw/ARM9/
Dioreg_MI.h559 #define REG_MBK_C0_ADDR (HW_REG_BASE + REG_MBK_C0_OFFSET) macro
560 #define reg_MI_MBK_C0 (*( REGType8v *) REG_MBK_C0_ADDR)