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Searched refs:REG_DMA0SAD_ADDR (Results 1 – 9 of 9) sorted by relevance

/TwlSDK-5.1.0/build/libraries/os/common/include/
Dmi_dma.h61 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams()
71 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait()
86 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_noInt()
94 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait_noInt()
171 dmaCntp = &((vu32*)REG_DMA0SAD_ADDR)[dmaNo * 3 + 2]; \
Ddma_red.h45 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
54 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
349 vu32 *(dmaCntp) = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
365 vu16* dmaCntp = &((vu16 *)REG_DMA0SAD_ADDR)[dmaNo * 6]; \
/TwlSDK-5.1.0/build/libraries/init/common/include/
Dmi_dma.h61 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams()
71 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait()
86 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_noInt()
94 vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12); in MIi_DmaSetParams_wait_noInt()
171 dmaCntp = &((vu32*)REG_DMA0SAD_ADDR)[dmaNo * 3 + 2]; \
Ddma_red.h45 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
54 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
349 vu32 *(dmaCntp) = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
365 vu16* dmaCntp = &((vu16 *)REG_DMA0SAD_ADDR)[dmaNo * 6]; \
/TwlSDK-5.1.0/build/libraries/mi/common/include/
Ddma_red.h45 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
54 vu32 *dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
349 vu32 *(dmaCntp) = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3]; \
365 vu16* dmaCntp = &((vu16 *)REG_DMA0SAD_ADDR)[dmaNo * 6]; \
Dmi_dma.h74 dmaCntp = &((vu32*)REG_DMA0SAD_ADDR)[dmaNo * 3 + 2]; \
/TwlSDK-5.1.0/include/nitro/hw/ARM9/
Dioreg_MI.h37 #define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) macro
38 #define reg_MI_DMA0SAD (*( REGType32v *) REG_DMA0SAD_ADDR)
/TwlSDK-5.1.0/include/nitro/mi/
Ddma.h101 #define MI_DMA_REGADDR(dmaNo, reg) (((vu32*)REG_DMA0SAD_ADDR) + MI_DMA_NUM_WOFFSET(dmaNo) + (reg…
/TwlSDK-5.1.0/include/twl/hw/ARM9/
Dioreg_MI.h37 #define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) macro
38 #define reg_MI_DMA0SAD (*( REGType32v *) REG_DMA0SAD_ADDR)