1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_CFG.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_CFG_H_ 18 #define NITRO_HW_ARM9_IOREG_CFG_H_ 19 20 #ifndef SDK_ASM 21 #include <twl/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* A9ROM */ 35 36 #define REG_A9ROM_OFFSET 0x4000 37 #define REG_A9ROM_ADDR (HW_REG_BASE + REG_A9ROM_OFFSET) 38 #define reg_CFG_A9ROM (*( REGType8v *) REG_A9ROM_ADDR) 39 40 /* CLK */ 41 42 #define REG_CLK_OFFSET 0x4004 43 #define REG_CLK_ADDR (HW_REG_BASE + REG_CLK_OFFSET) 44 #define reg_CFG_CLK (*( REGType16v *) REG_CLK_ADDR) 45 46 /* DSP_RST */ 47 48 #define REG_DSP_RST_OFFSET 0x4006 49 #define REG_DSP_RST_ADDR (HW_REG_BASE + REG_DSP_RST_OFFSET) 50 #define reg_CFG_DSP_RST (*( REGType8v *) REG_DSP_RST_ADDR) 51 52 /* DS_MDFY */ 53 54 #define REG_DS_MDFY_OFFSET 0x4008 55 #define REG_DS_MDFY_ADDR (HW_REG_BASE + REG_DS_MDFY_OFFSET) 56 #define reg_CFG_DS_MDFY (*( REGType8v *) REG_DS_MDFY_ADDR) 57 58 /* DS_EX */ 59 60 #define REG_DS_EX_OFFSET 0x4009 61 #define REG_DS_EX_ADDR (HW_REG_BASE + REG_DS_EX_OFFSET) 62 #define reg_CFG_DS_EX (*( REGType8v *) REG_DS_EX_ADDR) 63 64 /* TWL_EX */ 65 66 #define REG_TWL_EX_OFFSET 0x400a 67 #define REG_TWL_EX_ADDR (HW_REG_BASE + REG_TWL_EX_OFFSET) 68 #define reg_CFG_TWL_EX (*( REGType16v *) REG_TWL_EX_ADDR) 69 70 71 /* 72 * Definitions of Register fields 73 */ 74 75 76 /* A9ROM */ 77 78 #define REG_CFG_A9ROM_NTR_SHIFT 1 79 #define REG_CFG_A9ROM_NTR_SIZE 1 80 #define REG_CFG_A9ROM_NTR_MASK 0x02 81 82 #define REG_CFG_A9ROM_SEC_SHIFT 0 83 #define REG_CFG_A9ROM_SEC_SIZE 1 84 #define REG_CFG_A9ROM_SEC_MASK 0x01 85 86 #ifndef SDK_ASM 87 #define REG_CFG_A9ROM_FIELD( ntr, sec ) \ 88 (u8)( \ 89 ((u32)(ntr) << REG_CFG_A9ROM_NTR_SHIFT) | \ 90 ((u32)(sec) << REG_CFG_A9ROM_SEC_SHIFT)) 91 #endif 92 93 94 /* CLK */ 95 96 #define REG_CFG_CLK_CAM_CKI_SHIFT 8 97 #define REG_CFG_CLK_CAM_CKI_SIZE 1 98 #define REG_CFG_CLK_CAM_CKI_MASK 0x0100 99 100 #define REG_CFG_CLK_WRAM_SHIFT 7 101 #define REG_CFG_CLK_WRAM_SIZE 1 102 #define REG_CFG_CLK_WRAM_MASK 0x0080 103 104 #define REG_CFG_CLK_CAM_SHIFT 2 105 #define REG_CFG_CLK_CAM_SIZE 1 106 #define REG_CFG_CLK_CAM_MASK 0x0004 107 108 #define REG_CFG_CLK_DSP_SHIFT 1 109 #define REG_CFG_CLK_DSP_SIZE 0 110 #define REG_CFG_CLK_DSP_MASK 0x0002 111 112 #define REG_CFG_CLK_ARM2X_SHIFT 0 113 #define REG_CFG_CLK_ARM2X_SIZE 1 114 #define REG_CFG_CLK_ARM2X_MASK 0x0001 115 116 #ifndef SDK_ASM 117 #define REG_CFG_CLK_FIELD( cam_cki, wram, cam, dsp, arm2x ) \ 118 (u16)( \ 119 ((u32)(cam_cki) << REG_CFG_CLK_CAM_CKI_SHIFT) | \ 120 ((u32)(wram) << REG_CFG_CLK_WRAM_SHIFT) | \ 121 ((u32)(cam) << REG_CFG_CLK_CAM_SHIFT) | \ 122 ((u32)(dsp) << REG_CFG_CLK_DSP_SHIFT) | \ 123 ((u32)(arm2x) << REG_CFG_CLK_ARM2X_SHIFT)) 124 #endif 125 126 127 /* DSP_RST */ 128 129 #define REG_CFG_DSP_RST_OFF_SHIFT 0 130 #define REG_CFG_DSP_RST_OFF_SIZE 1 131 #define REG_CFG_DSP_RST_OFF_MASK 0x01 132 133 #ifndef SDK_ASM 134 #define REG_CFG_DSP_RST_FIELD( off ) \ 135 (u8)( \ 136 ((u32)(off) << REG_CFG_DSP_RST_OFF_SHIFT)) 137 #endif 138 139 140 /* DS_MDFY */ 141 142 #define REG_CFG_DS_MDFY_MC_SHIFT 7 143 #define REG_CFG_DS_MDFY_MC_SIZE 1 144 #define REG_CFG_DS_MDFY_MC_MASK 0x80 145 146 #define REG_CFG_DS_MDFY_DIV_SHIFT 4 147 #define REG_CFG_DS_MDFY_DIV_SIZE 1 148 #define REG_CFG_DS_MDFY_DIV_MASK 0x10 149 150 #define REG_CFG_DS_MDFY_G2_SHIFT 3 151 #define REG_CFG_DS_MDFY_G2_SIZE 1 152 #define REG_CFG_DS_MDFY_G2_MASK 0x08 153 154 #define REG_CFG_DS_MDFY_REN_SHIFT 2 155 #define REG_CFG_DS_MDFY_REN_SIZE 1 156 #define REG_CFG_DS_MDFY_REN_MASK 0x04 157 158 #define REG_CFG_DS_MDFY_GEO_SHIFT 1 159 #define REG_CFG_DS_MDFY_GEO_SIZE 1 160 #define REG_CFG_DS_MDFY_GEO_MASK 0x02 161 162 #define REG_CFG_DS_MDFY_DMA_SHIFT 0 163 #define REG_CFG_DS_MDFY_DMA_SIZE 1 164 #define REG_CFG_DS_MDFY_DMA_MASK 0x01 165 166 #ifndef SDK_ASM 167 #define REG_CFG_DS_MDFY_FIELD( mc, div, g2, ren, geo, dma ) \ 168 (u8)( \ 169 ((u32)(mc) << REG_CFG_DS_MDFY_MC_SHIFT) | \ 170 ((u32)(div) << REG_CFG_DS_MDFY_DIV_SHIFT) | \ 171 ((u32)(g2) << REG_CFG_DS_MDFY_G2_SHIFT) | \ 172 ((u32)(ren) << REG_CFG_DS_MDFY_REN_SHIFT) | \ 173 ((u32)(geo) << REG_CFG_DS_MDFY_GEO_SHIFT) | \ 174 ((u32)(dma) << REG_CFG_DS_MDFY_DMA_SHIFT)) 175 #endif 176 177 178 /* DS_EX */ 179 180 #define REG_CFG_DS_EX_MAIM_MEM_SHIFT 6 181 #define REG_CFG_DS_EX_MAIM_MEM_SIZE 2 182 #define REG_CFG_DS_EX_MAIM_MEM_MASK 0xc0 183 184 #define REG_CFG_DS_EX_VRAM_SHIFT 5 185 #define REG_CFG_DS_EX_VRAM_SIZE 1 186 #define REG_CFG_DS_EX_VRAM_MASK 0x20 187 188 #define REG_CFG_DS_EX_LCDC_SHIFT 4 189 #define REG_CFG_DS_EX_LCDC_SIZE 1 190 #define REG_CFG_DS_EX_LCDC_MASK 0x10 191 192 #define REG_CFG_DS_EX_INTC_SHIFT 0 193 #define REG_CFG_DS_EX_INTC_SIZE 1 194 #define REG_CFG_DS_EX_INTC_MASK 0x01 195 196 #ifndef SDK_ASM 197 #define REG_CFG_DS_EX_FIELD( maim_mem, vram, lcdc, intc ) \ 198 (u8)( \ 199 ((u32)(maim_mem) << REG_CFG_DS_EX_MAIM_MEM_SHIFT) | \ 200 ((u32)(vram) << REG_CFG_DS_EX_VRAM_SHIFT) | \ 201 ((u32)(lcdc) << REG_CFG_DS_EX_LCDC_SHIFT) | \ 202 ((u32)(intc) << REG_CFG_DS_EX_INTC_SHIFT)) 203 #endif 204 205 206 /* TWL_EX */ 207 208 #define REG_CFG_TWL_EX_CFG_E_SHIFT 15 209 #define REG_CFG_TWL_EX_CFG_E_SIZE 1 210 #define REG_CFG_TWL_EX_CFG_E_MASK 0x8000 211 212 #define REG_CFG_TWL_EX_WRAM_SHIFT 9 213 #define REG_CFG_TWL_EX_WRAM_SIZE 0 214 #define REG_CFG_TWL_EX_WRAM_MASK 0x0200 215 216 #define REG_CFG_TWL_EX_MC_B_SHIFT 8 217 #define REG_CFG_TWL_EX_MC_B_SIZE 1 218 #define REG_CFG_TWL_EX_MC_B_MASK 0x0100 219 220 #define REG_CFG_TWL_EX_DSP_SHIFT 2 221 #define REG_CFG_TWL_EX_DSP_SIZE 1 222 #define REG_CFG_TWL_EX_DSP_MASK 0x0004 223 224 #define REG_CFG_TWL_EX_CAM_SHIFT 1 225 #define REG_CFG_TWL_EX_CAM_SIZE 1 226 #define REG_CFG_TWL_EX_CAM_MASK 0x0002 227 228 #define REG_CFG_TWL_EX_DMA4_SHIFT 0 229 #define REG_CFG_TWL_EX_DMA4_SIZE 1 230 #define REG_CFG_TWL_EX_DMA4_MASK 0x0001 231 232 #ifndef SDK_ASM 233 #define REG_CFG_TWL_EX_FIELD( cfg_e, wram, mc_b, dsp, cam, dma4 ) \ 234 (u16)( \ 235 ((u32)(cfg_e) << REG_CFG_TWL_EX_CFG_E_SHIFT) | \ 236 ((u32)(wram) << REG_CFG_TWL_EX_WRAM_SHIFT) | \ 237 ((u32)(mc_b) << REG_CFG_TWL_EX_MC_B_SHIFT) | \ 238 ((u32)(dsp) << REG_CFG_TWL_EX_DSP_SHIFT) | \ 239 ((u32)(cam) << REG_CFG_TWL_EX_CAM_SHIFT) | \ 240 ((u32)(dma4) << REG_CFG_TWL_EX_DMA4_SHIFT)) 241 #endif 242 243 #ifdef __cplusplus 244 } /* extern "C" */ 245 #endif 246 247 /* NITRO_HW_ARM9_IOREG_CFG_H_ */ 248 #endif 249 250