1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - include - twl - HW 3 File: mmap_shared.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-10-31#$ 14 $Rev: 9171 $ 15 $Author: yada $ 16 *---------------------------------------------------------------------------*/ 17 #ifndef TWL_HW_COMMON_MMAP_SHARED_H_ 18 #define TWL_HW_COMMON_MMAP_SHARED_H_ 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 /*---------------------------------------------------------------------------*/ 23 24 /*----------------------------------------------------------------------* 25 MEMORY MAP of MAIN MEMORY SHARED AREA 26 *----------------------------------------------------------------------*/ 27 /* 28 4K -+------------------------------+- 0x03000000 29 | | 30 | System Shared | 31 | | 32 3K -+------------------------------+- 0x02fffc00 33 | Download Parameter | 34 +------------------------------+- 0x02fffbe0 35 | Card Rom Header | 36 +------------------------------+- 0x02fffa80 37 | Unused | 38 +------------------------------+- 0x02fffa00 39 | RED Reserved | 40 2K -+------------------------------+- 0x02fff800 41 | System Shared 2 | 42 +------------------------------+- 0x02fff680 43 | | 44 | Shared Arena | 45 | | 46 0 -+------------------------------+- 0x02fff000 47 | Booted application RomHeader | 48 -4K -+------------------------------+- 0x02ffe000 49 | Booted application SRL Path | 50 -+------------------------------+- 0x02ffdfc0 51 | FS Mount Parameter | 52 -+------------------------------+- 0x02ffdc00 53 | TitleID list for system use | 54 -+------------------------------+- 0x02ffd800 55 | SD NAND Context buf | 56 -+------------------------------+- 0x02ffd7bc 57 | SysMenuVer. Info | 58 -+------------------------------+- 0x02ffd7b3 59 | Reserved. | 60 -+------------------------------+- 0x02ffd000 61 | TWL CARD ROM HEADER. | 62 -12K -+------------------------------+- 0x02ffc000 63 */ 64 65 /*----------------------------------------------------------------------* 66 TWL CARD ROM HEADER 67 *----------------------------------------------------------------------*/ 68 #define HW_TWL_CARD_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffc000) 69 #define HW_TWL_CARD_ROM_HEADER_BUF_SIZE 0x1000 70 #define HW_TWL_CARD_ROM_HEADER_BUF_END (HW_TWL_CARD_ROM_HEADER_BUF + HW_TWL_CARD_ROM_HEADER_BUF_SIZE) 71 72 /*----------------------------------------------------------------------* 73 TWL SHARED RESERVED AREA 74 *----------------------------------------------------------------------*/ 75 #define HW_TWL_SHARED_RESERVED HW_TWL_CARD_ROM_HEADER_BUF_END 76 #define HW_TWL_SHARED_RESERVED_END HW_SYSM_VER_INFO_CONTENT_ID 77 78 /*----------------------------------------------------------------------* 79 SystemMenuVerionInfo content info 80 *----------------------------------------------------------------------*/ 81 #define HW_SYSM_VER_INFO_CONTENT_ID (HW_MAIN_MEM + 0x00ffd7b0 ) // 8-byte, NULL-terminated contentID 82 #define HW_SYSM_VER_INFO_CONTENT_LAST_INITIAL_CODE (HW_MAIN_MEM + 0x00ffd7b9 ) 83 84 /*----------------------------------------------------------------------* 85 Disable set HotBoot flag 86 *----------------------------------------------------------------------*/ 87 #define HW_SYSM_DISABLE_SET_HOTBOOT (HW_MAIN_MEM + 0x00ffd7ba ) 88 89 /*----------------------------------------------------------------------* 90 Nand context of SD driver 91 *----------------------------------------------------------------------*/ 92 #define HW_SD_NAND_CONTEXT_BUF (HW_MAIN_MEM + 0x00ffd7bc ) // NAND context data for the SD driver taken from the launcher 93 #define HW_SD_NAND_CONTEXT_BUF_END (HW_MAIN_MEM + 0x00ffd800 ) 94 95 /*----------------------------------------------------------------------* 96 TitleID list for system use 97 *----------------------------------------------------------------------*/ 98 #define HW_OS_TITLE_ID_LIST (HW_MAIN_MEM + 0x00ffd800 ) // User TitleID list 99 #define HW_OS_TITLE_ID_LIST_SIZE 0x400 100 101 /*----------------------------------------------------------------------* 102 FS PARAMETER from SystemMenu 103 *----------------------------------------------------------------------*/ 104 #define HW_TWL_FS_MOUNT_INFO_BUF (HW_MAIN_MEM + 0x00ffdc00 ) // Mount information (A size of 0x3c0 is allocated. You can specify up to 11 mount points. 11*84+1=0x39d�j 105 #define HW_TWL_FS_BOOT_SRL_PATH_BUF (HW_MAIN_MEM + 0x00ffdfc0 ) // Path to the SRL file for startup 106 107 /*----------------------------------------------------------------------* 108 MEMORY MAP of temporary area for sheltering each extended rom header 109 *----------------------------------------------------------------------*/ 110 #define HW_TWL_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffe000) 111 #define HW_TWL_ROM_HEADER_BUF_SIZE 0x1000 112 #define HW_TWL_ROM_HEADER_BUF_END (HW_TWL_ROM_HEADER_BUF + HW_TWL_ROM_HEADER_BUF_SIZE) 113 114 //#define HW_TWL_PRIMARY_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffd000) 115 //#define HW_TWL_PRIMARY_ROM_HEADER_BUF_SIZE 0x1000 116 //#define HW_TWL_PRIMARY_ROM_HEADER_BUF_END (HW_TWL_PRIMARY_ROM_HEADER_BUF + HW_TWL_PRIMARY_ROM_HEADER_BUF_SIZE) 117 118 //#define HW_TWL_SECONDARY_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffc000 ) 119 //#define HW_TWL_SECONDARY_ROM_HEADER_BUF_SIZE 0x1000 120 //#define HW_TWL_SECONDARY_ROM_HEADER_BUF_END (HW_TWL_SECONDARY_ROM_HEADER_BUF + HW_TWL_SECONDARY_ROM_HEADER_BUF_SIZE) 121 122 /*----------------------------------------------------------------------* 123 MEMORY MAP of SHARED AREA (4K bytes) 124 *----------------------------------------------------------------------*/ 125 #define HW_SHARED_ARENA_LO_DEFAULT HW_MAIN_MEM_SHARED 126 #define HW_SHARED_ARENA_SIZE_DEFAULT (HW_SHARED_ARENA_HI_DEFAULT - HW_SHARED_ARENA_LO_DEFAULT) // 1664 bytes 127 #define HW_SHARED_ARENA_HI_DEFAULT HW_PSEG1_RESERVED_0 128 129 #define HW_PSEG1_RESERVED_0 (HW_PSEG1_RESERVED_0_END - HW_PSEG1_RESERVED_0_SIZE) 130 #define HW_PSEG1_RESERVED_0_SIZE 0x180 // 384 bytes 131 #define HW_PSEG1_RESERVED_0_END HW_RED_RESERVED 132 133 #define HW_RED_RESERVED (HW_MAIN_MEM + 0x00fff800) 134 #define HW_RED_RESERVED_SIZE 0x200 // 512 bytes 135 #define HW_RED_RESERVED_END (HW_RED_RESERVED + HW_RED_RESERVED_SIZE) 136 137 #define HW_PSEG1_RESERVED_1 HW_RED_RESERVED_END 138 #define HW_PSEG1_RESERVED_1_SIZE (HW_PSEG1_RESERVED_1_END - HW_PSEG1_RESERVED_1) // 128 bytes 139 #define HW_PSEG1_RESERVED_1_END HW_CARD_ROM_HEADER 140 141 #define HW_CARD_ROM_HEADER (HW_MAIN_MEM + 0x00fffa80) 142 #define HW_CARD_ROM_HEADER_SIZE 0x160 // 352 bytes 143 #define HW_CARD_ROM_HEADER_END (HW_CARD_ROM_HEADER + HW_CARD_ROM_HEADER_SIZE) 144 145 #define HW_DOWNLOAD_PARAMETER (HW_MAIN_MEM + 0x00fffbe0) 146 #define HW_DOWNLOAD_PARAMETER_SIZE 0x20 // 32 bytes 147 #define HW_DOWNLOAD_PARAMETER_END (HW_DOWNLOAD_PARAMETER + HW_DOWNLOAD_PARAMETER_SIZE) 148 149 #define HW_MAIN_MEM_SYSTEM (HW_MAIN_MEM + 0x00fffc00) 150 #define HW_MAIN_MEM_SYSTEM_SIZE (HW_MAIN_MEM_SYSTEM_END - HW_MAIN_MEM_SYSTEM) // 1024 bytes 151 #define HW_MAIN_MEM_SYSTEM_END HW_MAIN_MEM_SHARED_END 152 153 /*----------------------------------------------------------------------* 154 MEMORY MAP of SYSTEM SHARED AREA2 (384 bytes) 155 *----------------------------------------------------------------------*/ 156 #define HW_WRAM_EX_LOCK_BUF (HW_MAIN_MEM + 0x00fff680) // WRAM lock buffer (END-0x180) 157 #define HW_WRAM_EX_LOCK_BUF_END (HW_MAIN_MEM + 0x00fff684) // (END-0x17c) 158 #define HW_RESET_LOCK_FLAG_BUF (HW_MAIN_MEM + 0x00fff684) // (END-0x17c) 159 #define HW_RESET_LOCK_FLAG_BUF_END (HW_MAIN_MEM + 0x00fff688) // (END-0x17c) 160 161 /*----------------------------------------------------------------------* 162 MEMORY MAP of SYSTEM SHARED AREA (1K bytes) 163 *----------------------------------------------------------------------*/ 164 #define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x00fffc00) // Boot check info (END-0x400) 165 #define HW_BOOT_CHECK_INFO_BUF_END (HW_MAIN_MEM + 0x00fffc20) // (END-0x3e0) 166 167 #define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x00fffc20) // reset parameter (END-0x3e0) 168 169 #define HW_BOOT_SHAKEHAND_9 (HW_MAIN_MEM + 0x00fffc24) // to shake hand with ARM7 boot sequence 170 #define HW_BOOT_SHAKEHAND_7 (HW_MAIN_MEM + 0x00fffc26) // to shake hand with ARM9 boot sequence 171 #define HW_BOOT_SYNC_PHASE (HW_MAIN_MEM + 0x00fffc28) // to synchronize ARM7/ARM9 boot sequences 172 // 0x02fffc2a - 0x02fffc2b reserved 173 174 #define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x00fffc2c) // ROM offset of own program (END-0x3d4) 175 #define HW_ROM_BASE_OFFSET_BUF_END (HW_MAIN_MEM + 0x00fffc30) // (END-0x3d0) 176 177 #define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x00fffc30) // Cartridge module info (END-0x3d0) 178 #define HW_CTRDG_MODULE_INFO_BUF_END (HW_MAIN_MEM + 0x00fffc3c) // (END-0x3c4) 179 180 #define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x00fffc3c) // VBlank counter (END-0x3c4) 181 182 #define HW_WM_BOOT_BUF (HW_MAIN_MEM + 0x00fffc40) // WM buffer for Multi-Boot (END-0x3c0) 183 #define HW_WM_BOOT_BUF_END (HW_MAIN_MEM + 0x00fffc80) // (END-0x380) 184 185 #define HW_NVRAM_USER_INFO (HW_MAIN_MEM + 0x00fffc80) // NVRAM user info (END-0x380) 186 #define HW_NVRAM_USER_INFO_END (HW_MAIN_MEM + 0x00fffd68) // (END-0x298) 187 #define HW_HW_SECURE_INFO (HW_MAIN_MEM + 0x00fffd68) // Secure system information (END-0x298) 188 #define HW_HW_SECURE_INFO_END (HW_MAIN_MEM + 0x00fffd80) // (END-0x280) 189 190 #define HW_BIOS_EXCP_STACK_MAIN (HW_MAIN_MEM + 0x00fffd80) // MAINP Debugger monitor exception handler(END-0x280) 191 #define HW_BIOS_EXCP_STACK_MAIN_END (HW_MAIN_MEM + 0x00fffd9c) // (END-0x264) 192 #define HW_EXCP_VECTOR_MAIN (HW_MAIN_MEM + 0x00fffd9c) // HW_EXCP_VECTOR_BUF for MAINP (END-0x264) 193 194 #define HW_ARENA_INFO_BUF (HW_MAIN_MEM + 0x00fffda0) // Arena data structure (27F_FDA0 to 27F_FDE7) (END-0x260) 195 #define HW_REAL_TIME_CLOCK_BUF (HW_MAIN_MEM + 0x00fffde8) // RTC 196 197 #define HW_SYS_CONF_BUF (HW_MAIN_MEM + 0x00fffdf0) // System config data (END-0x210) 198 #define HW_SYS_CONF_BUF_END (HW_MAIN_MEM + 0x00fffdf6) // (END-0x20a) 199 200 #define HW_PRINT_OUTPUT_ARM9 (HW_MAIN_MEM + 0x00fffdf6) // debug print window for ARM9 201 #define HW_PRINT_OUTPUT_ARM7 (HW_MAIN_MEM + 0x00fffdf7) // debug print window for ARM7 202 #define HW_PRINT_OUTPUT_ARM9ERR (HW_MAIN_MEM + 0x00fffdf8) // debug print window for ARM9 error 203 #define HW_PRINT_OUTPUT_ARM7ERR (HW_MAIN_MEM + 0x00fffdf9) // debug print window for ARM7 error 204 205 #define HW_NAND_FIRM_HOTSTART_FLAG (HW_MAIN_MEM + 0x00fffdfa) // debug print window for ARM7 error 206 #define HW_TWL_RED_LAUNCHER_VER (HW_MAIN_MEM + 0x00fffdfb) // RED launcher version 207 #define HW_PRELOAD_PARAMETER_ADDR (HW_MAIN_MEM + 0x00fffdfc) // preload parameter address 208 209 #define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00fffe00) // ROM-internal registration area data buffer (END-0x200) 210 #define HW_ROM_HEADER_BUF_END (HW_MAIN_MEM + 0x00ffff60) // (END-0x0a0) 211 #define HW_ISD_RESERVED (HW_MAIN_MEM + 0x00ffff60) // IS DEBUGGER Reserved (END-0xa0) 212 #define HW_ISD_RESERVED_END (HW_MAIN_MEM + 0x00ffff80) // (END-0x80) 213 214 #define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x00ffff80) // PXI Signal Param for ARM9 215 #define HW_PXI_SIGNAL_PARAM_ARM7 (HW_MAIN_MEM + 0x00ffff84) // PXI Signal Param for ARM7 216 #define HW_PXI_HANDLE_CHECKER_ARM9 (HW_MAIN_MEM + 0x00ffff88) // PXI Handle Checker for ARM9 217 #define HW_PXI_HANDLE_CHECKER_ARM7 (HW_MAIN_MEM + 0x00ffff8c) // PXI Handle Checker for ARM7 218 219 #define HW_MIC_LAST_ADDRESS (HW_MAIN_MEM + 0x00ffff90) // MIC new sampling data storage address 220 #define HW_MIC_SAMPLING_DATA (HW_MAIN_MEM + 0x00ffff94) // MIC individual sampling results 221 222 #define HW_WM_CALLBACK_CONTROL (HW_MAIN_MEM + 0x00ffff96) // Parameter to synchronize WM callback 223 #define HW_WM_RSSI_POOL (HW_MAIN_MEM + 0x00ffff98) // Random number source depends on WM received signal intensity 224 225 #define HW_SET_CTRDG_MODULE_INFO_ONCE (HW_MAIN_MEM + 0x00ffff9a) // set ctrdg module info flag 226 #define HW_IS_CTRDG_EXIST (HW_MAIN_MEM + 0x00ffff9b) // ctrdg exist flag 227 228 #define HW_COMPONENT_PARAM (HW_MAIN_MEM + 0x00ffff9c) // Parameter for component synchronization 229 230 #define HW_THREADINFO_MAIN (HW_MAIN_MEM + 0x00ffffa0) // ThreadInfo for Main processor 231 #define HW_THREADINFO_SUB (HW_MAIN_MEM + 0x00ffffa4) // ThreadInfo for subprocessor 232 #define HW_BUTTON_XY_BUF (HW_MAIN_MEM + 0x00ffffa8) // buffer for X and Y button 233 #define HW_TOUCHPANEL_BUF (HW_MAIN_MEM + 0x00ffffaa) // buffer for touch panel 234 #define HW_AUTOLOAD_SYNC_BUF (HW_MAIN_MEM + 0x00ffffae) // buffer for autoload sync 235 236 #define HW_LOCK_ID_FLAG_MAIN (HW_MAIN_MEM + 0x00ffffb0) // lockID flag for Main processor 237 #define HW_LOCK_ID_FLAG_SUB (HW_MAIN_MEM + 0x00ffffb8) // lockID flag for subprocessor 238 239 // SpinLock Mutex 240 #define HW_VRAM_C_LOCK_BUF (HW_MAIN_MEM + 0x00ffffc0) // VRAM-C lock buffer (END-0x40) 241 #define HW_VRAM_D_LOCK_BUF (HW_MAIN_MEM + 0x00ffffc8) // VRAM-D lock buffer (END-0x38) 242 #define HW_WRAM_BLOCK0_LOCK_BUF (HW_MAIN_MEM + 0x00ffffd0) // CPU internal work RAM - Block0 - lock buffer (END-0x30) 243 #define HW_WRAM_BLOCK1_LOCK_BUF (HW_MAIN_MEM + 0x00ffffd8) // CPU internal work RAM - Block1 - lock buffer (END-0x28) 244 #define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x00ffffe0) // Game Card - lock buffer (END-0x20) 245 #define HW_CTRDG_LOCK_BUF (HW_MAIN_MEM + 0x00ffffe8) // DS Pak - lock buffer (END-0x18) 246 #define HW_INIT_LOCK_BUF (HW_MAIN_MEM + 0x00fffff0) // Initialization lock buffer (END-0x10) 247 248 #define HW_MMEMCHECKER_MAIN (HW_MAIN_MEM + 0x00fffff8) // MainMemory Size Checker for Main processor (END-8) 249 #define HW_MMEMCHECKER_SUB (HW_MAIN_MEM + 0x00fffffa) // MainMemory Size Checker for Sub processor (END-6) 250 251 #define HW_CHIPTYPE_FLAG (HW_MAIN_MEM + 0x00fffffc) // chiptype flag (END-4) 252 253 #define HW_CMD_AREA (HW_MAIN_MEM + 0x00fffffe) // Main memory command issue area (Prohibited use area) (END-2) 254 255 //---------------------------------------------------------------------- 256 //---- Lock area 257 #define HW_SHARED_LOCK_BUF (HW_VRAM_C_LOCK_BUF) 258 #define HW_SHARED_LOCK_BUF_END (HW_INIT_LOCK_BUF + 8) 259 260 /*----------------------------------------------------------------------* 261 Shared memory space for checking the debugger state 262 [TODO] This region will no longer be reserved by the system when starting in TWL mode, so someone needs to revise the debugger library. 263 264 *----------------------------------------------------------------------*/ 265 #define HW_CHECK_DEBUGGER_SW 0x027ffc10 // (u16) debugger check switch. if 0 check buf1, else buf2. 266 #define HW_CHECK_DEBUGGER_BUF1 0x027ff814 // (u16) debugger checker. 1 if run on debugger. 267 #define HW_CHECK_DEBUGGER_BUF2 0x027ffc14 // (u16) debugger checker. 1 if run on debugger. 268 269 /*---------------------------------------------------------------------------*/ 270 #ifdef __cplusplus 271 } /* extern "C" */ 272 #endif 273 #endif /* TWL_HW_COMMON_MMAP_SHARED_H_ */ 274