1 /*---------------------------------------------------------------------------* 2 Project: Horizon 3 File: gx_MacroShader.h 4 5 Copyright (C)2009-2012 Nintendo Co., Ltd. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Rev: 46347 $ 14 *---------------------------------------------------------------------------*/ 15 16 #ifndef NN_GX_CTR_PICA_MACRO_SHADER_H_ 17 #define NN_GX_CTR_PICA_MACRO_SHADER_H_ 18 19 #include <nn/gx/CTR/gx_MacroCommon.h> 20 21 /* Please see man pages for details 22 23 24 */ 25 26 /////////////////////////////////// 27 // Draw API 28 // Geometry Misc Registers 29 /* 30 struct CommandDrawAPIMode0 31 { 32 u32 geometryUse : 2; 33 CMD_PADDING(6); 34 u32 mode : 1; 35 CMD_PADDING(1); // set to 0 [9:9] 36 CMD_PADDING(21); 37 u32 geometryUseMode : 1; 38 }; 39 */ 40 41 // PICA_REG_DRAW_MODE0 0x229 42 #define PICA_CMD_DATA_DRAW_MODE0(useGeometryShader, drawMode, useGeometryShaderSubdivision) \ 43 ( (useGeometryShader ? 2 : 0) | \ 44 (drawMode) << 8 | \ 45 0 << 9 | \ 46 ( (useGeometryShaderSubdivision) ? 1 : 0) << 31) 47 48 #define PICA_CMD_SET_DRAW_MODE0(drawMode) \ 49 PICA_CMD_DATA_DRAW_MODE0(0x0, drawMode, 0x0), \ 50 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE0, 0x2) 51 52 #define PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() \ 53 0x0, PICA_CMD_HEADER_BURST_BE(PICA_REG_VERTEX_ATTR_ARRAYS_BASE_ADDR, 30, 0x0), \ 54 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 55 0x0, 0x0, \ 56 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 57 0x0, 0x0, \ 58 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 59 0x0, 0x0 60 61 #define PICA_CMD_SET_DRAW_MODE0_DUMMY_BEGIN() \ 62 0x0, PICA_CMD_HEADER_BURST_BE(PICA_REG_VS_OUT_REG_NUM2, 10, 0x0), \ 63 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 64 0x0, 0x0, \ 65 PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() 66 67 #define PICA_CMD_SET_DRAW_MODE0_DUMMY_END() \ 68 PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() 69 70 #define PICA_CMD_SET_VS_GS_MODE(useGeometryShader, useGeometryShaderSubdivision) \ 71 PICA_CMD_SET_DRAW_MODE0_DUMMY_BEGIN(), \ 72 PICA_CMD_DATA_DRAW_MODE0(useGeometryShader, 0x0, useGeometryShaderSubdivision), \ 73 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE0, 0x9), \ 74 PICA_CMD_SET_DRAW_MODE0_DUMMY_END() 75 76 /* 77 struct CommandDrawAPIMode0 78 { 79 u32 func : 1; 80 CMD_PADDING(7); 81 u32 mode : 1; 82 CMD_PADDING(23); 83 }; 84 */ 85 86 // PICA_REG_START_DRAW_FUNC 0x245 87 #define PICA_CMD_DATA_START_DRAW_FUNC(data) \ 88 ( (data) ? 1 : 0 ) 89 90 // PICA_REG_DRAW_MODE1 0x253 91 #define PICA_CMD_DATA_DRAW_MODE1(func, mode) \ 92 ( (func) | (mode) << 8 ) 93 94 #define PICA_CMD_SET_DRAW_MODE1(func, mode) \ 95 PICA_CMD_DATA_DRAW_MODE1(func, mode), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE1, 0x3) 96 97 // PICA_REG_DRAW_VERTEX_NUM 0x228 98 #define PICA_CMD_DATA_DRAW_VERTEX_NUM(num) (num) 99 100 // PICA_REG_DRAW_VERTEX_OFFSET 0x22a 101 #define PICA_CMD_DATA_DRAW_VERTEX_OFFSET(offset) (offset) 102 103 // PICA_REG_START_DRAW_ARRAY 0x22e 104 #define PICA_CMD_DATA_START_DRAW_ARRAY(start) (start) 105 106 #define PICA_CMD_SET_START_DRAW_ARRAY(start) \ 107 PICA_CMD_DATA_START_DRAW_FUNC(0x0), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 108 PICA_CMD_DATA_START_DRAW_ARRAY(start), PICA_CMD_HEADER_SINGLE(PICA_REG_START_DRAW_ARRAY), \ 109 PICA_CMD_DATA_START_DRAW_FUNC(0x1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 110 0x1, PICA_CMD_HEADER_SINGLE(PICA_REG_VERTEX_FUNC), \ 111 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8), \ 112 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8) 113 114 // PICA_REG_START_DRAW_ELEMENT 0x22f 115 #define PICA_CMD_DATA_START_DRAW_ELEMENT(start) (start) 116 117 #define PICA_CMD_SET_START_DRAW_ELEMENT(start) \ 118 PICA_CMD_DATA_START_DRAW_FUNC(0x0), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 119 PICA_CMD_DATA_START_DRAW_ELEMENT(start), PICA_CMD_HEADER_SINGLE(PICA_REG_START_DRAW_ELEMENT), \ 120 PICA_CMD_DATA_START_DRAW_FUNC(0x1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 121 0x1, PICA_CMD_HEADER_SINGLE(PICA_REG_VERTEX_FUNC), \ 122 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8), \ 123 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8) 124 125 /////////////////////////////////// 126 // Vertex Shader float value 127 /* 128 struct CommandVSFloatAddr 129 { 130 u32 index : 8; 131 CMD_PADDING(23); 132 u32 mode : 1; 133 134 }; 135 */ 136 // PICA_REG_VS_FLOAT_ADDR 0x2c0 137 138 /* Please see man pages for details 139 140 141 */ 142 enum PicaDataVSFloat 143 { 144 // 145 PICA_DATA_VS_F24 = 0x0, 146 // 147 PICA_DATA_VS_F32 = 0x1 148 }; 149 150 #define PICA_CMD_DATA_VS_FLOAT_ADDR(mode, index) \ 151 ( (index) & 0xff | ( (mode) ? 0x80000000 : 0) ) 152 153 #define PICA_CMD_SET_VS_FLOAT_ADDR(mode, index) \ 154 PICA_CMD_DATA_VS_FLOAT_ADDR(mode, index), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_FLOAT_ADDR) 155 156 // PICA_REG_VS_FLOAT 0x2c1 to 0x2c8 157 #define PICA_CMD_DATA_VS_FLOAT(data) (data) 158 159 /////////////////////////////////// 160 // Vertex Shader Bool 161 162 // PICA_REG_VS_BOOL 0x2b0 163 164 #define PICA_CMD_DATA_VS_BOOL(b) \ 165 ( (b) | 0x7fff0000 ) 166 167 /////////////////////////////////// 168 // Vertex Shader Integer 169 /* 170 struct CommandVSInt 171 { 172 u32 x : 8; 173 u32 y : 8; 174 u32 z : 8; 175 CMD_PADDING(8); 176 }; 177 */ 178 // PICA_REG_VS_INT0 0x2b1 to 0x2b4 179 #define PICA_CMD_DATA_VS_INT(x, y, z) ( (x) | (y) << 8 | (z) << 16 ) 180 181 /////////////////////////////////// 182 // Vertex Shader Start Address 183 184 // PICA_REG_VS_START_ADDR 0x2ba 185 #define PICA_CMD_DATA_VS_START_ADDR(data) \ 186 ( (data) | 0x7fff0000 ) 187 188 /////////////////////////////////// 189 // Vertex Shader Attribute Number 190 191 // PICA_REG_VS_ATTR_NUM0 0x2b9 192 #define PICA_CMD_DATA_VS_ATTR_NUM0(num) \ 193 ( ((num - 1) & 0xf) | ( 0xa0000000 ) ) 194 195 // PICA_REG_VS_ATTR_NUM1 0x242 196 #define PICA_CMD_DATA_VS_ATTR_NUM1(num) \ 197 ( (num - 1) & 0xf ) 198 199 #define PICA_CMD_SET_VS_ATTR_NUM(num) \ 200 PICA_CMD_DATA_VS_ATTR_NUM0(num), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_ATTR_NUM0, 0xB), \ 201 PICA_CMD_DATA_VS_ATTR_NUM1(num), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_ATTR_NUM1) \ 202 203 /////////////////////////////////// 204 // Draw API 205 // Vertex Shader Output Register Number 206 // Geometry Shader Output Register Number 207 208 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM(num) (num) 209 210 // PICA_REG_VS_OUT_REG_NUM0 0x04f 211 // PICA_REG_GS_OUT_REG_NUM0 0x04f 212 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM0(num) (num) 213 214 // PICA_REG_VS_OUT_REG_NUM1 0x24a 215 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM1(num) ( (num) - 1 ) 216 217 // PICA_REG_VS_OUT_REG_NUM2 0x251 218 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM2(num) ( (num) - 1 ) 219 220 221 /* 222 struct CommandVSOutRegNum 223 { 224 u32 num : 4; 225 CMD_PADDING(4); 226 u32 mode : 1; 227 CMD_PADDING(23); 228 }; 229 */ 230 231 232 /* Please see man pages for details 233 234 235 */ 236 enum PicaDataDrawMode 237 { 238 // 239 PICA_DATA_DRAW_TRIANGLE_STRIP = 0x1, 240 // 241 PICA_DATA_DRAW_TRIANGLE_FAN = 0x2, 242 // 243 PICA_DATA_DRAW_TRIANGLES = 0x3, 244 // 245 PICA_DATA_DRAW_GEOMETRY_PRIMITIVE = 0x3 246 }; 247 248 // PICA_REG_VS_OUT_REG_NUM3 0x25e 249 // PICA_REG_GS_OUT_REG_NUM3 0x25e 250 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM3(num, mode) \ 251 ( (num - 1) | (mode) << 8 ) 252 253 #define PICA_CMD_SET_DRAW_MODE2(mode) \ 254 ((mode) << 8), \ 255 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_OUT_REG_NUM3, 0x2) 256 257 #define PICA_CMD_SET_VS_GS_OUT_REG_NUM(num) \ 258 num, PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM0), \ 259 (num - 1), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM1), \ 260 (num - 1), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM2), \ 261 (num - 1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_OUT_REG_NUM3, 0x1) 262 263 /////////////////////////////////// 264 // Vertex Shader Output Register Mask 265 266 // PICA_REG_VS_OUT_REG_MASK 0x2bd 267 #define PICA_CMD_DATA_VS_OUT_MASK(mask) \ 268 ( (mask) & 0xffff ) 269 270 /////////////////////////////////// 271 // Vertex Shader Output Attribute 272 // Geometry Shader Output Attribute 273 274 /* Please see man pages for details 275 276 277 */ 278 enum PicaDataVSOutAttr 279 { 280 // 281 PICA_DATA_VS_OUT_ATTR_X = 0x00, 282 // 283 PICA_DATA_VS_OUT_ATTR_Y = 0x01, 284 // 285 PICA_DATA_VS_OUT_ATTR_Z = 0x02, 286 // 287 PICA_DATA_VS_OUT_ATTR_W = 0x03, 288 // 289 PICA_DATA_VS_OUT_ATTR_QUART_X = 0x04, 290 // 291 PICA_DATA_VS_OUT_ATTR_QUART_Y = 0x05, 292 // 293 PICA_DATA_VS_OUT_ATTR_QUART_Z = 0x06, 294 // 295 PICA_DATA_VS_OUT_ATTR_QUART_W = 0x07, 296 // 297 PICA_DATA_VS_OUT_ATTR_R = 0x08, 298 // 299 PICA_DATA_VS_OUT_ATTR_G = 0x09, 300 // 301 PICA_DATA_VS_OUT_ATTR_B = 0x0a, 302 // 303 PICA_DATA_VS_OUT_ATTR_A = 0x0b, 304 // 305 PICA_DATA_VS_OUT_ATTR_TEX0_U = 0x0c, 306 // 307 PICA_DATA_VS_OUT_ATTR_TEX0_V = 0x0d, 308 // 309 PICA_DATA_VS_OUT_ATTR_TEX1_U = 0x0e, 310 // 311 PICA_DATA_VS_OUT_ATTR_TEX1_V = 0x0f, 312 // 313 PICA_DATA_VS_OUT_ATTR_TEX0_W = 0x10, 314 // 315 PICA_DATA_VS_OUT_ATTR_VIEW_X = 0x12, 316 // 317 PICA_DATA_VS_OUT_ATTR_VIEW_Y = 0x13, 318 // 319 PICA_DATA_VS_OUT_ATTR_VIEW_Z = 0x14, 320 // 321 PICA_DATA_VS_OUT_ATTR_TEX2_U = 0x16, 322 // 323 PICA_DATA_VS_OUT_ATTR_TEX2_V = 0x17, 324 // 325 PICA_DATA_VS_OUT_ATTR_INVALID = 0x1f 326 }; 327 328 /* 329 struct CommandVSOutAttr 330 { 331 u32 attr_x : 5; 332 CMD_PADDING(3); 333 u32 attr_y : 5; 334 CMD_PADDING(3); 335 u32 attr_z : 5; 336 CMD_PADDING(3); 337 u32 attr_w : 5; 338 CMD_PADDING(3); 339 }; 340 */ 341 342 // PICA_REG_VS_OUT_ATTR0 0x050 to 0x056 343 // PICA_REG_GS_OUT_ATTR0 0x050 to 0x056 344 #define PICA_CMD_DATA_VS_GS_OUT_ATTR(attr_x, attr_y, attr_z, attr_w) \ 345 ( (attr_x) | (attr_y) << 8 | (attr_z) << 16 | (attr_w) << 24 ) 346 347 // PICA_REG_VS_OUT_ATTR_MODE 0x064 348 // PICA_REG_GS_OUT_ATTR_MODE 0x064 349 #define PICA_CMD_DATA_VS_GS_OUT_ATTR_MODE( mode ) (mode) 350 351 /////////////////////////////////// 352 // Vertex Shader Output Attribute clock 353 // Geometry Shader Output Attribute clock 354 /* 355 struct CommandVSOutAttrClk 356 { 357 u32 verZ : 1; 358 u32 col : 1; 359 CMD_PADDING(6); 360 u32 tex0 : 1; 361 u32 tex1 : 1; 362 u32 tex2 : 1; 363 CMD_PADDING(5); 364 u32 tex0_w : 1; 365 CMD_PADDING(7); 366 u32 view_quart : 1; 367 CMD_PADDING(7); 368 }; 369 */ 370 371 // PICA_REG_VS_OUT_ATTR_CLK 0x06f 372 // PICA_REG_GS_OUT_ATTR_CLK 0x06f 373 #define PICA_CMD_DATA_VS_GS_OUT_ATTR_CLK(posZ, col, tex0, tex1, tex2, tex0_w, view_quart) \ 374 ( ((posZ) ? 1 : 0) | \ 375 ((col) ? 1 : 0) << 1 | \ 376 ((tex0) ? 1 : 0) << 8 | \ 377 ((tex1) ? 1 : 0) << 9 | \ 378 ((tex2) ? 1 : 0) << 10 | \ 379 ((tex0_w) ? 1 : 0) << 16 | \ 380 ((view_quart) ? 1 : 0) << 24 ) 381 382 /////////////////////////////////// 383 // Vertex Shader Program Code 384 385 // PICA_REG_VS_PROG_ADDR 0x2cb 386 #define PICA_CMD_DATA_VS_PROG_ADDR(addr) (addr) 387 388 // PICA_REG_VS_PROG_SWIZZLE_ADDR 0x2d5 389 #define PICA_CMD_DATA_VS_PROG_SWIZZLE_ADDR(addr) (addr) 390 391 // PICA_REG_VS_PROG_DATA0 0x2cc to 0x2d3 392 #define PICA_CMD_DATA_VS_PROG_DATA(data) (data) 393 394 // PICA_REG_VS_PROG_SWIZZLE_DATA0 0x2d6 to 0x2dd 395 #define PICA_CMD_DATA_VS_PROG_SWIZZLE_DATA(data) (data) 396 397 // PICA_REG_VS_PROG_END 0x2bf 398 #define PICA_CMD_DATA_VS_PROG_END(data) (data) 399 400 /////////////////////////////////// 401 // Vertex Shader Attribute Input Register Map 402 /* 403 struct CommandVSAttrInputRegMap0 404 u32 index1 : 4; 405 u32 index2 : 4; 406 u32 index3 : 4; 407 u32 index4 : 4; 408 u32 index5 : 4; 409 u32 index6 : 4; 410 u32 index7 : 4; 411 u32 index8 : 4; 412 }; 413 */ 414 415 // PICA_REG_VS_ATTR_IN_REG_MAP0 0x2bb 416 #define PICA_CMD_DATA_VS_ATTR_IN_REG_MAP0(index1, index2, index3, index4, index5, index6, index7, index8) \ 417 ((index1) | (index2) << 4 | (index3) << 8 | (index4) << 12 | \ 418 (index5) << 16 | (index6) << 20 | (index7) << 24 | (index8) << 28 ) 419 420 /* 421 struct CommandVSAttrInputRegMap1 422 { 423 u32 index9 : 4; 424 u32 index10 : 4; 425 u32 index11 : 4; 426 u32 index12 : 4; 427 CMD_PADDING(16); 428 429 }; 430 */ 431 432 // PICA_REG_VS_ATTR_IN_REG_MAP1 0x2bc 433 #define PICA_CMD_DATA_VS_ATTR_IN_REG_MAP1(index9, index10, index11, index12) \ 434 ((index9) | (index10) << 4 | (index11) << 8 | (index12) << 12) 435 436 /////////////////////////////////// 437 // Vertex Shader Fixed Attribute 438 439 // PICA_REG_VS_FIXED_ATTR 0x232 440 #define PICA_CMD_DATA_VS_FIXED_ATTR(order) ( (order) & 0xf ) 441 442 // PICA_REG_VS_FIXED_ATTR_DATA0 0x233 to 0x235 443 #define PICA_CMD_DATA_VS_FIXED_ATTR_DATA(data) (data) 444 445 #define PICA_CMD_SET_VS_FIXED_ATTR(order, c0, c1, c2) \ 446 PICA_CMD_DATA_VS_FIXED_ATTR(order), PICA_CMD_HEADER_BURSTSEQ( PICA_REG_VS_FIXED_ATTR, 4), \ 447 (u32)(c0), (u32)(c1), \ 448 (u32)(c2), PICA_CMD_DATA_ZERO() 449 450 /////////////////////////////////// 451 // Vertex Attribute Arrays 452 /* 453 struct CommandVtxAttrArraysBaseAddr 454 { 455 CMD_PADDING(1); 456 u32 addr : 28; 457 CMD_PADDING(3); 458 }; 459 */ 460 // PICA_REG_VERTEX_ATTR_ARRAYS_BASE_ADDR 0x200 461 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS_BASE_ADDR(addr) ( ((u32)(addr) >> 4) << 1 ) 462 463 /* 464 struct CommandVAttrArrays 465 { 466 u32 attr0 : 4; 467 u32 attr1 : 4; 468 u32 attr2 : 4; 469 u32 attr3 : 4; 470 u32 attr4 : 4; 471 u32 attr5 : 4; 472 u32 attr6 : 4; 473 u32 attr7 : 4; 474 }; 475 */ 476 477 478 /* Please see man pages for details 479 480 481 482 */ 483 enum PicaDataVertexAttrType 484 { 485 // 486 PICA_DATA_SIZE_1_BYTE = 0x0, 487 // 488 PICA_DATA_SIZE_1_UNSIGNED_BYTE = 0x1, 489 // 490 PICA_DATA_SIZE_1_SHORT = 0x2, 491 // 492 PICA_DATA_SIZE_1_FLOAT = 0x3, 493 // 494 PICA_DATA_SIZE_2_BYTE = 0x4, 495 // 496 PICA_DATA_SIZE_2_UNSIGNED_BYTE = 0x5, 497 // 498 PICA_DATA_SIZE_2_SHORT = 0x6, 499 // 500 PICA_DATA_SIZE_2_FLOAT = 0x7, 501 // 502 PICA_DATA_SIZE_3_BYTE = 0x8, 503 // 504 PICA_DATA_SIZE_3_UNSIGNED_BYTE = 0x9, 505 // 506 PICA_DATA_SIZE_3_SHORT = 0xa, 507 // 508 PICA_DATA_SIZE_3_FLOAT = 0xb, 509 // 510 PICA_DATA_SIZE_4_BYTE = 0xc, 511 // 512 PICA_DATA_SIZE_4_UNSIGNED_BYTE = 0xd, 513 // 514 PICA_DATA_SIZE_4_SHORT = 0xe, 515 // 516 PICA_DATA_SIZE_4_FLOAT = 0xf 517 }; 518 519 // PICA_REG_VERTEX_ATTR_ARRAYS0 0x201 520 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS0(attr0, attr1, attr2, attr3, attr4, attr5, attr6, attr7) \ 521 ((attr0) | (attr1) << 4 | (attr2) << 8 | (attr3) << 12 | \ 522 (attr4) << 16 | (attr5) << 20 | (attr6) << 24 | (attr7) << 28) 523 524 // PICA_REG_VERTEX_ATTR_ARRAYS1 0x202 525 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS1(attr8, attr9, attr10, attr11, mask, attrNum) \ 526 ( (attr8) | \ 527 (attr9) << 4 | \ 528 (attr10) << 8 | \ 529 (attr11) << 12 | \ 530 (mask) << 16 | \ 531 ((attrNum) - 1) << 28 ) 532 533 // PICA_REG_LOAD_ARRAY0_ATTR_OFFSET 0x203 534 #define PICA_CMD_DATA_LOAD_ARRAY0_ATTR_OFFSET(offset) (offset) 535 536 /* 537 struct CommandLodArray0Element 538 { 539 u32 attr0 : 4; 540 u32 attr1 : 4; 541 u32 attr2 : 4; 542 u32 attr3 : 4; 543 u32 attr4 : 4; 544 u32 attr5 : 4; 545 u32 attr6 : 4; 546 u32 attr7 : 4; 547 }; 548 */ 549 550 /* Please see man pages for details 551 552 553 */ 554 enum PicaDataVertexAttr 555 { 556 // 557 PICA_DATA_VERTEX_0_ATTR = 0x0, 558 // 559 PICA_DATA_VERTEX_1_ATTR = 0x1, 560 // 561 PICA_DATA_VERTEX_2_ATTR = 0x2, 562 // 563 PICA_DATA_VERTEX_3_ATTR = 0x3, 564 // 565 PICA_DATA_VERTEX_4_ATTR = 0x4, 566 // 567 PICA_DATA_VERTEX_5_ATTR = 0x5, 568 // 569 PICA_DATA_VERTEX_6_ATTR = 0x6, 570 // 571 PICA_DATA_VERTEX_7_ATTR = 0x7, 572 // 573 PICA_DATA_VERTEX_8_ATTR = 0x8, 574 // 575 PICA_DATA_VERTEX_9_ATTR = 0x9, 576 // 577 PICA_DATA_VERTEX_a_ATTR = 0xa, 578 // 579 PICA_DATA_VERTEX_b_ATTR = 0xb, 580 // 581 PICA_DATA_PADDING_4_BYTE = 0xc, 582 // 583 PICA_DATA_PADDING_8_BYTE = 0xd, 584 // 585 PICA_DATA_PADDING_12_BYTE = 0xe, 586 // 587 PICA_DATA_PADDING_16_BYTE = 0xf 588 }; 589 590 // PICA_REG_LOAD_ARRAY0_ELEMENT0 0x204 591 #define PICA_CMD_DATA_LOAD_ARRAY_ELEMENT0(attr0, attr1, attr2, attr3, attr4, attr5, attr6, attr7) \ 592 ( (attr0) | (attr1) << 4 | (attr2) << 8 | (attr3) << 12 | \ 593 (attr4) << 16 | (attr5) << 20 | (attr6) << 24 | (attr7) << 28) 594 595 // PICA_REG_LOAD_ARRAY0_ELEMENT1 0x205 596 #define PICA_CMD_DATA_LOAD_ARRAY_ELEMENT1(attr8, attr9, attr10, attr11, byteNum, elementNum) \ 597 ( (attr8) | \ 598 (attr9) << 4 | \ 599 (attr10) << 8 | \ 600 (attr11) << 12 | \ 601 (byteNum) << 16 | \ 602 (elementNum) << 28 ) 603 604 605 /* 606 struct CommandIndexArrayAddrOffset 607 { 608 u32 offset : 28; 609 CMD_PADDING(3); 610 u32 type : 1; 611 }; 612 */ 613 614 enum PicaDataIndexArray 615 { 616 PICA_DATA_INDEX_ARRAY_UNSIGNED_BYTE = 0x0, 617 PICA_DATA_INDEX_ARRAY_UNSIGNED_SHORT = 0x1 618 }; 619 620 // PICA_REG_INDEX_ARRAY_ADDR_OFFSET 0x227 621 #define PICA_CMD_DATA_INDEX_ARRAY_ADDR_OFFSET(offset, type) \ 622 ( (offset) | ((type) ? 0x80000000 : 0 ) ) 623 624 /////////////////////////////////// 625 // Geometry Shader Over View 626 627 // PICA_REG_VS_COM_MODE 0x244 628 #define PICA_CMD_DATA_VS_COM_MODE(mode) ((mode) ? 1 : 0) 629 630 #define PICA_CMD_SET_VS_COM_MODE(mode) \ 631 PICA_CMD_DATA_VS_COM_MODE(mode), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_COM_MODE, 0x1) 632 633 /////////////////////////////////// 634 // Geometry Shader float value 635 /* 636 struct CommandGSFloatAddr 637 { 638 u32 index : 8; 639 CMD_PADDING(23); 640 u32 mode : 1; 641 642 }; 643 */ 644 645 /* Please see man pages for details 646 647 648 */ 649 enum PicaDataGSFloat 650 { 651 // 652 PICA_DATA_GS_F24 = 0x0, 653 // 654 PICA_DATA_GS_F32 = 0x1 655 }; 656 657 // PICA_REG_GS_FLOAT_ADDR 0x290 658 659 #define PICA_CMD_DATA_GS_FLOAT_ADDR(mode, index) \ 660 ( ((index) & 0xff) | (mode) << 31 ) 661 662 #define PICA_CMD_SET_GS_FLOAT_ADDR(mode, index) \ 663 PICA_CMD_DATA_GS_FLOAT_ADDR(mode, index), PICA_CMD_HEADER_SINGLE(PICA_REG_GS_FLOAT_ADDR) 664 665 // PICA_REG_GS_FLOAT_DATA 0x291 to 0x298 666 #define PICA_CMD_DATA_GS_FLOAT_DATA(data) (data) 667 668 /////////////////////////////////// 669 // Geometry Shader Bool 670 671 // PICA_REG_GS_BOOL 0x280 672 #define PICA_CMD_DATA_GS_BOOL(b) \ 673 ( (b) | 0x7fff0000 ) 674 675 /////////////////////////////////// 676 // Geometry Shader Integer 677 /* 678 struct CommandGSInt 679 { 680 u32 x : 8; 681 u32 y : 8; 682 u32 z : 8; 683 CMD_PADDING(8); 684 }; 685 */ 686 // PICA_REG_GS_INT0 0x281 to 0x284 687 #define PICA_CMD_DATA_GS_INT(x, y, z) ( (x) | (y) << 8 | (z) << 16 ) 688 689 /////////////////////////////////// 690 // Geometry Shader Start Address 691 692 // PICA_REG_GS_START_ADDR 0x28a 693 #define PICA_CMD_DATA_GS_START_ADDR(data) \ 694 ( (data) | 0x7fff0000 ) 695 696 /////////////////////////////////// 697 // Geometry Shader Attribute Number 698 // Geometry Misc Registers 699 /* 700 struct CommandGSAttrNum 701 { 702 u32 num : 4; 703 CMD_PADDING(4); 704 u32 mode0 : 8; 705 CMD_PADDING(8); 706 u32 mode1 : 8; 707 }; 708 */ 709 710 // 0x289[15:8] : 0x1/0x0, 711 // 0x289[31:24] : 0x08/0xa0, 712 713 714 // PICA_REG_GS_ATTR_NUM 0x289 715 #define PICA_CMD_DATA_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader) \ 716 ( ( (geometryShaderVertexAttrInputNum) - 1) | \ 717 ( (useGeometrySubdivision) ? 1 : 0) << 8 | \ 718 ( ((useGeometryShader) ? 0x08 : 0xa0) << 24 ) ) 719 720 #define PICA_CMD_SET_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader) \ 721 PICA_CMD_DATA_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader), \ 722 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_GS_ATTR_NUM, 0xB) 723 724 /////////////////////////////////// 725 // Geometry Shader Output Register Mask 726 727 // PICA_REG_GS_OUT_REG_MASK 0x28d 728 #define PICA_CMD_DATA_GS_OUT_MASK(mask) \ 729 ( (mask) & 0xffff ) 730 731 /////////////////////////////////// 732 // Geometry Shader Program Code 733 734 735 // PICA_REG_GS_PROG_ADDR 0x29b 736 #define PICA_CMD_DATA_GS_PROG_ADDR(addr) (addr) 737 738 // PICA_REG_GS_PROG_SWIZZLE_ADDR 0x2a5 739 #define PICA_CMD_DATA_GS_PROG_SWIZZLE_ADDR(addr) (addr) 740 741 // PICA_REG_GS_PROG_DATA0 0x29c to 0x2a3 742 #define PICA_CMD_DATA_GS_PROG_DATA(data) (data) 743 744 // PICA_REG_GS_PROG_SWIZZLE_DATA0 0x2a6 to 0x2ad 745 #define PICA_CMD_DATA_GS_PROG_SWIZZLE_DATA(data) (data) 746 747 /////////////////////////////////// 748 // Geometry Shader Attribute Input Register Map 749 /* 750 struct CommandGSAttrInputRegMap0 751 u32 index1 : 4; 752 u32 index2 : 4; 753 u32 index3 : 4; 754 u32 index4 : 4; 755 u32 index5 : 4; 756 u32 index6 : 4; 757 u32 index7 : 4; 758 u32 index8 : 4; 759 }; 760 */ 761 762 // PICA_REG_GS_ATTR_IN_REG_MAP0 0x28b 763 #define PICA_CMD_DATA_GS_ATTR_IN_REG_MAP0(index1, index2, index3, index4, index5, index6, index7, index8) \ 764 ( (index1) | (index2) << 4 | (index3) << 8 | (index4) << 12 | \ 765 (index5) << 16 | (index6) << 20 | (index7) << 24 | (index8) << 28 ) 766 767 /* 768 struct CommandGSAttrInputRegMap1 769 { 770 u32 index9 : 4; 771 u32 index10 : 4; 772 u32 index11 : 4; 773 u32 index12 : 4; 774 CMD_PADDING(16); 775 776 }; 777 */ 778 779 // PICA_REG_GS_ATTR_IN_REG_MAP1 0x28c 780 #define PICA_CMD_DATA_GS_ATTR_IN_MAP1(index9, index10, index11, index12) \ 781 ((index9) | (index10) << 4 | (index11) << 8 | (index12) << 12) 782 783 #define PICA_CMD_SET_GS_ATTR_IN_MAP_RESERVED() \ 784 0x76543210, PICA_CMD_HEADER_SINGLE(PICA_REG_GS_ATTR_IN_REG_MAP0), \ 785 0xfedcba98, PICA_CMD_HEADER_SINGLE(PICA_REG_GS_ATTR_IN_REG_MAP1) 786 787 /////////////////////////////////// 788 // Geometry Misc Registers 789 790 /* Please see man pages for details 791 792 793 */ 794 enum PicaDataGSMode 795 { 796 // 797 PICA_DATA_GS_OTHER_MODE = 0x0, 798 // 799 PICA_DATA_GS_SUBDIVISION_MODE = 0x1, 800 // 801 PICA_DATA_GS_SUBDIVISION_CATMULL_MODE = 0x3, 802 // 803 PICA_DATA_GS_SUBDIVISION_LOOP_MODE = 0x5, 804 // 805 PICA_DATA_GS_PARTICLE_MODE = 0x2 806 }; 807 808 // PICA_REG_GS_MISC_REG0 0x252 809 #define PICA_CMD_DATA_GS_MISC_REG0(mode) \ 810 ( (mode & PICA_DATA_GS_SUBDIVISION_MODE) ? 0x1 : ( (mode == PICA_DATA_GS_PARTICLE_MODE) ? 0x01004302 : 0) ) 811 812 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION() \ 813 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_MODE), \ 814 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 815 816 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION_CATMULL() \ 817 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_CATMULL_MODE), \ 818 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 819 820 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION_LOOP() \ 821 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_LOOP_MODE), \ 822 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 823 824 #define PICA_CMD_SET_GS_MISC_REG0_PARTICLE() \ 825 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_PARTICLE_MODE), \ 826 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 827 828 #define PICA_CMD_SET_GS_MISC_REG0_OTHER() \ 829 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_OTHER_MODE), \ 830 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 831 832 // PICA_REG_GS_MISC_REG1 0x254 833 #define PICA_CMD_DATA_GS_MISC_REG1(mode) \ 834 ( (mode == PICA_DATA_GS_SUBDIVISION_CATMULL_MODE) ? 3 : ( (mode == PICA_DATA_GS_SUBDIVISION_LOOP_MODE) ? 2 : 0) ) 835 836 /////////////////////////////////// 837 // Appendex Registers 838 839 // PICA_REG_START_DRAW_FUNC1 0x25f 840 #define PICA_CMD_DATA_START_DRAW_FUNC1(resetVertexTriangleIndex) \ 841 ( (resetVertexTriangleIndex) ? 1 : 0 ) 842 843 /* 844 845 */ 846 847 #endif // NN_GX_CTR_PICA_MACRO_SHADER_H_ 848