1 /*---------------------------------------------------------------------------* 2 Project: Horizon 3 File: reg_access.h 4 5 Copyright (C)2009 Nintendo Co., Ltd. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Rev: 12449 $ 14 *---------------------------------------------------------------------------*/ 15 16 #ifndef NN_HW_ARM_REG_ACCESS_H_ 17 #define NN_HW_ARM_REG_ACCESS_H_ 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 //TODO: もし CTR 依存のものがあれば切り出す 24 25 //---------------------------------------------------------------------- 26 // instruction level macros 27 // NOTE: 28 // v is a register int variable 29 // a-e are symbols as like as c0, cpsr_c, etc. 30 //---------------------------------------------------------------------- 31 32 // MRS/MSR 33 #define HW_INST_MRS(a,v) __asm { mrs a,v } 34 35 #define HW_INST_MSR(a,v) __asm { msr a,v } 36 37 // MRC/MCR 38 // a: CP, b: Op1, c: CRn, d: CRm, e: Op2 39 #define HW_INST_MRC(a,b,c,d,e,v) __asm { mrc a,b,v,c,d,e } 40 41 #define HW_INST_MCR(a,b,c,d,e,v) __asm { mcr a,b,v,c,d,e } 42 43 /* 44 memo: read only 45 pc: __current_pc() 46 sp: __current_sp() 47 lr: __return_address() 48 */ 49 50 //---------------------------------------------------------------------- 51 // mrs/msr family 52 //---------------------------------------------------------------------- 53 54 #define HW_GET_CPSR(v) HW_INST_MRS(cpsr,v) 55 #define HW_GET_SPSR(v) HW_INST_MRS(spsr,v) 56 57 #define HW_SET_CPSR(f,v) HW_INST_MSR(cpsr_##f,v) // f: fields 58 #define HW_SET_SPSR(f,v) HW_INST_MSR(spsr_##f,v) // f: fields 59 60 //---------------------------------------------------------------------- 61 // cp15 62 //---------------------------------------------------------------------- 63 64 #define HW_GET_CP15_C0(c,o,v) HW_INST_MRC(p15,0,c0,c,o,v) // Opcode_1 is fixed 65 #define HW_GET_CP15_C1(o,v) HW_INST_MRC(p15,0,c1,c0,o,v) // Opcode_1 and CRm are fixed 66 #define HW_GET_CP15_C2(o,v) HW_INST_MRC(p15,0,c2,c0,o,v) // Opcode_1 and CRm are fixed 67 #define HW_GET_CP15_C3(v) HW_INST_MRC(p15,0,c3,c0,0,v) // fixed all 68 #define HW_GET_CP15_C5(o,v) HW_INST_MRC(p15,0,c5,c0,o,v) // Opcode_1 and CRm are fixed 69 #if defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6) 70 #define HW_GET_CP15_C6(o,v) HW_INST_MRC(p15,0,c6,c0,o,v) // Opcode_1 and CRm are fixed 71 #else 72 #define HW_GET_CP15_C6(c,o,v) HW_INST_MRC(p15,0,c6,c,o,v) // Opcode_1 is fixed 73 #endif 74 #define HW_GET_CP15_C7(c,o,v) HW_INST_MRC(p15,0,c7,c,o,v) // Opcode_1 is fixed 75 #define HW_GET_CP15_C8(c,o,v) HW_INST_MRC(p15,0,c8,c,o,v) // Opcode_1 is fixed 76 #if defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6) 77 #define HW_GET_CP15_C9(v) HW_INST_MRC(p15,0,c9,c0,0,v) // fixed all 78 #else 79 #define HW_GET_CP15_C9(o,v) HW_INST_MRC(p15,0,c9,c0,o,v) // Opcode_1 and CRm are fixed 80 #endif 81 #define HW_GET_CP15_C10(c,o,v) HW_INST_MRC(p15,0,c10,c,o,v) // Opcode_1 is fixed 82 #define HW_GET_CP15_C13(o,v) HW_INST_MRC(p15,0,c13,c0,o,v) // Opcode_1 and CRm are fixed 83 #define HW_GET_CP15_C15(o1,c,o2,v) HW_INST_MRC(p15,o1,c15,c,o2,v) // not fixed all 84 85 #define HW_GET_CP15_C15_0(c,o,v) HW_INST_MRC(p15,0,c15,c,o,v) 86 #define HW_GET_CP15_C15_1(c,o,v) HW_INST_MRC(p15,1,c15,c,o,v) 87 #define HW_GET_CP15_C15_2(c,o,v) HW_INST_MRC(p15,2,c15,c,o,v) 88 #define HW_GET_CP15_C15_5(c,o,v) HW_INST_MRC(p15,5,c15,c,o,v) 89 #define HW_GET_CP15_C15_7(v) HW_INST_MRC(p15,7,c15,c1,0,v) 90 91 // NOTE: must set variable not constant 92 93 #define HW_SET_CP15_C0(c,o,v) HW_INST_MCR(p15,0,c0,c,o,v) // Opcode_1 is fixed 94 #define HW_SET_CP15_C1(o,v) HW_INST_MCR(p15,0,c1,c0,o,v) // Opcode_1 and CRm are fixed 95 #define HW_SET_CP15_C2(o,v) HW_INST_MCR(p15,0,c2,c0,o,v) // Opcode_1 and CRm are fixed 96 #define HW_SET_CP15_C3(v) HW_INST_MCR(p15,0,c3,c0,0,v) // fixed all 97 #define HW_SET_CP15_C5(o,v) HW_INST_MCR(p15,0,c5,c0,o,v) // Opcode_1 and CRm are fixed 98 #define HW_SET_CP15_C6(o,v) HW_INST_MCR(p15,0,c6,c0,o,v) // Opcode_1 and CRm are fixed 99 #define HW_SET_CP15_C7(c,o,v) HW_INST_MCR(p15,0,c7,c,o,v) // Opcode_1 is fixed 100 #define HW_SET_CP15_C8(c,o,v) HW_INST_MCR(p15,0,c8,c,o,v) // Opcode_1 is fixed 101 #define HW_SET_CP15_C9(v) HW_INST_MCR(p15,0,c9,c0,0,v) // fixed all 102 #define HW_SET_CP15_C10(c,o,v) HW_INST_MCR(p15,0,c10,c,o,v) // Opcode_1 is fixed 103 #define HW_SET_CP15_C13(o,v) HW_INST_MCR(p15,0,c13,c0,o,v) // Opcode_1 and CRm are fixed 104 #define HW_SET_CP15_C15(o1,c,o2,v) HW_INST_MCR(p15,o1,c15,c,o2,v) // not fixed all 105 106 #define HW_SET_CP15_C15_0(c,o,v) HW_INST_MCR(p15,0,c15,c,o,v) 107 #define HW_SET_CP15_C15_5(c,o,v) HW_INST_MCR(p15,5,c15,c,o,v) 108 #define HW_SET_CP15_C15_7(v) HW_INST_MCR(p15,7,c15,c1,0,v) 109 110 // 111 // special named macro 112 // 113 114 #define HW_GET_CP15_MAIN_ID(v) HW_INST_MRC(p15,0,c0,c0,0,v) 115 #define HW_GET_CP15_CACHE_TYPE(v) HW_INST_MRC(p15,0,c0,c0,1,v) 116 #define HW_GET_CP15_TLB_TYPE(v) HW_INST_MRC(p15,0,c0,c0,3,v) 117 #define HW_GET_CP15_CPU_ID(v) HW_INST_MRC(p15,0,c0,c0,5,v) 118 #define HW_GET_CP15_PFR0(v) HW_INST_MRC(p15,0,c0,c1,0,v) 119 #define HW_GET_CP15_PFR1(v) HW_INST_MRC(p15,0,c0,c1,1,v) 120 #define HW_GET_CP15_DFR0(v) HW_INST_MRC(p15,0,c0,c1,2,v) 121 #define HW_GET_CP15_MMFR0(v) HW_INST_MRC(p15,0,c0,c1,4,v) 122 #define HW_GET_CP15_MMFR1(v) HW_INST_MRC(p15,0,c0,c1,5,v) 123 #define HW_GET_CP15_MMFR2(v) HW_INST_MRC(p15,0,c0,c1,6,v) 124 #define HW_GET_CP15_MMFR3(v) HW_INST_MRC(p15,0,c0,c1,7,v) 125 #define HW_GET_CP15_ISAR0(v) HW_INST_MRC(p15,0,c0,c2,0,v) 126 #define HW_GET_CP15_ISAR1(v) HW_INST_MRC(p15,0,c0,c2,1,v) 127 #define HW_GET_CP15_ISAR2(v) HW_INST_MRC(p15,0,c0,c2,2,v) 128 #define HW_GET_CP15_ISAR3(v) HW_INST_MRC(p15,0,c0,c2,3,v) 129 #define HW_GET_CP15_ISAR4(v) HW_INST_MRC(p15,0,c0,c2,4,v) 130 #define HW_GET_CP15_CONTROL(v) HW_INST_MRC(p15,0,c1,c0,0,v) 131 #define HW_GET_CP15_AUX_CONTROL(v) HW_INST_MRC(p15,0,c1,c0,1,v) 132 #define HW_GET_CP15_COPROCESSOR_ACCESS_CONTROL(v) HW_INST_MRC(p15,0,c1,c0,2,v) 133 #if defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6) 134 #define HW_GET_CP15_TTB0(v) HW_INST_MRC(p15,0,c2,c0,0,v) 135 #define HW_GET_CP15_TTB1(v) HW_INST_MRC(p15,0,c2,c0,1,v) 136 #define HW_GET_CP15_TTB_CONTROL(v) HW_INST_MRC(p15,0,c2,c0,2,v) 137 #define HW_GET_CP15_DOMAIN_ACCESS_CONTROL(v) HW_INST_MRC(p15,0,c3,c0,0,v) 138 #define HW_GET_CP15_DATA_FAULT_STATUS(v) HW_INST_MRC(p15,0,c5,c0,0,v) 139 #define HW_GET_CP15_INSTRUCTION_FAULT_STATUS(v) HW_INST_MRC(p15,0,c5,c0,1,v) 140 #define HW_GET_CP15_DATA_FAULT_ADDRESS(v) HW_INST_MRC(p15,0,c6,c0,0,v) 141 #define HW_GET_CP15_WATCHPOINT_FAULT_ADDRESS(v) HW_INST_MRC(p15,0,c6,c0,1,v) 142 #else 143 #define HW_GET_CP15_CACHE_ENABLE(v) HW_INST_MRC(p15,0,c2,c0,0,v) 144 #define HW_GET_CP15_DATA_CACHE_ENABLE(v) HW_GET_CP15_CACHE_ENABLE(v) 145 #define HW_GET_CP15_INSTRUCTION_CACHE_ENABLE(v) HW_INST_MRC(p15,0,c2,c0,1,v) 146 #define HW_GET_CP15_WRITE_BUFFER_ENABLE(v) HW_INST_MRC(p15,0,c3,c0,0,v) 147 #define HW_GET_CP15_ACCESS_PERMISSION(v) HW_INST_MRC(p15,0,c5,c0,0,v) 148 #define HW_GET_CP15_DATA_ACCESS_PERMISSION(v) HW_GET_CP15_ACCESS_PERMISSION(v) 149 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION(v) HW_INST_MRC(p15,0,c5,c0,1,v) 150 #define HW_GET_CP15_DATA_ACCESS_PERMISSION_EX(v) HW_INST_MRC(p15,0,c5,c0,2,v) 151 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MRC(p15,0,c5,c0,3,v) 152 #define HW_GET_CP15_PROTECTION_REGION_0(v) HW_INST_MRC(p15,0,c6,c0,0,v) 153 #define HW_GET_CP15_PROTECTION_REGION_1(v) HW_INST_MRC(p15,0,c6,c1,0,v) 154 #define HW_GET_CP15_PROTECTION_REGION_2(v) HW_INST_MRC(p15,0,c6,c2,0,v) 155 #define HW_GET_CP15_PROTECTION_REGION_3(v) HW_INST_MRC(p15,0,c6,c3,0,v) 156 #define HW_GET_CP15_PROTECTION_REGION_4(v) HW_INST_MRC(p15,0,c6,c4,0,v) 157 #define HW_GET_CP15_PROTECTION_REGION_5(v) HW_INST_MRC(p15,0,c6,c5,0,v) 158 #define HW_GET_CP15_PROTECTION_REGION_6(v) HW_INST_MRC(p15,0,c6,c6,0,v) 159 #define HW_GET_CP15_PROTECTION_REGION_7(v) HW_INST_MRC(p15,0,c6,c7,0,v) 160 #endif 161 #define HW_GET_CP15_PA(v) HW_INST_MRC(p15,0,c7,c4,0,v) 162 #define HW_GET_CP15_DATA_CACHE_LOCKDOWN(v) HW_INST_MRC(p15,0,c9,c0,0,v) 163 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 164 #define HW_GET_CP15_INSTRUCTION_CACHE_LOCKDOWN(v) HW_INST_MRC(p15,0,c9,c0,1,v) 165 #define HW_GET_CP15_DTCM(v) HW_INST_MRC(p15,0,c9,c1,0,v) 166 #define HW_GET_CP15_ITCM(v) HW_INST_MRC(p15,0,c9,c1,1,v) 167 #endif 168 #define HW_GET_CP15_TLB_LOCKDOWN(v) HW_INST_MRC(p15,0,c10,c0,0,v) 169 #define HW_GET_CP15_PRIMARY_REGION_REMAP(v) HW_INST_MRC(p15,0,c10,c2,0,v) 170 #define HW_GET_CP15_NORMAL_REGION_REMAP(v) HW_INST_MRC(p15,0,c10,c2,1,v) 171 #define HW_GET_CP15_FSCSE_PID(v) HW_INST_MRC(p15,0,c13,c0,0,v) 172 #define HW_GET_CP15_CONTEXT_ID(v) HW_INST_MRC(p15,0,c13,c0,1,v) 173 #define HW_GET_CP15_THREAD_ID(v) HW_INST_MRC(p15,0,c13,c0,2,v) 174 #define HW_GET_CP15_THREAD_ID_USER_READ_ONLY(v) HW_INST_MRC(p15,0,c13,c0,3,v) 175 #define HW_GET_CP15_THREAD_ID_PRIVILEGED_ONLY(v) HW_INST_MRC(p15,0,c13,c0,4,v) 176 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 177 #define HW_GET_CP15_TEST_STATE(v) HW_INST_MRC(p15,0,c15,c0,0,v) 178 #define HW_GET_CP15_INSTRUCTIN_TAG_BIST_ADDRESS(v) HW_INST_MRC(p15,0,c15,c0,2,v) 179 #define HW_GET_CP15_INSTRUCTIN_TAG_BIST_GENERAL(v) HW_INST_MRC(p15,0,c15,c0,3,v) 180 #define HW_GET_CP15_DATA_TAG_BIST_ADDRESS(v) HW_INST_MRC(p15,0,c15,c0,6,v) 181 #define HW_GET_CP15_DATA_TAG_BIST_GENERAL(v) HW_INST_MRC(p15,0,c15,c0,7,v) 182 #define HW_GET_CP15_ITCM_BIST_ADDRESS(v) HW_INST_MRC(p15,1,c15,c0,2,v) 183 #define HW_GET_CP15_ITCM_BIST_GENERAL(v) HW_INST_MRC(p15,1,c15,c0,3,v) 184 #define HW_GET_CP15_DTCM_BIST_ADDRESS(v) HW_INST_MRC(p15,1,c15,c0,6,v) 185 #define HW_GET_CP15_DTCM_BIST_GENERAL(v) HW_INST_MRC(p15,1,c15,c0,7,v) 186 #define HW_GET_CP15_TRACE_STATE_CONTROL(v) HW_INST_MRC(p15,1,c15,c1,0,v) 187 #define HW_GET_CP15_INSTRUCTIN_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MRC(p15,2,c15,c0,2,v) 188 #define HW_GET_CP15_INSTRUCTIN_CACHE_RAM_BIST_GENERAL(v) HW_INST_MRC(p15,2,c15,c0,3,v) 189 #define HW_GET_CP15_DATA_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MRC(p15,2,c15,c0,6,v) 190 #define HW_GET_CP15_DATA_CACHE_RAM_BIST_GENERAL(v) HW_INST_MRC(p15,2,c15,c0,7,v) 191 #endif 192 #define HW_GET_CP15_PERFORMANCE_MONITOR_CONTROL(v) HW_INST_MRC(p15,0,c15,c12,0,v) 193 #define HW_GET_CP15_CCNT(v) HW_INST_MRC(p15,0,c15,c12,1,v) 194 #define HW_GET_CP15_PMN0(v) HW_INST_MRC(p15,0,c15,c12,2,v) 195 #define HW_GET_CP15_PMN1(v) HW_INST_MRC(p15,0,c15,c12,3,v) 196 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 197 #define HW_GET_CP15_CACHE_DEBUG_INDEX(v) HW_INST_MRC(p15,3,c15,c0,0,v) 198 #define HW_GET_CP15_INSTRUCTION_TAG(v) HW_INST_MRC(p15,3,c15,c1,0,v) 199 #define HW_GET_CP15_DATA_TAG(v) HW_INST_MRC(p15,3,c15,c2,0,v) 200 #define HW_GET_CP15_INSTRUCTION_CACHE(v) HW_INST_MRC(p15,3,c15,c3,0,v) 201 #define HW_GET_CP15_DATA_CACHE(v) HW_INST_MRC(p15,3,c15,c4,0,v) 202 #endif 203 #define HW_GET_CP15_MAIN_TLB_LOCKDOWN_VA(v) HW_INST_MRC(p15,5,c15,c5,2,v) 204 #define HW_GET_CP15_MAIN_TLB_LOCKDOWN_PA(v) HW_INST_MRC(p15,5,c15,c6,2,v) 205 #define HW_GET_CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE(v) HW_INST_MRC(p15,5,c15,c7,2,v) 206 #define HW_GET_CP15_TLB_DEBUG_CONTROL(v) HW_INST_MRC(p15,7,c15,c1,0,v) 207 208 #define HW_SET_CP15_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,0,v) 209 #define HW_SET_CP15_AUX_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,1,v) 210 #define HW_SET_CP15_COPROCESSOR_ACCESS_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,2,v) 211 #if defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6) 212 #define HW_SET_CP15_TTB0(v) HW_INST_MCR(p15,0,c2,c0,0,v) 213 #define HW_SET_CP15_TTB1(v) HW_INST_MCR(p15,0,c2,c0,1,v) 214 #define HW_SET_CP15_TTB_CONTROL(v) HW_INST_MCR(p15,0,c2,c0,2,v) 215 #define HW_SET_CP15_DOMAIN_ACCESS_CONTROL(v) HW_INST_MCR(p15,0,c3,c0,0,v) 216 #define HW_SET_CP15_DATA_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,0,v) 217 #define HW_SET_CP15_INSTRUCTION_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,1,v) 218 #define HW_SET_CP15_DATA_FAULT_ADDRESS(v) HW_INST_MCR(p15,0,c6,c0,0,v) 219 #define HW_SET_CP15_WATCHPOINT_FAULT_ADDRESS(v) HW_INST_MCR(p15,0,c6,c0,1,v) 220 #else 221 #define HW_SET_CP15_CACHE_ENABLE(v) HW_INST_MCR(p15,0,c2,c0,0,v) 222 #define HW_SET_CP15_DATA_CACHE_ENABLE(v) HW_SET_CP15_CACHE_ENABLE(v) 223 #define HW_SET_CP15_INSTRUCTION_CACHE_ENABLE(v) HW_INST_MCR(p15,0,c2,c0,1,v) 224 #define HW_SET_CP15_WRITE_BUFFER_ENABLE(v) HW_INST_MCR(p15,0,c3,c0,0,v) 225 #define HW_SET_CP15_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,0,v) 226 #define HW_SET_CP15_DATA_ACCESS_PERMISSION(v) HW_SET_CP15_ACCESS_PERMISSION(v) 227 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,1,v) 228 #define HW_SET_CP15_DATA_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,2,v) 229 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,3,v) 230 #define HW_SET_CP15_PROTECTION_REGION_0(v) HW_INST_MCR(p15,0,c6,c0,0,v) 231 #define HW_SET_CP15_PROTECTION_REGION_1(v) HW_INST_MCR(p15,0,c6,c1,0,v) 232 #define HW_SET_CP15_PROTECTION_REGION_2(v) HW_INST_MCR(p15,0,c6,c2,0,v) 233 #define HW_SET_CP15_PROTECTION_REGION_3(v) HW_INST_MCR(p15,0,c6,c3,0,v) 234 #define HW_SET_CP15_PROTECTION_REGION_4(v) HW_INST_MCR(p15,0,c6,c4,0,v) 235 #define HW_SET_CP15_PROTECTION_REGION_5(v) HW_INST_MCR(p15,0,c6,c5,0,v) 236 #define HW_SET_CP15_PROTECTION_REGION_6(v) HW_INST_MCR(p15,0,c6,c6,0,v) 237 #define HW_SET_CP15_PROTECTION_REGION_7(v) HW_INST_MCR(p15,0,c6,c7,0,v) 238 #endif 239 #define HW_SET_CP15_WFI(v) HW_INST_MCR(p15,0,c7,c0,4,v) 240 #define HW_SET_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE(v) HW_INST_MCR(p15,0,c7,c5,0,v) 241 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c5,1,v) 242 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c5,2,v) 243 #define HW_SET_CP15_FLUSH_PREFETCH_BUFFER(v) HW_INST_MCR(p15,0,c7,c5,4,v) 244 #define HW_SET_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE(v) HW_INST_MCR(p15,0,c7,c5,6,v) 245 #define HW_SET_CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY(v) HW_INST_MCR(p15,0,c7,c5,7,v) 246 #define HW_SET_CP15_INVALIDATE_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c6,0,v) 247 #define HW_SET_CP15_INVALIDATE_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c6,1,v) 248 #define HW_SET_CP15_INVALIDATE_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c6,2,v) 249 #define HW_SET_CP15_INVALIDATE_BOTH_CACHE(v) HW_INST_MCR(p15,0,c7,c7,0,v) 250 #define HW_SET_CP15_VA_TO_PA_PRIVILEGED_READ(v) HW_INST_MCR(p15,0,c7,c8,0,v) 251 #define HW_SET_CP15_VA_TO_PA_PRIVILEGED_WRITE(v) HW_INST_MCR(p15,0,c7,c8,1,v) 252 #define HW_SET_CP15_VA_TO_PA_USER_READ(v) HW_INST_MCR(p15,0,c7,c8,2,v) 253 #define HW_SET_CP15_VA_TO_PA_USER_WRITE(v) HW_INST_MCR(p15,0,c7,c8,3,v) 254 #define HW_SET_CP15_CLEAN_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c10,0,v) 255 #define HW_SET_CP15_CLEAN_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c10,1,v) 256 #define HW_SET_CP15_CLEAN_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c10,2,v) 257 #define HW_SET_CP15_DATA_SYNC_BARRIER(v) HW_INST_MCR(p15,0,c7,c10,4,v) 258 #define HW_SET_CP15_DATA_MEMORY_BARRIER(v) HW_INST_MCR(p15,0,c7,c10,5,v) 259 #define HW_SET_CP15_CLEAN_INVALIDATE_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c14,0,v) 260 #define HW_SET_CP15_CLEAN_INVALIDATE_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c14,1,v) 261 #define HW_SET_CP15_CLEAN_INVALIDATE_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c14,2,v) 262 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB(v) HW_INST_MCR(p15,0,c8,c5,0,v) 263 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c5,1,v) 264 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c5,2,v) 265 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c5,3,v) 266 #define HW_SET_CP15_INVALIDATE_DATA_TLB(v) HW_INST_MCR(p15,0,c8,c6,0,v) 267 #define HW_SET_CP15_INVALIDATE_DATA_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c6,1,v) 268 #define HW_SET_CP15_INVALIDATE_DATA_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c6,2,v) 269 #define HW_SET_CP15_INVALIDATE_DATA_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c6,3,v) 270 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB(v) HW_INST_MCR(p15,0,c8,c7,0,v) 271 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c7,1,v) 272 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c7,2,v) 273 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c7,3,v) 274 #define HW_SET_CP15_DATA_CACHE_LOCKDOWN(v) HW_INST_MCR(p15,0,c9,c0,0,v) 275 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 276 #define HW_SET_CP15_INSTRUCTION_CACHE_LOCKDOWN(v) HW_INST_MCR(p15,0,c9,c0,1,v) 277 #define HW_SET_CP15_DTCM(v) HW_INST_MCR(p15,0,c9,c1,0,v) 278 #define HW_SET_CP15_ITCM(v) HW_INST_MCR(p15,0,c9,c1,1,v) 279 #endif 280 #define HW_SET_CP15_PRIMARY_REGION_REMAP(v) HW_INST_MCR(p15,0,c10,c2,0,v) 281 #define HW_SET_CP15_NORMAL_REGION_REMAP(v) HW_INST_MCR(p15,0,c10,c2,1,v) 282 #define HW_SET_CP15_FSCSE_PID(v) HW_INST_MCR(p15,0,c13,c0,0,v) 283 #define HW_SET_CP15_CONTEXT_ID(v) HW_INST_MCR(p15,0,c13,c0,1,v) 284 #define HW_SET_CP15_THREAD_ID(v) HW_INST_MCR(p15,0,c13,c0,2,v) 285 #define HW_SET_CP15_THREAD_ID_USER_READ_ONLY(v) HW_INST_MCR(p15,0,c13,c0,3,v) 286 #define HW_SET_CP15_THREAD_ID_PRIVILEGED_ONLY(v) HW_INST_MCR(p15,0,c13,c0,4,v) 287 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 288 #define HW_SET_CP15_TEST_STATE(v) HW_INST_MCR(p15,0,c15,c0,0,v) 289 #define HW_SET_CP15_INSTRUCTIN_TAG_BIST_ADDRESS(v) HW_INST_MCR(p15,0,c15,c0,2,v) 290 #define HW_SET_CP15_INSTRUCTIN_TAG_BIST_GENERAL(v) HW_INST_MCR(p15,0,c15,c0,3,v) 291 #define HW_SET_CP15_DATA_TAG_BIST_ADDRESS(v) HW_INST_MCR(p15,0,c15,c0,6,v) 292 #define HW_SET_CP15_DATA_TAG_BIST_GENERAL(v) HW_INST_MCR(p15,0,c15,c0,7,v) 293 #define HW_SET_CP15_ITCM_BIST_ADDRESS(v) HW_INST_MCR(p15,1,c15,c0,2,v) 294 #define HW_SET_CP15_ITCM_BIST_GENERAL(v) HW_INST_MCR(p15,1,c15,c0,3,v) 295 #define HW_SET_CP15_DTCM_BIST_ADDRESS(v) HW_INST_MCR(p15,1,c15,c0,6,v) 296 #define HW_SET_CP15_DTCM_BIST_GENERAL(v) HW_INST_MCR(p15,1,c15,c0,7,v) 297 #define HW_SET_CP15_TRACE_STATE_CONTROL(v) HW_INST_MCR(p15,1,c15,c1,0,v) 298 #define HW_SET_CP15_INSTRUCTIN_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MCR(p15,2,c15,c0,2,v) 299 #define HW_SET_CP15_INSTRUCTIN_CACHE_RAM_BIST_GENERAL(v) HW_INST_MCR(p15,2,c15,c0,3,v) 300 #define HW_SET_CP15_DATA_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MCR(p15,2,c15,c0,6,v) 301 #define HW_SET_CP15_DATA_CACHE_RAM_BIST_GENERAL(v) HW_INST_MCR(p15,2,c15,c0,7,v) 302 #endif 303 #define HW_SET_CP15_PERFORMANCE_MONITOR_CONTROL(v) HW_INST_MCR(p15,0,c15,c12,0,v) 304 #define HW_SET_CP15_CCNT(v) HW_INST_MCR(p15,0,c15,c12,1,v) 305 #define HW_SET_CP15_PMN0(v) HW_INST_MCR(p15,0,c15,c12,2,v) 306 #define HW_SET_CP15_PMN1(v) HW_INST_MCR(p15,0,c15,c12,3,v) 307 #define HW_SET_CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY(v) HW_INST_MCR(p15,0,c15,c4,2,v) 308 #define HW_SET_CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY(v) HW_INST_MCR(p15,0,c15,c4,4,v) 309 #if ! (defined(SDK_ARM11) || defined(NN_PROCESSOR_ARM_V6)) 310 #define HW_SET_CP15_CACHE_DEBUG_INDEX(v) HW_INST_MCR(p15,3,c15,c0,0,v) 311 #define HW_SET_CP15_INSTRUCTION_TAG(v) HW_INST_MCR(p15,3,c15,c1,0,v) 312 #define HW_SET_CP15_DATA_TAG(v) HW_INST_MCR(p15,3,c15,c2,0,v) 313 #define HW_SET_CP15_INSTRUCTION_CACHE(v) HW_INST_MCR(p15,3,c15,c3,0,v) 314 #define HW_SET_CP15_DATA_CACHE(v) HW_INST_MCR(p15,3,c15,c4,0,v) 315 #endif 316 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_VA(v) HW_INST_MCR(p15,5,c15,c5,2,v) 317 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_PA(v) HW_INST_MCR(p15,5,c15,c6,2,v) 318 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE(v) HW_INST_MCR(p15,5,c15,c7,2,v) 319 #define HW_SET_CP15_TLB_DEBUG_CONTROL(v) HW_INST_MCR(p15,7,c15,c1,0,v) 320 321 // 322 // static input value 323 // 324 #define HW_CP15_WFI() HW_INST_MCR(p15,0,c7,c0,4,0) 325 #define HW_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE() HW_INST_MCR(p15,0,c7,c5,0,0) 326 #define HW_CP15_FLUSH_PREFETCH_BUFFER() HW_INST_MCR(p15,0,c7,c5,4,0) 327 #define HW_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE() HW_INST_MCR(p15,0,c7,c5,6,0) 328 #define HW_CP15_INVALIDATE_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c6,0,0) 329 #define HW_CP15_INVALIDATE_BOTH_CACHE() HW_INST_MCR(p15,0,c7,c7,0,0) 330 #define HW_CP15_CLEAN_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c10,0,0) 331 #define HW_CP15_DATA_SYNC_BARRIER() HW_INST_MCR(p15,0,c7,c10,4,0) 332 #define HW_CP15_DATA_MEMORY_BARRIER() HW_INST_MCR(p15,0,c7,c10,5,0) 333 #define HW_CP15_CLEAN_INVALIDATE_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c14,0,0) 334 #define HW_CP15_INVALIDATE_INSTRUCTION_TLB() HW_INST_MCR(p15,0,c8,c5,0,0) 335 #define HW_CP15_INVALIDATE_DATA_TLB() HW_INST_MCR(p15,0,c8,c6,0,0) 336 #define HW_CP15_INVALIDATE_UNIFIED_TLB() HW_INST_MCR(p15,0,c8,c7,0,0) 337 338 339 #ifdef __cplusplus 340 } // extern "C" 341 #endif 342 343 // NN_HW_ARM_REG_ACCESS_H_ 344 #endif 345