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8<TITLE>System Configuration Library (SCFG) API Function List</TITLE>
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12<H1>System Configuration Library (SCFG) API Function List</H1>
13<H3><A name="Config">Configuration Functions</A></H3>
14<TABLE border="1" width="100%">
15   <TBODY>
16   <TR>
17<TH width=25%><a href="scfg/SCFG_GetSystemRomType.html" target="_self">SCFG_GetSystemRomType</a></TH>
18    <TD width="48"><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
19<TD>Determines the system ROM type.</TD>
20   </TR>
21   <TR>
22<TH><a href="scfg/SCFG_IsSecureRomAccessible.html" target="_self">SCFG_IsSecureRomAccessible</a></TH>
23    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
24<TD>Determines if ARM9 secure ROM is accessible.</TD>
25   </TR>
26 <TR><TD style="background:blue;" colspan=3></TD></TR>
27   <TR>
28<TH><a href="scfg/SCFG_SetCameraCKIClock.html" target="_self">SCFG_SetCameraCKIClock</a></TH>
29    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
30<TD>Controls the CAM_CKI clock for the camera.</TD>
31   </TR>
32   <TR>
33<TH><a href="scfg/SCFG_IsCameraCKIClockEnable.html" target="_self">SCFG_IsCameraCKIClockEnable</a></TH>
34    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
35<TD>Determines the state of the CAM_CKI clock for the camera.</TD>
36   </TR>
37   <TR>
38<TH><a href="scfg/SCFG_SupplyClockToCamera.html" target="_self">SCFG_SupplyClockToCamera</a></TH>
39    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
40<TD>Configures the clock supply to the camera block.</TD>
41   </TR>
42   <TR>
43<TH><a href="scfg/SCFG_IsClockSuppliedToCamera.html" target="_self">SCFG_IsClockSuppliedToCamera</a></TH>
44    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
45<TD>Determines the clock supply setting for the camera block.</TD>
46   </TR>
47   <TR>
48<TH><a href="scfg/SCFG_SupplyClockToDSP.html" target="_self">SCFG_SupplyClockToDSP</a></TH>
49    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
50<TD>Configures the clock supply to the DSP block.</TD>
51   </TR>
52   <TR>
53<TH><a href="scfg/SCFG_IsClockSuppliedToDSP.html" target="_self">SCFG_IsClockSuppliedToDSP</a></TH>
54    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
55<TD>Determines the clock supply setting for the DSP block.</TD>
56   </TR>
57   <TR>
58<TH><a href="scfg/SCFG_IsClockSuppliedToWram.html" target="_self">SCFG_IsClockSuppliedToWram</a></TH>
59    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
60<TD>Gets the clock supply setting for the WRAM block.</TD>
61   </TR>
62 <TR><TD style="background:blue;" colspan=3></TD></TR>
63   <TR>
64<TH><a href="scfg/SCFG_SetCpuSpeed.html" target="_self">SCFG_SetCpuSpeed</a></TH>
65    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
66<TD>Configures the operating speed for the ARM9 CPU.</TD>
67   </TR>
68   <TR>
69<TH><a href="scfg/SCFG_GetCpuSpeed.html" target="_self">SCFG_GetCpuSpeed</a></TH>
70    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
71<TD>Determines the operating speed configured for the ARM9 CPU.</TD>
72   </TR>
73 <TR><TD style="background:blue;" colspan=3></TD></TR>
74   <TR>
75<TH><a href="scfg/SCFG_ResetDSP.html" target="_self">SCFG_ResetDSP</a></TH>
76    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
77<TD>Outputs a reset signal to the DSP block.</TD>
78   </TR>
79   <TR>
80<TH><a href="scfg/SCFG_ReleaseResetDSP.html" target="_self">SCFG_ReleaseResetDSP</a></TH>
81    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
82<TD>Cancels reset signal output to the DSP block.</TD>
83   </TR>
84   <TR>
85<TH><a href="scfg/SCFG_IsDSPReset.html" target="_self">SCFG_IsDSPReset</a></TH>
86    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
87<TD>Determines the state of reset signal output to the DSP block.</TD>
88   </TR>
89 <TR><TD style="background:blue;" colspan=3></TD></TR>
90   <TR>
91<TH><a href="scfg/SCFG_SetConfigBlockInaccessible.html" target="_self">SCFG_SetConfigBlockInaccessible</a></TH>
92    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
93<TD>Prohibits access to the ARM9 configuration block.</TD>
94   </TR>
95   <TR>
96<TH><a href="scfg/SCFG_IsConfigBlockAccessible.html" target="_self">SCFG_IsConfigBlockAccessible</a></TH>
97    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
98<TD>Determines if the ARM9 configuration block is accessible.</TD>
99   </TR>
100   <TR>
101<TH><a href="scfg/SCFG_IsWramAccessible.html" target="_self">SCFG_IsWramAccessible</a></TH>
102    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
103<TD>Determines if the new WRAM is accessible from any block.</TD>
104   </TR>
105   <TR>
106<TH><a href="scfg/SCFG_SetDSPAccessible.html" target="_self">SCFG_SetDSPAccessible</a></TH>
107    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
108<TD>Configures access to the DSP block.</TD>
109   </TR>
110   <TR>
111<TH><a href="scfg/SCFG_IsDSPAccessible.html" target="_self">SCFG_IsDSPAccessible</a></TH>
112    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
113<TD>Determines if the DSP block is accessible.</TD>
114   </TR>
115   <TR>
116<TH><a href="scfg/SCFG_SetCameraAccessible.html" target="_self">SCFG_SetCameraAccessible</a></TH>
117    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
118<TD>Configures access to the camera block.</TD>
119   </TR>
120   <TR>
121<TH><a href="scfg/SCFG_IsCameraAccessible.html" target="_self">SCFG_IsCameraAccessible</a></TH>
122    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
123<TD>Determines if the camera block is accessible.</TD>
124   </TR>
125   <TR>
126<TH><a href="scfg/SCFG_SetNDmaAccessible.html" target="_self">SCFG_SetNDmaAccessible</a></TH>
127    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
128<TD>Configures access to the new DMA block.</TD>
129   </TR>
130   <TR>
131<TH><a href="scfg/SCFG_IsNDmaAccessible.html" target="_self">SCFG_IsNDmaAccessible</a></TH>
132    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
133<TD>Determines if the new DMA block is accessible.</TD>
134   </TR>
135 <TR><TD style="background:blue;" colspan=3></TD></TR>
136   <TR>
137<TH><a href="scfg/SCFG_SetIntcExpanded.html" target="_self">SCFG_SetIntcExpanded</a></TH>
138    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
139<TD>Configures the use of extensions to the interrupt controller circuit.</TD>
140   </TR>
141   <TR>
142<TH><a href="scfg/SCFG_IsIntcExpanded.html" target="_self">SCFG_IsIntcExpanded</a></TH>
143    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
144<TD>Determines if the interrupt controller circuit is configured to use extensions.</TD>
145   </TR>
146   <TR>
147<TH><a href="scfg/SCFG_SetLCDCExpanded.html" target="_self">SCFG_SetLCDCExpanded</a></TH>
148    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
149<TD>Configures the use of extensions to the LCDC circuit.</TD>
150   </TR>
151   <TR>
152<TH><a href="scfg/SCFG_IsLCDCExpanded.html" target="_self">SCFG_IsLCDCExpanded</a></TH>
153    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
154<TD>Determines if the LCDC circuit is configured to use extensions.</TD>
155   </TR>
156   <TR>
157<TH><a href="scfg/SCFG_SetVramExpanded.html" target="_self">SCFG_SetVramExpanded</a></TH>
158    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
159<TD>Configures the use of extensions for accessing VRAM.</TD>
160   </TR>
161   <TR>
162<TH><a href="scfg/SCFG_IsVramExpanded.html" target="_self">SCFG_IsVramExpanded</a></TH>
163    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
164<TD>Configures the use of VRAM extensions.</TD>
165   </TR>
166   <TR>
167<TH><a href="scfg/SCFG_SetPsramBoundary.html" target="_self">SCFG_SetPsramBoundary</a></TH>
168    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
169<TD>Configures PSRAM access boundaries.</TD>
170   </TR>
171   <TR>
172<TH><a href="scfg/SCFG_GetPsramBoundary.html" target="_self">SCFG_GetPsramBoundary</a></TH>
173    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
174<TD>Determines the configured PSRAM access boundaries.</TD>
175   </TR>
176 <TR><TD style="background:blue;" colspan=3></TD></TR>
177   <TR>
178<TH><a href="scfg/SCFG_SetCardFixed.html" target="_self">SCFG_SetCardFixed</a></TH>
179    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
180<TD>Configures the use of revisions to the memory card I/F circuit.</TD>
181   </TR>
182   <TR>
183<TH><a href="scfg/SCFG_IsCardFixed.html" target="_self">SCFG_IsCardFixed</a></TH>
184    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
185<TD>Determines if revisions are configured to be used for the memory card I/F circuit.</TD>
186   </TR>
187    <TR>
188<TH><a href="scfg/SCFG_SetDividerFixed.html" target="_self">SCFG_SetDividerFixed</a></TH>
189    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
190<TD>Configures the use of revisions to the divider circuit.</TD>
191   </TR>
192   <TR>
193<TH><a href="scfg/SCFG_IsDividerFixed.html" target="_self">SCFG_IsDividerFixed</a></TH>
194    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
195<TD>Determines if revisions are configured to be used for the divider circuit.</TD>
196   </TR>
197   <TR>
198<TH><a href="scfg/SCFG_Set2DEngineFixed.html" target="_self">SCFG_Set2DEngineFixed</a></TH>
199    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
200<TD>Configures the use of revisions to the 2D engine circuit.</TD>
201   </TR>
202   <TR>
203<TH><a href="scfg/SCFG_Is2DEngineFixed.html" target="_self">SCFG_Is2DEngineFixed</a></TH>
204    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
205<TD>Determines if revisions are configured to be used for the 2D engine circuit.</TD>
206   </TR>
207   <TR>
208<TH><a href="scfg/SCFG_SetRendererFixed.html" target="_self">SCFG_SetRendererFixed</a></TH>
209    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
210<TD>Configures the use of revisions to the renderer circuit.</TD>
211   </TR>
212   <TR>
213<TH><a href="scfg/SCFG_IsRendererFixed.html" target="_self">SCFG_IsRendererFixed</a></TH>
214    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
215<TD>Determines if revisions are configured to be used for the renderer circuit.</TD>
216   </TR>
217   <TR>
218<TH><a href="scfg/SCFG_SetGeometryFixed.html" target="_self">SCFG_SetGeometryFixed</a></TH>
219    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
220<TD>Configures the use of revisions to the geometry circuit.</TD>
221   </TR>
222   <TR>
223<TH><a href="scfg/SCFG_IsGeometryFixed.html" target="_self">SCFG_IsGeometryFixed</a></TH>
224    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
225<TD>Determines if revisions are configured to be used for the geometry circuit.</TD>
226   </TR>
227   <TR>
228<TH><a href="scfg/SCFG_SetDmacFixed.html" target="_self">SCFG_SetDmacFixed</a></TH>
229    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
230<TD>Configures the use of revisions to the old DMA circuit.</TD>
231   </TR>
232   <TR>
233<TH><a href="scfg/SCFG_IsDmacFixed.html" target="_self">SCFG_IsDmacFixed</a></TH>
234    <TD><img src="../image/BPT.gif"><img src="../image/TWL.gif"></TD>
235<TD>Determines if revisions are configured to be used for the old DMA circuit.</TD>
236   </TR>
237
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