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9<title>ICFreeze</title>
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13
14<h1>ICFreeze</h1>
15
16
17<h2>C Specification</h2>
18
19<dl>
20<dd><pre><code>#include &lt;revolution/os.h&gt;</code></pre>
21  </dd>
22<dd><pre><code>void ICFreeze ( void );</code></pre>
23  </dd>
24</dl>
25<H2>Arguments</H2>
26<P>None.</P>
27<H2>Return Values</H2>
28<P>None.</P>
29<h2>Description</h2>
30
31<p>Current contents of the L1 instruction cache are locked and will not be invalidated. Hits are still serviced but misses go straight to the L2 instruction cache or 60x bus.</p>
32
33<p>In PowerPC architecture jargon, this feature is referred to as locking the instruction cache.&nbsp;Under Revolution, we use freeze to distinguish between the locked cache and DMA features.</p>
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36
37<h2>See Also</h2>
38
39<p><a href="../toc.html#Cache" target="contents">Cache Functions</a>, <br> <code><a href="ICUnfreeze.html">ICUnfreeze</a>, <a href="DCUnfreeze.html">DCUnfreeze</a>, <a href="DCFreeze.html">DCFreeze</a></code></p>
40
41<h2>Revision History</h2>
42<P>2006/03/01 Initial version.</p>
43<hr>
44<P>CONFIDENTIAL</p>
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