1 /*---------------------------------------------------------------------------*
2 Project: TwlSDK - MI - include
3 File: exMemory.h
4
5 Copyright 2003-2008 Nintendo. All rights reserved.
6
7 These coded instructions, statements, and computer programs contain
8 proprietary information of Nintendo of America Inc. and/or Nintendo
9 Company Ltd., and are protected by Federal copyright law. They may
10 not be disclosed to third parties or copied or duplicated in any form,
11 in whole or in part, without the prior written consent of Nintendo.
12
13 $Date:: 2008-09-18#$
14 $Rev: 8573 $
15 $Author: okubata_ryoma $
16
17 *---------------------------------------------------------------------------*/
18
19 #ifndef NITRO_MI_EXMEMORY_H_
20 #define NITRO_MI_EXMEMORY_H_
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 #ifdef SDK_NITRO
27 #include <nitro/ioreg.h>
28 #else
29 #include <twl/ioreg.h>
30 #endif
31
32 #include <nitro/types.h>
33 #include <nitro/misc.h>
34
35 //----------------------------------------------------------------
36 // alias for ARM7
37
38 #ifdef SDK_ARM7
39 #define reg_MI_EXMEMCNT reg_MI_EXMEMCNT_L
40
41 #define REG_MI_EXMEMCNT_EP_SHIFT REG_MI_EXMEMCNT_L_EP_SHIFT
42 #define REG_MI_EXMEMCNT_EP_SIZE REG_MI_EXMEMCNT_L_EP_SIZE
43 #define REG_MI_EXMEMCNT_EP_MASK REG_MI_EXMEMCNT_L_EP_MASK
44
45 #define REG_MI_EXMEMCNT_MP_SHIFT REG_MI_EXMEMCNT_L_MP_SHIFT
46 #define REG_MI_EXMEMCNT_MP_SIZE REG_MI_EXMEMCNT_L_MP_SIZE
47 #define REG_MI_EXMEMCNT_MP_MASK REG_MI_EXMEMCNT_L_MP_MASK
48
49 #define REG_MI_EXMEMCNT_CP_SHIFT REG_MI_EXMEMCNT_L_CP_SHIFT
50 #define REG_MI_EXMEMCNT_CP_SIZE REG_MI_EXMEMCNT_L_CP_SIZE
51 #define REG_MI_EXMEMCNT_CP_MASK REG_MI_EXMEMCNT_L_CP_MASK
52
53 #define REG_MI_EXMEMCNT_PHI_SHIFT REG_MI_EXMEMCNT_L_PHI_SHIFT
54 #define REG_MI_EXMEMCNT_PHI_SIZE REG_MI_EXMEMCNT_L_PHI_SIZE
55 #define REG_MI_EXMEMCNT_PHI_MASK REG_MI_EXMEMCNT_L_PHI_MASK
56
57 #define REG_MI_EXMEMCNT_ROM2nd_SHIFT REG_MI_EXMEMCNT_L_ROM2nd_SHIFT
58 #define REG_MI_EXMEMCNT_ROM2nd_SIZE REG_MI_EXMEMCNT_L_ROM2nd_SIZE
59 #define REG_MI_EXMEMCNT_ROM2nd_MASK REG_MI_EXMEMCNT_L_ROM2nd_MASK
60
61 #define REG_MI_EXMEMCNT_ROM1st_SHIFT REG_MI_EXMEMCNT_L_ROM1st_SHIFT
62 #define REG_MI_EXMEMCNT_ROM1st_SIZE REG_MI_EXMEMCNT_L_ROM1st_SIZE
63 #define REG_MI_EXMEMCNT_ROM1st_MASK REG_MI_EXMEMCNT_L_ROM1st_MASK
64
65 #define REG_MI_EXMEMCNT_RAM_SHIFT REG_MI_EXMEMCNT_L_RAM_SHIFT
66 #define REG_MI_EXMEMCNT_RAM_SIZE REG_MI_EXMEMCNT_L_RAM_SIZE
67 #define REG_MI_EXMEMCNT_RAM_MASK REG_MI_EXMEMCNT_L_RAM_MASK
68 #endif // SDK_ARM7
69
70 //----------------------------------------------------------------
71 //---- Access priority
72 typedef enum
73 {
74 MI_PROCESSOR_ARM9 = 0, // Main processor
75 MI_PROCESSOR_ARM7 = 1 // Sub processor
76 }
77 MIProcessor;
78
79 //---- PHI output control
80 typedef enum
81 {
82 MIi_PHI_CLOCK_LOW = 0, // Low level
83 MIi_PHI_CLOCK_4MHZ = 1, // 4.19 MHz
84 MIi_PHI_CLOCK_8MHZ = 2, // 8.38 MHz
85 MIi_PHI_CLOCK_16MHZ = 3 // 16.76 MHz
86 }
87 MIiPhiClock;
88
89 //---- cartridge ROM 1st access cycle
90 typedef enum
91 {
92 MI_CTRDG_ROMCYCLE1_10 = 0, // 10 cycle
93 MI_CTRDG_ROMCYCLE1_8 = 1, // 8 cycle
94 MI_CTRDG_ROMCYCLE1_6 = 2, // 6 cycle
95 MI_CTRDG_ROMCYCLE1_18 = 3 // 18 cycle
96 }
97 MICartridgeRomCycle1st;
98
99 //---- cartridge ROM 2nd access cycle
100 typedef enum
101 {
102 MI_CTRDG_ROMCYCLE2_6 = 0, // 6 cycle
103 MI_CTRDG_ROMCYCLE2_4 = 1 // 4 cycle
104 }
105 MICartridgeRomCycle2nd;
106
107 //---- cartridge RAM access cycle
108 typedef enum
109 {
110 MI_CTRDG_RAMCYCLE_10 = 0, // 10 cycle
111 MI_CTRDG_RAMCYCLE_8 = 1, // 8 cycle
112 MI_CTRDG_RAMCYCLE_6 = 2, // 6 cycle
113 MI_CTRDG_RAMCYCLE_18 = 3 // 18 cycle
114 }
115 MICartridgeRamCycle;
116
117 //---- Wireless System (Wait State 0) control 1st wait (for ARM7)
118 typedef enum
119 {
120 MI_WMWAIT0_1_9 = 0, // 9 wait
121 MI_WMWAIT0_1_7 = 1, // 7 wait
122 MI_WMWAIT0_1_5 = 2, // 5 wait
123 MI_WMWAIT0_1_17 = 3 // 17 wait
124 }
125 MIWMWait0_1;
126
127 //---- Wireless System (Wait State 0) control 2nd wait (for ARM7)
128 typedef enum
129 {
130 MI_WMWAIT0_2_5 = 0, // 5 wait
131 MI_WMWAIT0_2_3 = 1 // 3 wait
132 }
133 MIWMWait0_2;
134
135 //---- Wireless System (Wait State 1) control 1st wait (for ARM7)
136 typedef enum
137 {
138 MI_WMWAIT1_1_9 = 0, // 9 wait
139 MI_WMWAIT1_1_7 = 1, // 7 wait
140 MI_WMWAIT1_1_5 = 2, // 5 wait
141 MI_WMWAIT1_1_17 = 3 // 17 wait
142 }
143 MIWMWait1_1;
144
145 //---- Wireless System (Wait State 1) control 2nd wait (for ARM7)
146 typedef enum
147 {
148 MI_WMWAIT1_2_9 = 0, // 9 wait
149 MI_WMWAIT1_2_3 = 1 // 3 wait
150 }
151 MIWMWait1_2;
152
153 //---- PHI Control (for ARM7)
154 typedef enum
155 {
156 MI_PHI_CLOCK_CARTRIDGE = 0, // conform to cartridge setting
157 MI_PHI_CLOCK_33MHZ = 1 // 33.51 MHz output from PHI (default)
158 }
159 MIPhiControl;
160
161
162 //----------------------------------------------------------------
163 // assert definition
164 //
165 #define MI_PROCESSOR_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_PROCESSOR_ARM7 )
166 #define MI_PHICLOCK_ASSERT( x ) SDK_ASSERT( (u32)x <= MIi_PHI_CLOCK_16MHZ )
167
168
169 #define MI_ROMCYCLE1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_ROMCYCLE1_18 )
170 #define MI_ROMCYCLE2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_ROMCYCLE2_4 )
171 #define MI_RAMCYCLE_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_CTRDG_RAMCYCLE_18 )
172
173
174 #define MI_WMWAIT0_1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT0_1_17 )
175 #define MI_WMWAIT0_2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT0_2_3 )
176 #define MI_WMWAIT1_1_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT1_1_17 )
177 #define MI_WMWAIT1_2_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_WMWAIT1_2_3 )
178
179 #define MI_PHICONTROL_ASSERT( x ) SDK_ASSERT( (u32)x <= MI_PHI_CLOCK_33MHZ )
180
181 //================================================================
182 // priority setting
183 //================================================================
184 //----------------
185 // set/get of access priority : main memory
186 #ifdef SDK_ARM9
MI_SetMainMemoryPriority(MIProcessor proc)187 static inline void MI_SetMainMemoryPriority(MIProcessor proc)
188 {
189 MI_PROCESSOR_ASSERT(proc);
190 reg_MI_EXMEMCNT =
191 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_EP_MASK) | (proc << REG_MI_EXMEMCNT_EP_SHIFT));
192 }
193 #endif
194
MI_GetMainMemoryPriority(void)195 static inline MIProcessor MI_GetMainMemoryPriority(void)
196 {
197 return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_EP_MASK) >> REG_MI_EXMEMCNT_EP_SHIFT);
198 }
199
200 //----------------
201 // set/get of access priority : NITRO card
202 #ifdef SDK_ARM9
MIi_SetCardProcessor(MIProcessor proc)203 static inline void MIi_SetCardProcessor(MIProcessor proc)
204 {
205 MI_PROCESSOR_ASSERT(proc);
206 reg_MI_EXMEMCNT =
207 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_MASK) | (proc << REG_MI_EXMEMCNT_MP_SHIFT));
208 }
209 #endif
210
MI_GetCardProcessor(void)211 static inline MIProcessor MI_GetCardProcessor(void)
212 {
213 return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_MP_MASK) >> REG_MI_EXMEMCNT_MP_SHIFT);
214 }
215
216 //----------------
217 // set/get of access priority : Cartridge
218 #ifdef SDK_ARM9
MIi_SetCartridgeProcessor(MIProcessor proc)219 static inline void MIi_SetCartridgeProcessor(MIProcessor proc)
220 {
221 MI_PROCESSOR_ASSERT(proc);
222 reg_MI_EXMEMCNT =
223 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_CP_MASK) | (proc << REG_MI_EXMEMCNT_CP_SHIFT));
224 }
225 #endif
226
MI_GetCartridgeProcessor(void)227 static inline MIProcessor MI_GetCartridgeProcessor(void)
228 {
229 return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_CP_MASK) >> REG_MI_EXMEMCNT_CP_SHIFT);
230 }
231
232 //================================================================
233 // speed and control setting
234 //================================================================
235 /*---------------------------------------------------------------------------*
236 Name: MIi_SetPhiClock
237
238 Description: set PHI output clock
239
240 Arguments: clock : Phi clock to set
241
242 Returns: None
243 *---------------------------------------------------------------------------*/
MIi_SetPhiClock(MIiPhiClock clock)244 static inline void MIi_SetPhiClock(MIiPhiClock clock)
245 {
246 MI_PHICLOCK_ASSERT(clock);
247 reg_MI_EXMEMCNT =
248 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_PHI_MASK) | (clock << REG_MI_EXMEMCNT_PHI_SHIFT));
249 }
250
251 /*---------------------------------------------------------------------------*
252 Name: MIi_GetPhiClock
253
254 Description: get PHI output clock
255
256 Arguments: None
257
258 Returns: Phi clock
259 *---------------------------------------------------------------------------*/
MIi_GetPhiClock(void)260 static inline MIiPhiClock MIi_GetPhiClock(void)
261 {
262 return (MIiPhiClock) ((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_PHI_MASK) >>
263 REG_MI_EXMEMCNT_PHI_SHIFT);
264 }
265
266 /*---------------------------------------------------------------------------*
267 Name: MI_SetCartridgeRomCycle1st
268
269 Description: set Cartridge ROM 1st access cycle
270
271 Arguments: c1 : access cycle to set
272
273 Returns: None
274 *---------------------------------------------------------------------------*/
MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1)275 static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1)
276 {
277 MI_ROMCYCLE1_ASSERT(c1);
278 reg_MI_EXMEMCNT =
279 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM1st_MASK) |
280 (c1 << REG_MI_EXMEMCNT_ROM1st_SHIFT));
281 }
282
283 /*---------------------------------------------------------------------------*
284 Name: MI_GetCartridgeRomCycle1st
285
286 Description: get Cartridge ROM 1st access cycle
287
288 Arguments: None
289
290 Returns: cartridge ROM 1st access cycle
291 *---------------------------------------------------------------------------*/
MI_GetCartridgeRomCycle1st(void)292 static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void)
293 {
294 return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM1st_MASK) >>
295 REG_MI_EXMEMCNT_ROM1st_SHIFT);
296 }
297
298 /*---------------------------------------------------------------------------*
299 Name: MI_SetCartridgeRomCycle2nd
300
301 Description: set Cartridge ROM 2nd access cycle
302
303 Arguments: c2 : access cycle to set
304
305 Returns: None
306 *---------------------------------------------------------------------------*/
MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2)307 static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2)
308 {
309 MI_ROMCYCLE2_ASSERT(c2);
310 reg_MI_EXMEMCNT =
311 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM2nd_MASK) |
312 (c2 << REG_MI_EXMEMCNT_ROM2nd_SHIFT));
313 }
314
315 /*---------------------------------------------------------------------------*
316 Name: MI_GetCartridgeRomCycle2nd
317
318 Description: get Cartridge ROM 2nd access cycle
319
320 Arguments: None
321
322 Returns: cartridge ROM 2nd access cycle
323 *---------------------------------------------------------------------------*/
MI_GetCartridgeRomCycle2nd(void)324 static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void)
325 {
326 return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM2nd_MASK) >>
327 REG_MI_EXMEMCNT_ROM2nd_SHIFT);
328 }
329
330 /*---------------------------------------------------------------------------*
331 Name: MI_SetAgbCartridgeFastestRomCycle
332
333 Description: set Cartridge ROM access cycles for AGB. (8-4 cycle)
334
335 Arguments: prev1st : pointer to be store the previous 1st ROM access cycle.
336 if NULL, no effect.
337 prev2nd : pointer to be store the previous 2nd ROM access cycle.
338 if NULL, no effect.
339
340 Returns: None
341 *---------------------------------------------------------------------------*/
342 void MI_SetAgbCartridgeFastestRomCycle(MICartridgeRomCycle1st *prev1st,
343 MICartridgeRomCycle2nd *prev2nd);
344
345 /*---------------------------------------------------------------------------*
346 Name: MI_SetCartridgeRamCycle
347
348 Description: set Cartridge RAM access cycle
349
350 Arguments: c : access cycle to set
351
352 Returns: None
353 *---------------------------------------------------------------------------*/
MI_SetCartridgeRamCycle(MICartridgeRamCycle c)354 static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c)
355 {
356 MI_RAMCYCLE_ASSERT(c);
357 reg_MI_EXMEMCNT =
358 (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_RAM_MASK) | (c << REG_MI_EXMEMCNT_RAM_SHIFT));
359 }
360
361 /*---------------------------------------------------------------------------*
362 Name: MI_GetCartridgeRamCycle
363
364 Description: get Cartridge RAM access cycle
365
366 Arguments: None
367
368 Returns: cartridge RAM access cycle
369 *---------------------------------------------------------------------------*/
MI_GetCartridgeRamCycle(void)370 static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void)
371 {
372 return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_RAM_MASK) >>
373 REG_MI_EXMEMCNT_RAM_SHIFT);
374 }
375
376
377 //================================================================
378 // speed and control setting (for ARM7)
379 //================================================================
380 #ifdef SDK_ARM7
381 /*---------------------------------------------------------------------------*
382 Name: MI_SetWM0Wait1st
383
384 Description: set 1st wait to Wireless system area at wait state 0
385 (this function is for ARM7)
386
387 Arguments: wait : 1st wait to set
388
389 Returns: None
390 *---------------------------------------------------------------------------*/
MI_SetWM0Wait1st(MIWMWait0_1 wait)391 static inline void MI_SetWM0Wait1st(MIWMWait0_1 wait)
392 {
393 MI_WMWAIT0_1_ASSERT(wait);
394 reg_MI_EXMEMCNT_H =
395 (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_1st_MASK) |
396 (wait << REG_MI_EXMEMCNT_H_WW0_1st_SHIFT));
397 }
398
399 /*---------------------------------------------------------------------------*
400 Name: MI_GetWM0Wait1st
401
402 Description: get 1st wait to Wireless system area at wait state 0
403 (this function is for ARM7)
404
405 Arguments: None
406
407 Returns: 1st wait to wireless system area at wait state 0
408 *---------------------------------------------------------------------------*/
MI_GetWM0Wait1st(void)409 static inline MIWMWait0_1 MI_GetWM0Wait1st(void)
410 {
411 return (MIWMWait0_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_1st_MASK) >>
412 REG_MI_EXMEMCNT_H_WW0_1st_SHIFT);
413 }
414
415 /*---------------------------------------------------------------------------*
416 Name: MI_SetWM0Wait2nd
417
418 Description: set 2nd wait to Wireless system area at wait state 0
419 (this function is for ARM7)
420
421 Arguments: wait : 2nd wait to set
422
423 Returns: None
424 *---------------------------------------------------------------------------*/
MI_SetWM0Wait2nd(MIWMWait0_2 wait)425 static inline void MI_SetWM0Wait2nd(MIWMWait0_2 wait)
426 {
427 MI_WMWAIT0_2_ASSERT(wait);
428 reg_MI_EXMEMCNT_H =
429 (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_2nd_MASK) |
430 (wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT));
431 }
432
433 /*---------------------------------------------------------------------------*
434 Name: MI_GetWM0Wait2nd
435
436 Description: get 2nd wait to Wireless system area at wait state 0
437 (this function is for ARM7)
438
439 Arguments: None
440
441 Returns: 2nd wait to wireless system area at wait state 0
442 *---------------------------------------------------------------------------*/
MI_GetWM0Wait2nd(void)443 static inline MIWMWait0_2 MI_GetWM0Wait2nd(void)
444 {
445 return (MIWMWait0_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_2nd_MASK) >>
446 REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT);
447 }
448
449 /*---------------------------------------------------------------------------*
450 Name: MI_SetWM1Wait1st
451
452 Description: set 1st wait to Wireless system area at wait state 1
453 (this function is for ARM7)
454
455 Arguments: wait : 1st wait to set
456
457 Returns: None
458 *---------------------------------------------------------------------------*/
MI_SetWM1Wait1st(MIWMWait1_1 wait)459 static inline void MI_SetWM1Wait1st(MIWMWait1_1 wait)
460 {
461 MI_WMWAIT1_1_ASSERT(wait);
462 reg_MI_EXMEMCNT_H =
463 (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_1st_MASK) |
464 (wait << REG_MI_EXMEMCNT_H_WW1_1st_SHIFT));
465 }
466
467 /*---------------------------------------------------------------------------*
468 Name: MI_GetWM1Wait1st
469
470 Description: get 1st wait to Wireless system area at wait state 1
471 (this function is for ARM7)
472
473 Arguments: None
474
475 Returns: 1st wait to wireless system area at wait state 1
476 *---------------------------------------------------------------------------*/
MI_GetWM1Wait1st(void)477 static inline MIWMWait1_1 MI_GetWM1Wait1st(void)
478 {
479 return (MIWMWait1_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_1st_MASK) >>
480 REG_MI_EXMEMCNT_H_WW1_1st_SHIFT);
481 }
482
483 /*---------------------------------------------------------------------------*
484 Name: MI_SetWM1Wait2nd
485
486 Description: set 2nd wait to Wireless system area at wait state 1
487 (this function is for ARM7)
488
489 Arguments: wait : 2nd wait to set
490
491 Returns: None
492 *---------------------------------------------------------------------------*/
MI_SetWM1Wait2nd(MIWMWait1_2 wait)493 static inline void MI_SetWM1Wait2nd(MIWMWait1_2 wait)
494 {
495 MI_WMWAIT1_2_ASSERT(wait);
496 reg_MI_EXMEMCNT_H =
497 (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_2nd_MASK) |
498 (wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT));
499 }
500
501 /*---------------------------------------------------------------------------*
502 Name: MI_GetWM1Wait2nd
503
504 Description: get 2nd wait to Wireless system area at wait state 1
505 (this function is for ARM7)
506
507 Arguments: None
508
509 Returns: 2nd wait to wireless system area at wait state 1
510 *---------------------------------------------------------------------------*/
MI_GetWM1Wait2nd(void)511 static inline MIWMWait1_2 MI_GetWM1Wait2nd(void)
512 {
513 return (MIWMWait1_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_2nd_MASK) >>
514 REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT);
515 }
516
517 /*---------------------------------------------------------------------------*
518 Name: MI_SetPhiControl
519
520 Description: set PHI control
521 (this function is for ARM7)
522
523 Arguments: control : PHI setting
524
525 Returns: None
526 *---------------------------------------------------------------------------*/
MI_SetPhiControl(MIPhiControl control)527 static inline void MI_SetPhiControl(MIPhiControl control)
528 {
529 MI_PHICONTROL_ASSERT(control);
530 reg_MI_EXMEMCNT_H =
531 (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_PHI33M_MASK) |
532 (control << REG_MI_EXMEMCNT_H_PHI33M_SHIFT));
533 }
534
535 /*---------------------------------------------------------------------------*
536 Name: MI_GetPhiControl
537
538 Description: get PHI control
539 (this function is for ARM7)
540
541 Arguments: None
542
543 Returns: PHI control setting
544 *---------------------------------------------------------------------------*/
MI_GetPhiControl(void)545 static inline MIPhiControl MI_GetPhiControl(void)
546 {
547 return (MIPhiControl)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_PHI33M_MASK) >>
548 REG_MI_EXMEMCNT_H_PHI33M_SHIFT);
549 }
550
551 #endif // ifdef SDK_ARM7
552
553
554
555 #ifdef __cplusplus
556 } /* extern "C" */
557 #endif
558
559 /* NITRO_MI_EXMEMORY_H_ */
560 #endif
561