1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_OS.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_OS_H_ 18 #define NITRO_HW_ARM9_IOREG_OS_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* TM0CNT_L */ 35 36 #define REG_TM0CNT_L_OFFSET 0x100 37 #define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) 38 #define reg_OS_TM0CNT_L (*( REGType16v *) REG_TM0CNT_L_ADDR) 39 40 /* TM0CNT_H */ 41 42 #define REG_TM0CNT_H_OFFSET 0x102 43 #define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) 44 #define reg_OS_TM0CNT_H (*( REGType16v *) REG_TM0CNT_H_ADDR) 45 46 /* TM1CNT_L */ 47 48 #define REG_TM1CNT_L_OFFSET 0x104 49 #define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) 50 #define reg_OS_TM1CNT_L (*( REGType16v *) REG_TM1CNT_L_ADDR) 51 52 /* TM1CNT_H */ 53 54 #define REG_TM1CNT_H_OFFSET 0x106 55 #define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) 56 #define reg_OS_TM1CNT_H (*( REGType16v *) REG_TM1CNT_H_ADDR) 57 58 /* TM2CNT_L */ 59 60 #define REG_TM2CNT_L_OFFSET 0x108 61 #define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) 62 #define reg_OS_TM2CNT_L (*( REGType16v *) REG_TM2CNT_L_ADDR) 63 64 /* TM2CNT_H */ 65 66 #define REG_TM2CNT_H_OFFSET 0x10a 67 #define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) 68 #define reg_OS_TM2CNT_H (*( REGType16v *) REG_TM2CNT_H_ADDR) 69 70 /* TM3CNT_L */ 71 72 #define REG_TM3CNT_L_OFFSET 0x10c 73 #define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) 74 #define reg_OS_TM3CNT_L (*( REGType16v *) REG_TM3CNT_L_ADDR) 75 76 /* TM3CNT_H */ 77 78 #define REG_TM3CNT_H_OFFSET 0x10e 79 #define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) 80 #define reg_OS_TM3CNT_H (*( REGType16v *) REG_TM3CNT_H_ADDR) 81 82 /* IME */ 83 84 #define REG_IME_OFFSET 0x208 85 #define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) 86 #define reg_OS_IME (*( REGType16v *) REG_IME_ADDR) 87 88 /* IE */ 89 90 #define REG_IE_OFFSET 0x210 91 #define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) 92 #define reg_OS_IE (*( REGType32v *) REG_IE_ADDR) 93 94 /* IF */ 95 96 #define REG_IF_OFFSET 0x214 97 #define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) 98 #define reg_OS_IF (*( REGType32v *) REG_IF_ADDR) 99 100 /* PAUSE */ 101 102 #define REG_PAUSE_OFFSET 0x300 103 #define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET) 104 #define reg_OS_PAUSE (*( REGType16v *) REG_PAUSE_ADDR) 105 106 107 /* 108 * Definitions of Register fields 109 */ 110 111 112 /* TM0CNT_L */ 113 114 #define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 115 #define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 116 #define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff 117 118 #ifndef SDK_ASM 119 #define REG_OS_TM0CNT_L_FIELD( timer0cnt ) \ 120 (u16)( \ 121 ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) 122 #endif 123 124 125 /* TM0CNT_H */ 126 127 #define REG_OS_TM0CNT_H_E_SHIFT 7 128 #define REG_OS_TM0CNT_H_E_SIZE 1 129 #define REG_OS_TM0CNT_H_E_MASK 0x0080 130 131 #define REG_OS_TM0CNT_H_I_SHIFT 6 132 #define REG_OS_TM0CNT_H_I_SIZE 1 133 #define REG_OS_TM0CNT_H_I_MASK 0x0040 134 135 #define REG_OS_TM0CNT_H_PS_SHIFT 0 136 #define REG_OS_TM0CNT_H_PS_SIZE 2 137 #define REG_OS_TM0CNT_H_PS_MASK 0x0003 138 139 #ifndef SDK_ASM 140 #define REG_OS_TM0CNT_H_FIELD( e, i, ps ) \ 141 (u16)( \ 142 ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \ 143 ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \ 144 ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT)) 145 #endif 146 147 148 /* TM1CNT_L */ 149 150 #define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0 151 #define REG_OS_TM1CNT_L_TIMER1CNT_SIZE 16 152 #define REG_OS_TM1CNT_L_TIMER1CNT_MASK 0xffff 153 154 #ifndef SDK_ASM 155 #define REG_OS_TM1CNT_L_FIELD( timer1cnt ) \ 156 (u16)( \ 157 ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) 158 #endif 159 160 161 /* TM1CNT_H */ 162 163 #define REG_OS_TM1CNT_H_E_SHIFT 7 164 #define REG_OS_TM1CNT_H_E_SIZE 1 165 #define REG_OS_TM1CNT_H_E_MASK 0x0080 166 167 #define REG_OS_TM1CNT_H_I_SHIFT 6 168 #define REG_OS_TM1CNT_H_I_SIZE 1 169 #define REG_OS_TM1CNT_H_I_MASK 0x0040 170 171 #define REG_OS_TM1CNT_H_CH_SHIFT 2 172 #define REG_OS_TM1CNT_H_CH_SIZE 1 173 #define REG_OS_TM1CNT_H_CH_MASK 0x0004 174 175 #define REG_OS_TM1CNT_H_PS_SHIFT 0 176 #define REG_OS_TM1CNT_H_PS_SIZE 2 177 #define REG_OS_TM1CNT_H_PS_MASK 0x0003 178 179 #ifndef SDK_ASM 180 #define REG_OS_TM1CNT_H_FIELD( e, i, ch, ps ) \ 181 (u16)( \ 182 ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \ 183 ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \ 184 ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \ 185 ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT)) 186 #endif 187 188 189 /* TM2CNT_L */ 190 191 #define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0 192 #define REG_OS_TM2CNT_L_TIMER2CNT_SIZE 16 193 #define REG_OS_TM2CNT_L_TIMER2CNT_MASK 0xffff 194 195 #ifndef SDK_ASM 196 #define REG_OS_TM2CNT_L_FIELD( timer2cnt ) \ 197 (u16)( \ 198 ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) 199 #endif 200 201 202 /* TM2CNT_H */ 203 204 #define REG_OS_TM2CNT_H_E_SHIFT 7 205 #define REG_OS_TM2CNT_H_E_SIZE 1 206 #define REG_OS_TM2CNT_H_E_MASK 0x0080 207 208 #define REG_OS_TM2CNT_H_I_SHIFT 6 209 #define REG_OS_TM2CNT_H_I_SIZE 1 210 #define REG_OS_TM2CNT_H_I_MASK 0x0040 211 212 #define REG_OS_TM2CNT_H_CH_SHIFT 2 213 #define REG_OS_TM2CNT_H_CH_SIZE 1 214 #define REG_OS_TM2CNT_H_CH_MASK 0x0004 215 216 #define REG_OS_TM2CNT_H_PS_SHIFT 0 217 #define REG_OS_TM2CNT_H_PS_SIZE 2 218 #define REG_OS_TM2CNT_H_PS_MASK 0x0003 219 220 #ifndef SDK_ASM 221 #define REG_OS_TM2CNT_H_FIELD( e, i, ch, ps ) \ 222 (u16)( \ 223 ((u32)(e) << REG_OS_TM2CNT_H_E_SHIFT) | \ 224 ((u32)(i) << REG_OS_TM2CNT_H_I_SHIFT) | \ 225 ((u32)(ch) << REG_OS_TM2CNT_H_CH_SHIFT) | \ 226 ((u32)(ps) << REG_OS_TM2CNT_H_PS_SHIFT)) 227 #endif 228 229 230 /* TM3CNT_L */ 231 232 #define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0 233 #define REG_OS_TM3CNT_L_TIMER2CNT_SIZE 16 234 #define REG_OS_TM3CNT_L_TIMER2CNT_MASK 0xffff 235 236 #ifndef SDK_ASM 237 #define REG_OS_TM3CNT_L_FIELD( timer2cnt ) \ 238 (u16)( \ 239 ((u32)(timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) 240 #endif 241 242 243 /* TM3CNT_H */ 244 245 #define REG_OS_TM3CNT_H_E_SHIFT 7 246 #define REG_OS_TM3CNT_H_E_SIZE 1 247 #define REG_OS_TM3CNT_H_E_MASK 0x0080 248 249 #define REG_OS_TM3CNT_H_I_SHIFT 6 250 #define REG_OS_TM3CNT_H_I_SIZE 1 251 #define REG_OS_TM3CNT_H_I_MASK 0x0040 252 253 #define REG_OS_TM3CNT_H_CH_SHIFT 2 254 #define REG_OS_TM3CNT_H_CH_SIZE 1 255 #define REG_OS_TM3CNT_H_CH_MASK 0x0004 256 257 #define REG_OS_TM3CNT_H_PS_SHIFT 0 258 #define REG_OS_TM3CNT_H_PS_SIZE 2 259 #define REG_OS_TM3CNT_H_PS_MASK 0x0003 260 261 #ifndef SDK_ASM 262 #define REG_OS_TM3CNT_H_FIELD( e, i, ch, ps ) \ 263 (u16)( \ 264 ((u32)(e) << REG_OS_TM3CNT_H_E_SHIFT) | \ 265 ((u32)(i) << REG_OS_TM3CNT_H_I_SHIFT) | \ 266 ((u32)(ch) << REG_OS_TM3CNT_H_CH_SHIFT) | \ 267 ((u32)(ps) << REG_OS_TM3CNT_H_PS_SHIFT)) 268 #endif 269 270 271 /* IME */ 272 273 #define REG_OS_IME_IME_SHIFT 0 274 #define REG_OS_IME_IME_SIZE 1 275 #define REG_OS_IME_IME_MASK 0x0001 276 277 #ifndef SDK_ASM 278 #define REG_OS_IME_FIELD( ime ) \ 279 (u16)( \ 280 ((u32)(ime) << REG_OS_IME_IME_SHIFT)) 281 #endif 282 283 284 /* IE */ 285 286 #define REG_OS_IE_GF_SHIFT 21 287 #define REG_OS_IE_GF_SIZE 1 288 #define REG_OS_IE_GF_MASK 0x00200000 289 290 #define REG_OS_IE_MI_SHIFT 20 291 #define REG_OS_IE_MI_SIZE 1 292 #define REG_OS_IE_MI_MASK 0x00100000 293 294 #define REG_OS_IE_MC_SHIFT 19 295 #define REG_OS_IE_MC_SIZE 1 296 #define REG_OS_IE_MC_MASK 0x00080000 297 298 #define REG_OS_IE_IFN_SHIFT 18 299 #define REG_OS_IE_IFN_SIZE 1 300 #define REG_OS_IE_IFN_MASK 0x00040000 301 302 #define REG_OS_IE_IFE_SHIFT 17 303 #define REG_OS_IE_IFE_SIZE 1 304 #define REG_OS_IE_IFE_MASK 0x00020000 305 306 #define REG_OS_IE_A7_SHIFT 16 307 #define REG_OS_IE_A7_SIZE 1 308 #define REG_OS_IE_A7_MASK 0x00010000 309 310 #define REG_OS_IE_I_D_SHIFT 13 311 #define REG_OS_IE_I_D_SIZE 1 312 #define REG_OS_IE_I_D_MASK 0x00002000 313 314 #define REG_OS_IE_K_SHIFT 12 315 #define REG_OS_IE_K_SIZE 1 316 #define REG_OS_IE_K_MASK 0x00001000 317 318 #define REG_OS_IE_D3_SHIFT 11 319 #define REG_OS_IE_D3_SIZE 1 320 #define REG_OS_IE_D3_MASK 0x00000800 321 322 #define REG_OS_IE_D2_SHIFT 10 323 #define REG_OS_IE_D2_SIZE 1 324 #define REG_OS_IE_D2_MASK 0x00000400 325 326 #define REG_OS_IE_D1_SHIFT 9 327 #define REG_OS_IE_D1_SIZE 1 328 #define REG_OS_IE_D1_MASK 0x00000200 329 330 #define REG_OS_IE_D0_SHIFT 8 331 #define REG_OS_IE_D0_SIZE 1 332 #define REG_OS_IE_D0_MASK 0x00000100 333 334 #define REG_OS_IE_T3_SHIFT 6 335 #define REG_OS_IE_T3_SIZE 1 336 #define REG_OS_IE_T3_MASK 0x00000040 337 338 #define REG_OS_IE_T2_SHIFT 5 339 #define REG_OS_IE_T2_SIZE 1 340 #define REG_OS_IE_T2_MASK 0x00000020 341 342 #define REG_OS_IE_T1_SHIFT 4 343 #define REG_OS_IE_T1_SIZE 1 344 #define REG_OS_IE_T1_MASK 0x00000010 345 346 #define REG_OS_IE_T0_SHIFT 3 347 #define REG_OS_IE_T0_SIZE 1 348 #define REG_OS_IE_T0_MASK 0x00000008 349 350 #define REG_OS_IE_VE_SHIFT 2 351 #define REG_OS_IE_VE_SIZE 1 352 #define REG_OS_IE_VE_MASK 0x00000004 353 354 #define REG_OS_IE_HB_SHIFT 1 355 #define REG_OS_IE_HB_SIZE 1 356 #define REG_OS_IE_HB_MASK 0x00000002 357 358 #define REG_OS_IE_VB_SHIFT 0 359 #define REG_OS_IE_VB_SIZE 1 360 #define REG_OS_IE_VB_MASK 0x00000001 361 362 #ifndef SDK_ASM 363 #define REG_OS_IE_FIELD( gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ 364 (u32)( \ 365 ((u32)(gf) << REG_OS_IE_GF_SHIFT) | \ 366 ((u32)(mi) << REG_OS_IE_MI_SHIFT) | \ 367 ((u32)(mc) << REG_OS_IE_MC_SHIFT) | \ 368 ((u32)(ifn) << REG_OS_IE_IFN_SHIFT) | \ 369 ((u32)(ife) << REG_OS_IE_IFE_SHIFT) | \ 370 ((u32)(a7) << REG_OS_IE_A7_SHIFT) | \ 371 ((u32)(i_d) << REG_OS_IE_I_D_SHIFT) | \ 372 ((u32)(k) << REG_OS_IE_K_SHIFT) | \ 373 ((u32)(d3) << REG_OS_IE_D3_SHIFT) | \ 374 ((u32)(d2) << REG_OS_IE_D2_SHIFT) | \ 375 ((u32)(d1) << REG_OS_IE_D1_SHIFT) | \ 376 ((u32)(d0) << REG_OS_IE_D0_SHIFT) | \ 377 ((u32)(t3) << REG_OS_IE_T3_SHIFT) | \ 378 ((u32)(t2) << REG_OS_IE_T2_SHIFT) | \ 379 ((u32)(t1) << REG_OS_IE_T1_SHIFT) | \ 380 ((u32)(t0) << REG_OS_IE_T0_SHIFT) | \ 381 ((u32)(ve) << REG_OS_IE_VE_SHIFT) | \ 382 ((u32)(hb) << REG_OS_IE_HB_SHIFT) | \ 383 ((u32)(vb) << REG_OS_IE_VB_SHIFT)) 384 #endif 385 386 387 /* IF */ 388 389 #define REG_OS_IF_GF_SHIFT 21 390 #define REG_OS_IF_GF_SIZE 1 391 #define REG_OS_IF_GF_MASK 0x00200000 392 393 #define REG_OS_IF_MI_SHIFT 20 394 #define REG_OS_IF_MI_SIZE 1 395 #define REG_OS_IF_MI_MASK 0x00100000 396 397 #define REG_OS_IF_MC_SHIFT 19 398 #define REG_OS_IF_MC_SIZE 1 399 #define REG_OS_IF_MC_MASK 0x00080000 400 401 #define REG_OS_IF_IFN_SHIFT 18 402 #define REG_OS_IF_IFN_SIZE 1 403 #define REG_OS_IF_IFN_MASK 0x00040000 404 405 #define REG_OS_IF_IFE_SHIFT 17 406 #define REG_OS_IF_IFE_SIZE 1 407 #define REG_OS_IF_IFE_MASK 0x00020000 408 409 #define REG_OS_IF_A7_SHIFT 16 410 #define REG_OS_IF_A7_SIZE 1 411 #define REG_OS_IF_A7_MASK 0x00010000 412 413 #define REG_OS_IF_I_D_SHIFT 13 414 #define REG_OS_IF_I_D_SIZE 1 415 #define REG_OS_IF_I_D_MASK 0x00002000 416 417 #define REG_OS_IF_K_SHIFT 12 418 #define REG_OS_IF_K_SIZE 1 419 #define REG_OS_IF_K_MASK 0x00001000 420 421 #define REG_OS_IF_D3_SHIFT 11 422 #define REG_OS_IF_D3_SIZE 1 423 #define REG_OS_IF_D3_MASK 0x00000800 424 425 #define REG_OS_IF_D2_SHIFT 10 426 #define REG_OS_IF_D2_SIZE 1 427 #define REG_OS_IF_D2_MASK 0x00000400 428 429 #define REG_OS_IF_D1_SHIFT 9 430 #define REG_OS_IF_D1_SIZE 1 431 #define REG_OS_IF_D1_MASK 0x00000200 432 433 #define REG_OS_IF_D0_SHIFT 8 434 #define REG_OS_IF_D0_SIZE 1 435 #define REG_OS_IF_D0_MASK 0x00000100 436 437 #define REG_OS_IF_T3_SHIFT 6 438 #define REG_OS_IF_T3_SIZE 1 439 #define REG_OS_IF_T3_MASK 0x00000040 440 441 #define REG_OS_IF_T2_SHIFT 5 442 #define REG_OS_IF_T2_SIZE 1 443 #define REG_OS_IF_T2_MASK 0x00000020 444 445 #define REG_OS_IF_T1_SHIFT 4 446 #define REG_OS_IF_T1_SIZE 1 447 #define REG_OS_IF_T1_MASK 0x00000010 448 449 #define REG_OS_IF_T0_SHIFT 3 450 #define REG_OS_IF_T0_SIZE 1 451 #define REG_OS_IF_T0_MASK 0x00000008 452 453 #define REG_OS_IF_VE_SHIFT 2 454 #define REG_OS_IF_VE_SIZE 1 455 #define REG_OS_IF_VE_MASK 0x00000004 456 457 #define REG_OS_IF_HB_SHIFT 1 458 #define REG_OS_IF_HB_SIZE 1 459 #define REG_OS_IF_HB_MASK 0x00000002 460 461 #define REG_OS_IF_VB_SHIFT 0 462 #define REG_OS_IF_VB_SIZE 1 463 #define REG_OS_IF_VB_MASK 0x00000001 464 465 #ifndef SDK_ASM 466 #define REG_OS_IF_FIELD( gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ 467 (u32)( \ 468 ((u32)(gf) << REG_OS_IF_GF_SHIFT) | \ 469 ((u32)(mi) << REG_OS_IF_MI_SHIFT) | \ 470 ((u32)(mc) << REG_OS_IF_MC_SHIFT) | \ 471 ((u32)(ifn) << REG_OS_IF_IFN_SHIFT) | \ 472 ((u32)(ife) << REG_OS_IF_IFE_SHIFT) | \ 473 ((u32)(a7) << REG_OS_IF_A7_SHIFT) | \ 474 ((u32)(i_d) << REG_OS_IF_I_D_SHIFT) | \ 475 ((u32)(k) << REG_OS_IF_K_SHIFT) | \ 476 ((u32)(d3) << REG_OS_IF_D3_SHIFT) | \ 477 ((u32)(d2) << REG_OS_IF_D2_SHIFT) | \ 478 ((u32)(d1) << REG_OS_IF_D1_SHIFT) | \ 479 ((u32)(d0) << REG_OS_IF_D0_SHIFT) | \ 480 ((u32)(t3) << REG_OS_IF_T3_SHIFT) | \ 481 ((u32)(t2) << REG_OS_IF_T2_SHIFT) | \ 482 ((u32)(t1) << REG_OS_IF_T1_SHIFT) | \ 483 ((u32)(t0) << REG_OS_IF_T0_SHIFT) | \ 484 ((u32)(ve) << REG_OS_IF_VE_SHIFT) | \ 485 ((u32)(hb) << REG_OS_IF_HB_SHIFT) | \ 486 ((u32)(vb) << REG_OS_IF_VB_SHIFT)) 487 #endif 488 489 490 /* PAUSE */ 491 492 #define REG_OS_PAUSE_MOD_SHIFT 14 493 #define REG_OS_PAUSE_MOD_SIZE 2 494 #define REG_OS_PAUSE_MOD_MASK 0xc000 495 496 #define REG_OS_PAUSE_CHK_SHIFT 0 497 #define REG_OS_PAUSE_CHK_SIZE 1 498 #define REG_OS_PAUSE_CHK_MASK 0x0001 499 500 #ifndef SDK_ASM 501 #define REG_OS_PAUSE_FIELD( mod, chk ) \ 502 (u16)( \ 503 ((u32)(mod) << REG_OS_PAUSE_MOD_SHIFT) | \ 504 ((u32)(chk) << REG_OS_PAUSE_CHK_SHIFT)) 505 #endif 506 507 508 #ifdef __cplusplus 509 } /* extern "C" */ 510 #endif 511 512 /* NITRO_HW_ARM9_IOREG_OS_H_ */ 513 #endif 514