1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_MI.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_MI_H_ 18 #define NITRO_HW_ARM9_IOREG_MI_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DMA0SAD */ 35 36 #define REG_DMA0SAD_OFFSET 0x0b0 37 #define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) 38 #define reg_MI_DMA0SAD (*( REGType32v *) REG_DMA0SAD_ADDR) 39 40 /* DMA0DAD */ 41 42 #define REG_DMA0DAD_OFFSET 0x0b4 43 #define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) 44 #define reg_MI_DMA0DAD (*( REGType32v *) REG_DMA0DAD_ADDR) 45 46 /* DMA0CNT */ 47 48 #define REG_DMA0CNT_OFFSET 0x0b8 49 #define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) 50 #define reg_MI_DMA0CNT (*( REGType32v *) REG_DMA0CNT_ADDR) 51 52 /* DMA1SAD */ 53 54 #define REG_DMA1SAD_OFFSET 0x0bc 55 #define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET) 56 #define reg_MI_DMA1SAD (*( REGType32v *) REG_DMA1SAD_ADDR) 57 58 /* DMA1DAD */ 59 60 #define REG_DMA1DAD_OFFSET 0x0c0 61 #define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) 62 #define reg_MI_DMA1DAD (*( REGType32v *) REG_DMA1DAD_ADDR) 63 64 /* DMA1CNT */ 65 66 #define REG_DMA1CNT_OFFSET 0x0c4 67 #define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) 68 #define reg_MI_DMA1CNT (*( REGType32v *) REG_DMA1CNT_ADDR) 69 70 /* DMA2SAD */ 71 72 #define REG_DMA2SAD_OFFSET 0x0c8 73 #define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET) 74 #define reg_MI_DMA2SAD (*( REGType32v *) REG_DMA2SAD_ADDR) 75 76 /* DMA2DAD */ 77 78 #define REG_DMA2DAD_OFFSET 0x0cc 79 #define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) 80 #define reg_MI_DMA2DAD (*( REGType32v *) REG_DMA2DAD_ADDR) 81 82 /* DMA2CNT */ 83 84 #define REG_DMA2CNT_OFFSET 0x0d0 85 #define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) 86 #define reg_MI_DMA2CNT (*( REGType32v *) REG_DMA2CNT_ADDR) 87 88 /* DMA3SAD */ 89 90 #define REG_DMA3SAD_OFFSET 0x0d4 91 #define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET) 92 #define reg_MI_DMA3SAD (*( REGType32v *) REG_DMA3SAD_ADDR) 93 94 /* DMA3DAD */ 95 96 #define REG_DMA3DAD_OFFSET 0x0d8 97 #define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET) 98 #define reg_MI_DMA3DAD (*( REGType32v *) REG_DMA3DAD_ADDR) 99 100 /* DMA3CNT */ 101 102 #define REG_DMA3CNT_OFFSET 0x0dc 103 #define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) 104 #define reg_MI_DMA3CNT (*( REGType32v *) REG_DMA3CNT_ADDR) 105 106 /* DMA0_CLR_DATA */ 107 108 #define REG_DMA0_CLR_DATA_OFFSET 0x0e0 109 #define REG_DMA0_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA0_CLR_DATA_OFFSET) 110 #define reg_MI_DMA0_CLR_DATA (*( REGType32v *) REG_DMA0_CLR_DATA_ADDR) 111 112 /* DMA1_CLR_DATA */ 113 114 #define REG_DMA1_CLR_DATA_OFFSET 0x0e4 115 #define REG_DMA1_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA1_CLR_DATA_OFFSET) 116 #define reg_MI_DMA1_CLR_DATA (*( REGType32v *) REG_DMA1_CLR_DATA_ADDR) 117 118 /* DMA2_CLR_DATA */ 119 120 #define REG_DMA2_CLR_DATA_OFFSET 0x0e8 121 #define REG_DMA2_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA2_CLR_DATA_OFFSET) 122 #define reg_MI_DMA2_CLR_DATA (*( REGType32v *) REG_DMA2_CLR_DATA_ADDR) 123 124 /* DMA3_CLR_DATA */ 125 126 #define REG_DMA3_CLR_DATA_OFFSET 0x0ec 127 #define REG_DMA3_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA3_CLR_DATA_OFFSET) 128 #define reg_MI_DMA3_CLR_DATA (*( REGType32v *) REG_DMA3_CLR_DATA_ADDR) 129 130 /* MCCNT0 */ 131 132 #define REG_MCCNT0_OFFSET 0x1a0 133 #define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET) 134 #define reg_MI_MCCNT0 (*( REGType16v *) REG_MCCNT0_ADDR) 135 136 /* MCD0 */ 137 138 #define REG_MCD0_OFFSET 0x1a2 139 #define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET) 140 #define reg_MI_MCD0 (*( REGType16v *) REG_MCD0_ADDR) 141 142 /* MCD1 */ 143 144 #define REG_MCD1_OFFSET 0x100010 145 #define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET) 146 #define reg_MI_MCD1 (*( REGType32v *) REG_MCD1_ADDR) 147 148 /* MCCNT1 */ 149 150 #define REG_MCCNT1_OFFSET 0x1a4 151 #define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET) 152 #define reg_MI_MCCNT1 (*( REGType32v *) REG_MCCNT1_ADDR) 153 154 /* MCCMD0 */ 155 156 #define REG_MCCMD0_OFFSET 0x1a8 157 #define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET) 158 #define reg_MI_MCCMD0 (*( REGType32v *) REG_MCCMD0_ADDR) 159 160 /* MCCMD1 */ 161 162 #define REG_MCCMD1_OFFSET 0x1ac 163 #define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET) 164 #define reg_MI_MCCMD1 (*( REGType32v *) REG_MCCMD1_ADDR) 165 166 /* EXMEMCNT */ 167 168 #define REG_EXMEMCNT_OFFSET 0x204 169 #define REG_EXMEMCNT_ADDR (HW_REG_BASE + REG_EXMEMCNT_OFFSET) 170 #define reg_MI_EXMEMCNT (*( REGType16v *) REG_EXMEMCNT_ADDR) 171 172 173 /* 174 * Definitions of Register fields 175 */ 176 177 178 /* DMA0SAD */ 179 180 #define REG_MI_DMA0SAD_DMASRC_SHIFT 0 181 #define REG_MI_DMA0SAD_DMASRC_SIZE 28 182 #define REG_MI_DMA0SAD_DMASRC_MASK 0x0fffffff 183 184 #ifndef SDK_ASM 185 #define REG_MI_DMA0SAD_FIELD( dmasrc ) \ 186 (u32)( \ 187 ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) 188 #endif 189 190 191 /* DMA0DAD */ 192 193 #define REG_MI_DMA0DAD_DMADEST_SHIFT 0 194 #define REG_MI_DMA0DAD_DMADEST_SIZE 28 195 #define REG_MI_DMA0DAD_DMADEST_MASK 0x0fffffff 196 197 #ifndef SDK_ASM 198 #define REG_MI_DMA0DAD_FIELD( dmadest ) \ 199 (u32)( \ 200 ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) 201 #endif 202 203 204 /* DMA0CNT */ 205 206 #define REG_MI_DMA0CNT_E_SHIFT 31 207 #define REG_MI_DMA0CNT_E_SIZE 1 208 #define REG_MI_DMA0CNT_E_MASK 0x80000000 209 210 #define REG_MI_DMA0CNT_I_SHIFT 30 211 #define REG_MI_DMA0CNT_I_SIZE 1 212 #define REG_MI_DMA0CNT_I_MASK 0x40000000 213 214 #define REG_MI_DMA0CNT_MODE_SHIFT 27 215 #define REG_MI_DMA0CNT_MODE_SIZE 3 216 #define REG_MI_DMA0CNT_MODE_MASK 0x38000000 217 218 #define REG_MI_DMA0CNT_SB_SHIFT 26 219 #define REG_MI_DMA0CNT_SB_SIZE 1 220 #define REG_MI_DMA0CNT_SB_MASK 0x04000000 221 222 #define REG_MI_DMA0CNT_CM_SHIFT 25 223 #define REG_MI_DMA0CNT_CM_SIZE 1 224 #define REG_MI_DMA0CNT_CM_MASK 0x02000000 225 226 #define REG_MI_DMA0CNT_SAR_SHIFT 23 227 #define REG_MI_DMA0CNT_SAR_SIZE 2 228 #define REG_MI_DMA0CNT_SAR_MASK 0x01800000 229 230 #define REG_MI_DMA0CNT_DAR_SHIFT 21 231 #define REG_MI_DMA0CNT_DAR_SIZE 2 232 #define REG_MI_DMA0CNT_DAR_MASK 0x00600000 233 234 #define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 235 #define REG_MI_DMA0CNT_WORDCNT_SIZE 21 236 #define REG_MI_DMA0CNT_WORDCNT_MASK 0x001fffff 237 238 #ifndef SDK_ASM 239 #define REG_MI_DMA0CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 240 (u32)( \ 241 ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \ 242 ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \ 243 ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \ 244 ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \ 245 ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \ 246 ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \ 247 ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \ 248 ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) 249 #endif 250 251 252 /* DMA1SAD */ 253 254 #define REG_MI_DMA1SAD_DMASRC_SHIFT 0 255 #define REG_MI_DMA1SAD_DMASRC_SIZE 28 256 #define REG_MI_DMA1SAD_DMASRC_MASK 0x0fffffff 257 258 #ifndef SDK_ASM 259 #define REG_MI_DMA1SAD_FIELD( dmasrc ) \ 260 (u32)( \ 261 ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) 262 #endif 263 264 265 /* DMA1DAD */ 266 267 #define REG_MI_DMA1DAD_DMADEST_SHIFT 0 268 #define REG_MI_DMA1DAD_DMADEST_SIZE 28 269 #define REG_MI_DMA1DAD_DMADEST_MASK 0x0fffffff 270 271 #ifndef SDK_ASM 272 #define REG_MI_DMA1DAD_FIELD( dmadest ) \ 273 (u32)( \ 274 ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) 275 #endif 276 277 278 /* DMA1CNT */ 279 280 #define REG_MI_DMA1CNT_E_SHIFT 31 281 #define REG_MI_DMA1CNT_E_SIZE 1 282 #define REG_MI_DMA1CNT_E_MASK 0x80000000 283 284 #define REG_MI_DMA1CNT_I_SHIFT 30 285 #define REG_MI_DMA1CNT_I_SIZE 1 286 #define REG_MI_DMA1CNT_I_MASK 0x40000000 287 288 #define REG_MI_DMA1CNT_MODE_SHIFT 27 289 #define REG_MI_DMA1CNT_MODE_SIZE 3 290 #define REG_MI_DMA1CNT_MODE_MASK 0x38000000 291 292 #define REG_MI_DMA1CNT_SB_SHIFT 26 293 #define REG_MI_DMA1CNT_SB_SIZE 1 294 #define REG_MI_DMA1CNT_SB_MASK 0x04000000 295 296 #define REG_MI_DMA1CNT_CM_SHIFT 25 297 #define REG_MI_DMA1CNT_CM_SIZE 1 298 #define REG_MI_DMA1CNT_CM_MASK 0x02000000 299 300 #define REG_MI_DMA1CNT_SAR_SHIFT 23 301 #define REG_MI_DMA1CNT_SAR_SIZE 2 302 #define REG_MI_DMA1CNT_SAR_MASK 0x01800000 303 304 #define REG_MI_DMA1CNT_DAR_SHIFT 21 305 #define REG_MI_DMA1CNT_DAR_SIZE 2 306 #define REG_MI_DMA1CNT_DAR_MASK 0x00600000 307 308 #define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 309 #define REG_MI_DMA1CNT_WORDCNT_SIZE 21 310 #define REG_MI_DMA1CNT_WORDCNT_MASK 0x001fffff 311 312 #ifndef SDK_ASM 313 #define REG_MI_DMA1CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 314 (u32)( \ 315 ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \ 316 ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \ 317 ((u32)(mode) << REG_MI_DMA1CNT_MODE_SHIFT) | \ 318 ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \ 319 ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \ 320 ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \ 321 ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \ 322 ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) 323 #endif 324 325 326 /* DMA2SAD */ 327 328 #define REG_MI_DMA2SAD_DMASRC_SHIFT 0 329 #define REG_MI_DMA2SAD_DMASRC_SIZE 28 330 #define REG_MI_DMA2SAD_DMASRC_MASK 0x0fffffff 331 332 #ifndef SDK_ASM 333 #define REG_MI_DMA2SAD_FIELD( dmasrc ) \ 334 (u32)( \ 335 ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) 336 #endif 337 338 339 /* DMA2DAD */ 340 341 #define REG_MI_DMA2DAD_DMADEST_SHIFT 0 342 #define REG_MI_DMA2DAD_DMADEST_SIZE 28 343 #define REG_MI_DMA2DAD_DMADEST_MASK 0x0fffffff 344 345 #ifndef SDK_ASM 346 #define REG_MI_DMA2DAD_FIELD( dmadest ) \ 347 (u32)( \ 348 ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) 349 #endif 350 351 352 /* DMA2CNT */ 353 354 #define REG_MI_DMA2CNT_E_SHIFT 31 355 #define REG_MI_DMA2CNT_E_SIZE 1 356 #define REG_MI_DMA2CNT_E_MASK 0x80000000 357 358 #define REG_MI_DMA2CNT_I_SHIFT 30 359 #define REG_MI_DMA2CNT_I_SIZE 1 360 #define REG_MI_DMA2CNT_I_MASK 0x40000000 361 362 #define REG_MI_DMA2CNT_MODE_SHIFT 27 363 #define REG_MI_DMA2CNT_MODE_SIZE 3 364 #define REG_MI_DMA2CNT_MODE_MASK 0x38000000 365 366 #define REG_MI_DMA2CNT_SB_SHIFT 26 367 #define REG_MI_DMA2CNT_SB_SIZE 1 368 #define REG_MI_DMA2CNT_SB_MASK 0x04000000 369 370 #define REG_MI_DMA2CNT_CM_SHIFT 25 371 #define REG_MI_DMA2CNT_CM_SIZE 1 372 #define REG_MI_DMA2CNT_CM_MASK 0x02000000 373 374 #define REG_MI_DMA2CNT_SAR_SHIFT 23 375 #define REG_MI_DMA2CNT_SAR_SIZE 2 376 #define REG_MI_DMA2CNT_SAR_MASK 0x01800000 377 378 #define REG_MI_DMA2CNT_DAR_SHIFT 21 379 #define REG_MI_DMA2CNT_DAR_SIZE 2 380 #define REG_MI_DMA2CNT_DAR_MASK 0x00600000 381 382 #define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 383 #define REG_MI_DMA2CNT_WORDCNT_SIZE 21 384 #define REG_MI_DMA2CNT_WORDCNT_MASK 0x001fffff 385 386 #ifndef SDK_ASM 387 #define REG_MI_DMA2CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 388 (u32)( \ 389 ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \ 390 ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \ 391 ((u32)(mode) << REG_MI_DMA2CNT_MODE_SHIFT) | \ 392 ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \ 393 ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \ 394 ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \ 395 ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \ 396 ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) 397 #endif 398 399 400 /* DMA3SAD */ 401 402 #define REG_MI_DMA3SAD_DMASRC_SHIFT 0 403 #define REG_MI_DMA3SAD_DMASRC_SIZE 28 404 #define REG_MI_DMA3SAD_DMASRC_MASK 0x0fffffff 405 406 #ifndef SDK_ASM 407 #define REG_MI_DMA3SAD_FIELD( dmasrc ) \ 408 (u32)( \ 409 ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) 410 #endif 411 412 413 /* DMA3DAD */ 414 415 #define REG_MI_DMA3DAD_DMADEST_SHIFT 0 416 #define REG_MI_DMA3DAD_DMADEST_SIZE 28 417 #define REG_MI_DMA3DAD_DMADEST_MASK 0x0fffffff 418 419 #ifndef SDK_ASM 420 #define REG_MI_DMA3DAD_FIELD( dmadest ) \ 421 (u32)( \ 422 ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) 423 #endif 424 425 426 /* DMA3CNT */ 427 428 #define REG_MI_DMA3CNT_E_SHIFT 31 429 #define REG_MI_DMA3CNT_E_SIZE 1 430 #define REG_MI_DMA3CNT_E_MASK 0x80000000 431 432 #define REG_MI_DMA3CNT_I_SHIFT 30 433 #define REG_MI_DMA3CNT_I_SIZE 1 434 #define REG_MI_DMA3CNT_I_MASK 0x40000000 435 436 #define REG_MI_DMA3CNT_MODE_SHIFT 27 437 #define REG_MI_DMA3CNT_MODE_SIZE 3 438 #define REG_MI_DMA3CNT_MODE_MASK 0x38000000 439 440 #define REG_MI_DMA3CNT_SB_SHIFT 26 441 #define REG_MI_DMA3CNT_SB_SIZE 1 442 #define REG_MI_DMA3CNT_SB_MASK 0x04000000 443 444 #define REG_MI_DMA3CNT_CM_SHIFT 25 445 #define REG_MI_DMA3CNT_CM_SIZE 1 446 #define REG_MI_DMA3CNT_CM_MASK 0x02000000 447 448 #define REG_MI_DMA3CNT_SAR_SHIFT 23 449 #define REG_MI_DMA3CNT_SAR_SIZE 2 450 #define REG_MI_DMA3CNT_SAR_MASK 0x01800000 451 452 #define REG_MI_DMA3CNT_DAR_SHIFT 21 453 #define REG_MI_DMA3CNT_DAR_SIZE 2 454 #define REG_MI_DMA3CNT_DAR_MASK 0x00600000 455 456 #define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 457 #define REG_MI_DMA3CNT_WORDCNT_SIZE 21 458 #define REG_MI_DMA3CNT_WORDCNT_MASK 0x001fffff 459 460 #ifndef SDK_ASM 461 #define REG_MI_DMA3CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ 462 (u32)( \ 463 ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \ 464 ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \ 465 ((u32)(mode) << REG_MI_DMA3CNT_MODE_SHIFT) | \ 466 ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \ 467 ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \ 468 ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \ 469 ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \ 470 ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) 471 #endif 472 473 474 /* DMA0_CLR_DATA */ 475 476 /* DMA1_CLR_DATA */ 477 478 /* DMA2_CLR_DATA */ 479 480 /* DMA3_CLR_DATA */ 481 482 /* MCCNT0 */ 483 484 #define REG_MI_MCCNT0_E_SHIFT 15 485 #define REG_MI_MCCNT0_E_SIZE 1 486 #define REG_MI_MCCNT0_E_MASK 0x8000 487 488 #define REG_MI_MCCNT0_I_SHIFT 14 489 #define REG_MI_MCCNT0_I_SIZE 1 490 #define REG_MI_MCCNT0_I_MASK 0x4000 491 492 #define REG_MI_MCCNT0_SEL_SHIFT 13 493 #define REG_MI_MCCNT0_SEL_SIZE 1 494 #define REG_MI_MCCNT0_SEL_MASK 0x2000 495 496 #define REG_MI_MCCNT0_BUSY_SHIFT 7 497 #define REG_MI_MCCNT0_BUSY_SIZE 1 498 #define REG_MI_MCCNT0_BUSY_MASK 0x0080 499 500 #define REG_MI_MCCNT0_MODE_SHIFT 6 501 #define REG_MI_MCCNT0_MODE_SIZE 1 502 #define REG_MI_MCCNT0_MODE_MASK 0x0040 503 504 #define REG_MI_MCCNT0_BAUDRATE_SHIFT 0 505 #define REG_MI_MCCNT0_BAUDRATE_SIZE 2 506 #define REG_MI_MCCNT0_BAUDRATE_MASK 0x0003 507 508 #ifndef SDK_ASM 509 #define REG_MI_MCCNT0_FIELD( e, i, sel, busy, mode, baudrate ) \ 510 (u16)( \ 511 ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \ 512 ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \ 513 ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \ 514 ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \ 515 ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \ 516 ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) 517 #endif 518 519 520 /* MCD0 */ 521 522 #define REG_MI_MCD0_DATA_SHIFT 0 523 #define REG_MI_MCD0_DATA_SIZE 8 524 #define REG_MI_MCD0_DATA_MASK 0x00ff 525 526 #ifndef SDK_ASM 527 #define REG_MI_MCD0_FIELD( data ) \ 528 (u16)( \ 529 ((u32)(data) << REG_MI_MCD0_DATA_SHIFT)) 530 #endif 531 532 533 /* MCD1 */ 534 535 /* MCCNT1 */ 536 537 #define REG_MI_MCCNT1_START_SHIFT 31 538 #define REG_MI_MCCNT1_START_SIZE 1 539 #define REG_MI_MCCNT1_START_MASK 0x80000000 540 541 #define REG_MI_MCCNT1_WR_SHIFT 30 542 #define REG_MI_MCCNT1_WR_SIZE 1 543 #define REG_MI_MCCNT1_WR_MASK 0x40000000 544 545 #define REG_MI_MCCNT1_CT_SHIFT 27 546 #define REG_MI_MCCNT1_CT_SIZE 1 547 #define REG_MI_MCCNT1_CT_MASK 0x08000000 548 549 #define REG_MI_MCCNT1_PC_SHIFT 24 550 #define REG_MI_MCCNT1_PC_SIZE 3 551 #define REG_MI_MCCNT1_PC_MASK 0x07000000 552 553 #define REG_MI_MCCNT1_RDY_SHIFT 23 554 #define REG_MI_MCCNT1_RDY_SIZE 1 555 #define REG_MI_MCCNT1_RDY_MASK 0x00800000 556 557 #define REG_MI_MCCNT1_L2_SHIFT 16 558 #define REG_MI_MCCNT1_L2_SIZE 6 559 #define REG_MI_MCCNT1_L2_MASK 0x003f0000 560 561 #define REG_MI_MCCNT1_L1_SHIFT 0 562 #define REG_MI_MCCNT1_L1_SIZE 13 563 #define REG_MI_MCCNT1_L1_MASK 0x00001fff 564 565 #ifndef SDK_ASM 566 #define REG_MI_MCCNT1_FIELD( start, wr, ct, pc, rdy, l2, l1 ) \ 567 (u32)( \ 568 ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \ 569 ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \ 570 ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \ 571 ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \ 572 ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \ 573 ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \ 574 ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT)) 575 #endif 576 577 578 /* MCCMD0 */ 579 580 #define REG_MI_MCCMD0_CMD3_SHIFT 24 581 #define REG_MI_MCCMD0_CMD3_SIZE 8 582 #define REG_MI_MCCMD0_CMD3_MASK 0xff000000 583 584 #define REG_MI_MCCMD0_CMD2_SHIFT 16 585 #define REG_MI_MCCMD0_CMD2_SIZE 8 586 #define REG_MI_MCCMD0_CMD2_MASK 0x00ff0000 587 588 #define REG_MI_MCCMD0_CMD1_SHIFT 8 589 #define REG_MI_MCCMD0_CMD1_SIZE 8 590 #define REG_MI_MCCMD0_CMD1_MASK 0x0000ff00 591 592 #define REG_MI_MCCMD0_CMD0_SHIFT 0 593 #define REG_MI_MCCMD0_CMD0_SIZE 8 594 #define REG_MI_MCCMD0_CMD0_MASK 0x000000ff 595 596 #ifndef SDK_ASM 597 #define REG_MI_MCCMD0_FIELD( cmd3, cmd2, cmd1, cmd0 ) \ 598 (u32)( \ 599 ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \ 600 ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \ 601 ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \ 602 ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) 603 #endif 604 605 606 /* MCCMD1 */ 607 608 #define REG_MI_MCCMD1_CMD7_SHIFT 24 609 #define REG_MI_MCCMD1_CMD7_SIZE 8 610 #define REG_MI_MCCMD1_CMD7_MASK 0xff000000 611 612 #define REG_MI_MCCMD1_CMD6_SHIFT 16 613 #define REG_MI_MCCMD1_CMD6_SIZE 8 614 #define REG_MI_MCCMD1_CMD6_MASK 0x00ff0000 615 616 #define REG_MI_MCCMD1_CMD5_SHIFT 8 617 #define REG_MI_MCCMD1_CMD5_SIZE 8 618 #define REG_MI_MCCMD1_CMD5_MASK 0x0000ff00 619 620 #define REG_MI_MCCMD1_CMD4_SHIFT 0 621 #define REG_MI_MCCMD1_CMD4_SIZE 8 622 #define REG_MI_MCCMD1_CMD4_MASK 0x000000ff 623 624 #ifndef SDK_ASM 625 #define REG_MI_MCCMD1_FIELD( cmd7, cmd6, cmd5, cmd4 ) \ 626 (u32)( \ 627 ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \ 628 ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \ 629 ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \ 630 ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) 631 #endif 632 633 634 /* EXMEMCNT */ 635 636 #define REG_MI_EXMEMCNT_EP_SHIFT 15 637 #define REG_MI_EXMEMCNT_EP_SIZE 1 638 #define REG_MI_EXMEMCNT_EP_MASK 0x8000 639 640 #define REG_MI_EXMEMCNT_IFM_SHIFT 14 641 #define REG_MI_EXMEMCNT_IFM_SIZE 1 642 #define REG_MI_EXMEMCNT_IFM_MASK 0x4000 643 644 #define REG_MI_EXMEMCNT_MP_SHIFT 11 645 #define REG_MI_EXMEMCNT_MP_SIZE 1 646 #define REG_MI_EXMEMCNT_MP_MASK 0x0800 647 648 #define REG_MI_EXMEMCNT_CP_SHIFT 7 649 #define REG_MI_EXMEMCNT_CP_SIZE 1 650 #define REG_MI_EXMEMCNT_CP_MASK 0x0080 651 652 #define REG_MI_EXMEMCNT_PHI_SHIFT 5 653 #define REG_MI_EXMEMCNT_PHI_SIZE 2 654 #define REG_MI_EXMEMCNT_PHI_MASK 0x0060 655 656 #define REG_MI_EXMEMCNT_ROM2nd_SHIFT 4 657 #define REG_MI_EXMEMCNT_ROM2nd_SIZE 1 658 #define REG_MI_EXMEMCNT_ROM2nd_MASK 0x0010 659 660 #define REG_MI_EXMEMCNT_ROM1st_SHIFT 2 661 #define REG_MI_EXMEMCNT_ROM1st_SIZE 2 662 #define REG_MI_EXMEMCNT_ROM1st_MASK 0x000c 663 664 #define REG_MI_EXMEMCNT_RAM_SHIFT 0 665 #define REG_MI_EXMEMCNT_RAM_SIZE 2 666 #define REG_MI_EXMEMCNT_RAM_MASK 0x0003 667 668 #ifndef SDK_ASM 669 #define REG_MI_EXMEMCNT_FIELD( ep, ifm, mp, cp, phi, rom2nd, rom1st, ram ) \ 670 (u16)( \ 671 ((u32)(ep) << REG_MI_EXMEMCNT_EP_SHIFT) | \ 672 ((u32)(ifm) << REG_MI_EXMEMCNT_IFM_SHIFT) | \ 673 ((u32)(mp) << REG_MI_EXMEMCNT_MP_SHIFT) | \ 674 ((u32)(cp) << REG_MI_EXMEMCNT_CP_SHIFT) | \ 675 ((u32)(phi) << REG_MI_EXMEMCNT_PHI_SHIFT) | \ 676 ((u32)(rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT) | \ 677 ((u32)(rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT) | \ 678 ((u32)(ram) << REG_MI_EXMEMCNT_RAM_SHIFT)) 679 #endif 680 681 682 #ifdef __cplusplus 683 } /* extern "C" */ 684 #endif 685 686 /* NITRO_HW_ARM9_IOREG_MI_H_ */ 687 #endif 688