1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_GX.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_GX_H_ 18 #define NITRO_HW_ARM9_IOREG_GX_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DISPCNT */ 35 36 #define REG_DISPCNT_OFFSET 0x000 37 #define REG_DISPCNT_ADDR (HW_REG_BASE + REG_DISPCNT_OFFSET) 38 #define reg_GX_DISPCNT (*( REGType32v *) REG_DISPCNT_ADDR) 39 40 /* DISPSTAT */ 41 42 #define REG_DISPSTAT_OFFSET 0x004 43 #define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET) 44 #define reg_GX_DISPSTAT (*( REGType16v *) REG_DISPSTAT_ADDR) 45 46 /* VCOUNT */ 47 48 #define REG_VCOUNT_OFFSET 0x006 49 #define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) 50 #define reg_GX_VCOUNT (*( REGType16v *) REG_VCOUNT_ADDR) 51 52 /* DISPCAPCNT */ 53 54 #define REG_DISPCAPCNT_OFFSET 0x064 55 #define REG_DISPCAPCNT_ADDR (HW_REG_BASE + REG_DISPCAPCNT_OFFSET) 56 #define reg_GX_DISPCAPCNT (*( REGType32v *) REG_DISPCAPCNT_ADDR) 57 58 /* DISP_MMEM_FIFO */ 59 60 #define REG_DISP_MMEM_FIFO_OFFSET 0x068 61 #define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) 62 #define reg_GX_DISP_MMEM_FIFO (*( REGType32v *) REG_DISP_MMEM_FIFO_ADDR) 63 64 /* DISP_MMEM_FIFO_L */ 65 66 #define REG_DISP_MMEM_FIFO_L_OFFSET 0x068 67 #define REG_DISP_MMEM_FIFO_L_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_L_OFFSET) 68 #define reg_GX_DISP_MMEM_FIFO_L (*( REGType16v *) REG_DISP_MMEM_FIFO_L_ADDR) 69 70 /* DISP_MMEM_FIFO_H */ 71 72 #define REG_DISP_MMEM_FIFO_H_OFFSET 0x06a 73 #define REG_DISP_MMEM_FIFO_H_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_H_OFFSET) 74 #define reg_GX_DISP_MMEM_FIFO_H (*( REGType16v *) REG_DISP_MMEM_FIFO_H_ADDR) 75 76 /* MASTER_BRIGHT */ 77 78 #define REG_MASTER_BRIGHT_OFFSET 0x06c 79 #define REG_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_MASTER_BRIGHT_OFFSET) 80 #define reg_GX_MASTER_BRIGHT (*( REGType16v *) REG_MASTER_BRIGHT_ADDR) 81 82 /* TVOUTCNT */ 83 84 #define REG_TVOUTCNT_OFFSET 0x070 85 #define REG_TVOUTCNT_ADDR (HW_REG_BASE + REG_TVOUTCNT_OFFSET) 86 #define reg_GX_TVOUTCNT (*( REGType16v *) REG_TVOUTCNT_ADDR) 87 88 /* VRAMCNT */ 89 90 #define REG_VRAMCNT_OFFSET 0x240 91 #define REG_VRAMCNT_ADDR (HW_REG_BASE + REG_VRAMCNT_OFFSET) 92 #define reg_GX_VRAMCNT (*( REGType32v *) REG_VRAMCNT_ADDR) 93 94 /* VRAMCNT_A */ 95 96 #define REG_VRAMCNT_A_OFFSET 0x240 97 #define REG_VRAMCNT_A_ADDR (HW_REG_BASE + REG_VRAMCNT_A_OFFSET) 98 #define reg_GX_VRAMCNT_A (*( REGType8v *) REG_VRAMCNT_A_ADDR) 99 100 /* VRAMCNT_B */ 101 102 #define REG_VRAMCNT_B_OFFSET 0x241 103 #define REG_VRAMCNT_B_ADDR (HW_REG_BASE + REG_VRAMCNT_B_OFFSET) 104 #define reg_GX_VRAMCNT_B (*( REGType8v *) REG_VRAMCNT_B_ADDR) 105 106 /* VRAMCNT_C */ 107 108 #define REG_VRAMCNT_C_OFFSET 0x242 109 #define REG_VRAMCNT_C_ADDR (HW_REG_BASE + REG_VRAMCNT_C_OFFSET) 110 #define reg_GX_VRAMCNT_C (*( REGType8v *) REG_VRAMCNT_C_ADDR) 111 112 /* VRAMCNT_D */ 113 114 #define REG_VRAMCNT_D_OFFSET 0x243 115 #define REG_VRAMCNT_D_ADDR (HW_REG_BASE + REG_VRAMCNT_D_OFFSET) 116 #define reg_GX_VRAMCNT_D (*( REGType8v *) REG_VRAMCNT_D_ADDR) 117 118 /* WVRAMCNT */ 119 120 #define REG_WVRAMCNT_OFFSET 0x244 121 #define REG_WVRAMCNT_ADDR (HW_REG_BASE + REG_WVRAMCNT_OFFSET) 122 #define reg_GX_WVRAMCNT (*( REGType32v *) REG_WVRAMCNT_ADDR) 123 124 /* VRAMCNT_E */ 125 126 #define REG_VRAMCNT_E_OFFSET 0x244 127 #define REG_VRAMCNT_E_ADDR (HW_REG_BASE + REG_VRAMCNT_E_OFFSET) 128 #define reg_GX_VRAMCNT_E (*( REGType8v *) REG_VRAMCNT_E_ADDR) 129 130 /* VRAMCNT_F */ 131 132 #define REG_VRAMCNT_F_OFFSET 0x245 133 #define REG_VRAMCNT_F_ADDR (HW_REG_BASE + REG_VRAMCNT_F_OFFSET) 134 #define reg_GX_VRAMCNT_F (*( REGType8v *) REG_VRAMCNT_F_ADDR) 135 136 /* VRAMCNT_G */ 137 138 #define REG_VRAMCNT_G_OFFSET 0x246 139 #define REG_VRAMCNT_G_ADDR (HW_REG_BASE + REG_VRAMCNT_G_OFFSET) 140 #define reg_GX_VRAMCNT_G (*( REGType8v *) REG_VRAMCNT_G_ADDR) 141 142 /* VRAMCNT_WRAM */ 143 144 #define REG_VRAMCNT_WRAM_OFFSET 0x247 145 #define REG_VRAMCNT_WRAM_ADDR (HW_REG_BASE + REG_VRAMCNT_WRAM_OFFSET) 146 #define reg_GX_VRAMCNT_WRAM (*( REGType8v *) REG_VRAMCNT_WRAM_ADDR) 147 148 /* VRAM_HI_CNT */ 149 150 #define REG_VRAM_HI_CNT_OFFSET 0x248 151 #define REG_VRAM_HI_CNT_ADDR (HW_REG_BASE + REG_VRAM_HI_CNT_OFFSET) 152 #define reg_GX_VRAM_HI_CNT (*( REGType16v *) REG_VRAM_HI_CNT_ADDR) 153 154 /* VRAMCNT_H */ 155 156 #define REG_VRAMCNT_H_OFFSET 0x248 157 #define REG_VRAMCNT_H_ADDR (HW_REG_BASE + REG_VRAMCNT_H_OFFSET) 158 #define reg_GX_VRAMCNT_H (*( REGType8v *) REG_VRAMCNT_H_ADDR) 159 160 /* VRAMCNT_I */ 161 162 #define REG_VRAMCNT_I_OFFSET 0x249 163 #define REG_VRAMCNT_I_ADDR (HW_REG_BASE + REG_VRAMCNT_I_OFFSET) 164 #define reg_GX_VRAMCNT_I (*( REGType8v *) REG_VRAMCNT_I_ADDR) 165 166 /* POWCNT */ 167 168 #define REG_POWCNT_OFFSET 0x304 169 #define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) 170 #define reg_GX_POWCNT (*( REGType16v *) REG_POWCNT_ADDR) 171 172 173 /* 174 * Definitions of Register fields 175 */ 176 177 178 /* DISPCNT */ 179 180 #define REG_GX_DISPCNT_O_SHIFT 31 181 #define REG_GX_DISPCNT_O_SIZE 1 182 #define REG_GX_DISPCNT_O_MASK 0x80000000 183 184 #define REG_GX_DISPCNT_BG_SHIFT 30 185 #define REG_GX_DISPCNT_BG_SIZE 1 186 #define REG_GX_DISPCNT_BG_MASK 0x40000000 187 188 #define REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT 27 189 #define REG_GX_DISPCNT_BGSCREENOFFSET_SIZE 3 190 #define REG_GX_DISPCNT_BGSCREENOFFSET_MASK 0x38000000 191 192 #define REG_GX_DISPCNT_BGCHAROFFSET_SHIFT 24 193 #define REG_GX_DISPCNT_BGCHAROFFSET_SIZE 3 194 #define REG_GX_DISPCNT_BGCHAROFFSET_MASK 0x07000000 195 196 #define REG_GX_DISPCNT_OH_SHIFT 23 197 #define REG_GX_DISPCNT_OH_SIZE 1 198 #define REG_GX_DISPCNT_OH_MASK 0x00800000 199 200 #define REG_GX_DISPCNT_EXOBJ_SHIFT 20 201 #define REG_GX_DISPCNT_EXOBJ_SIZE 3 202 #define REG_GX_DISPCNT_EXOBJ_MASK 0x00700000 203 204 #define REG_GX_DISPCNT_VRAM_SHIFT 18 205 #define REG_GX_DISPCNT_VRAM_SIZE 2 206 #define REG_GX_DISPCNT_VRAM_MASK 0x000c0000 207 208 #define REG_GX_DISPCNT_MODE_SHIFT 16 209 #define REG_GX_DISPCNT_MODE_SIZE 2 210 #define REG_GX_DISPCNT_MODE_MASK 0x00030000 211 212 #define REG_GX_DISPCNT_OW_SHIFT 15 213 #define REG_GX_DISPCNT_OW_SIZE 1 214 #define REG_GX_DISPCNT_OW_MASK 0x00008000 215 216 #define REG_GX_DISPCNT_W1_SHIFT 14 217 #define REG_GX_DISPCNT_W1_SIZE 1 218 #define REG_GX_DISPCNT_W1_MASK 0x00004000 219 220 #define REG_GX_DISPCNT_W0_SHIFT 13 221 #define REG_GX_DISPCNT_W0_SIZE 1 222 #define REG_GX_DISPCNT_W0_MASK 0x00002000 223 224 #define REG_GX_DISPCNT_DISPLAY_SHIFT 8 225 #define REG_GX_DISPCNT_DISPLAY_SIZE 5 226 #define REG_GX_DISPCNT_DISPLAY_MASK 0x00001f00 227 228 #define REG_GX_DISPCNT_BLANK_SHIFT 7 229 #define REG_GX_DISPCNT_BLANK_SIZE 1 230 #define REG_GX_DISPCNT_BLANK_MASK 0x00000080 231 232 #define REG_GX_DISPCNT_OBJMAP_SHIFT 4 233 #define REG_GX_DISPCNT_OBJMAP_SIZE 3 234 #define REG_GX_DISPCNT_OBJMAP_MASK 0x00000070 235 236 #define REG_GX_DISPCNT_BG02D3D_SHIFT 3 237 #define REG_GX_DISPCNT_BG02D3D_SIZE 1 238 #define REG_GX_DISPCNT_BG02D3D_MASK 0x00000008 239 240 #define REG_GX_DISPCNT_BGMODE_SHIFT 0 241 #define REG_GX_DISPCNT_BGMODE_SIZE 3 242 #define REG_GX_DISPCNT_BGMODE_MASK 0x00000007 243 244 #define REG_GX_DISPCNT_OBJMAP_CH_SHIFT 4 245 #define REG_GX_DISPCNT_OBJMAP_CH_SIZE 1 246 #define REG_GX_DISPCNT_OBJMAP_CH_MASK 0x00000010 247 248 #define REG_GX_DISPCNT_OBJMAP_BM_SHIFT 5 249 #define REG_GX_DISPCNT_OBJMAP_BM_SIZE 2 250 #define REG_GX_DISPCNT_OBJMAP_BM_MASK 0x00000060 251 252 #define REG_GX_DISPCNT_EXOBJ_CH_SHIFT 20 253 #define REG_GX_DISPCNT_EXOBJ_CH_SIZE 2 254 #define REG_GX_DISPCNT_EXOBJ_CH_MASK 0x00300000 255 256 #define REG_GX_DISPCNT_EXOBJ_BM_SHIFT 22 257 #define REG_GX_DISPCNT_EXOBJ_BM_SIZE 1 258 #define REG_GX_DISPCNT_EXOBJ_BM_MASK 0x00400000 259 260 #ifndef SDK_ASM 261 #define REG_GX_DISPCNT_FIELD( o, bg, bgscreenoffset, bgcharoffset, oh, exobj, vram, mode, ow, w1, w0, display, blank, objmap, bg02d3d, bgmode, objmap_ch, objmap_bm, exobj_ch, exobj_bm ) \ 262 (u32)( \ 263 ((u32)(o) << REG_GX_DISPCNT_O_SHIFT) | \ 264 ((u32)(bg) << REG_GX_DISPCNT_BG_SHIFT) | \ 265 ((u32)(bgscreenoffset) << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT) | \ 266 ((u32)(bgcharoffset) << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT) | \ 267 ((u32)(oh) << REG_GX_DISPCNT_OH_SHIFT) | \ 268 ((u32)(exobj) << REG_GX_DISPCNT_EXOBJ_SHIFT) | \ 269 ((u32)(vram) << REG_GX_DISPCNT_VRAM_SHIFT) | \ 270 ((u32)(mode) << REG_GX_DISPCNT_MODE_SHIFT) | \ 271 ((u32)(ow) << REG_GX_DISPCNT_OW_SHIFT) | \ 272 ((u32)(w1) << REG_GX_DISPCNT_W1_SHIFT) | \ 273 ((u32)(w0) << REG_GX_DISPCNT_W0_SHIFT) | \ 274 ((u32)(display) << REG_GX_DISPCNT_DISPLAY_SHIFT) | \ 275 ((u32)(blank) << REG_GX_DISPCNT_BLANK_SHIFT) | \ 276 ((u32)(objmap) << REG_GX_DISPCNT_OBJMAP_SHIFT) | \ 277 ((u32)(bg02d3d) << REG_GX_DISPCNT_BG02D3D_SHIFT) | \ 278 ((u32)(bgmode) << REG_GX_DISPCNT_BGMODE_SHIFT) | \ 279 ((u32)(objmap_ch) << REG_GX_DISPCNT_OBJMAP_CH_SHIFT) | \ 280 ((u32)(objmap_bm) << REG_GX_DISPCNT_OBJMAP_BM_SHIFT) | \ 281 ((u32)(exobj_ch) << REG_GX_DISPCNT_EXOBJ_CH_SHIFT) | \ 282 ((u32)(exobj_bm) << REG_GX_DISPCNT_EXOBJ_BM_SHIFT)) 283 #endif 284 285 286 /* DISPSTAT */ 287 288 #define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 289 #define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 290 #define REG_GX_DISPSTAT_VCOUNTER_MASK 0xff80 291 292 #define REG_GX_DISPSTAT_VQI_SHIFT 5 293 #define REG_GX_DISPSTAT_VQI_SIZE 1 294 #define REG_GX_DISPSTAT_VQI_MASK 0x0020 295 296 #define REG_GX_DISPSTAT_HBI_SHIFT 4 297 #define REG_GX_DISPSTAT_HBI_SIZE 1 298 #define REG_GX_DISPSTAT_HBI_MASK 0x0010 299 300 #define REG_GX_DISPSTAT_VBI_SHIFT 3 301 #define REG_GX_DISPSTAT_VBI_SIZE 1 302 #define REG_GX_DISPSTAT_VBI_MASK 0x0008 303 304 #define REG_GX_DISPSTAT_LYC_SHIFT 2 305 #define REG_GX_DISPSTAT_LYC_SIZE 1 306 #define REG_GX_DISPSTAT_LYC_MASK 0x0004 307 308 #define REG_GX_DISPSTAT_HBLK_SHIFT 1 309 #define REG_GX_DISPSTAT_HBLK_SIZE 1 310 #define REG_GX_DISPSTAT_HBLK_MASK 0x0002 311 312 #define REG_GX_DISPSTAT_VBLK_SHIFT 0 313 #define REG_GX_DISPSTAT_VBLK_SIZE 1 314 #define REG_GX_DISPSTAT_VBLK_MASK 0x0001 315 316 #ifndef SDK_ASM 317 #define REG_GX_DISPSTAT_FIELD( vcounter, vqi, hbi, vbi, lyc, hblk, vblk ) \ 318 (u16)( \ 319 ((u32)(vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT) | \ 320 ((u32)(vqi) << REG_GX_DISPSTAT_VQI_SHIFT) | \ 321 ((u32)(hbi) << REG_GX_DISPSTAT_HBI_SHIFT) | \ 322 ((u32)(vbi) << REG_GX_DISPSTAT_VBI_SHIFT) | \ 323 ((u32)(lyc) << REG_GX_DISPSTAT_LYC_SHIFT) | \ 324 ((u32)(hblk) << REG_GX_DISPSTAT_HBLK_SHIFT) | \ 325 ((u32)(vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) 326 #endif 327 328 329 /* VCOUNT */ 330 331 #define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 332 #define REG_GX_VCOUNT_VCOUNTER_SIZE 9 333 #define REG_GX_VCOUNT_VCOUNTER_MASK 0x01ff 334 335 #ifndef SDK_ASM 336 #define REG_GX_VCOUNT_FIELD( vcounter ) \ 337 (u16)( \ 338 ((u32)(vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) 339 #endif 340 341 342 /* DISPCAPCNT */ 343 344 #define REG_GX_DISPCAPCNT_E_SHIFT 31 345 #define REG_GX_DISPCAPCNT_E_SIZE 1 346 #define REG_GX_DISPCAPCNT_E_MASK 0x80000000 347 348 #define REG_GX_DISPCAPCNT_MOD_SHIFT 29 349 #define REG_GX_DISPCAPCNT_MOD_SIZE 2 350 #define REG_GX_DISPCAPCNT_MOD_MASK 0x60000000 351 352 #define REG_GX_DISPCAPCNT_COFS_SHIFT 26 353 #define REG_GX_DISPCAPCNT_COFS_SIZE 2 354 #define REG_GX_DISPCAPCNT_COFS_MASK 0x0c000000 355 356 #define REG_GX_DISPCAPCNT_SRCB_SHIFT 25 357 #define REG_GX_DISPCAPCNT_SRCB_SIZE 1 358 #define REG_GX_DISPCAPCNT_SRCB_MASK 0x02000000 359 360 #define REG_GX_DISPCAPCNT_SRCA_SHIFT 24 361 #define REG_GX_DISPCAPCNT_SRCA_SIZE 1 362 #define REG_GX_DISPCAPCNT_SRCA_MASK 0x01000000 363 364 #define REG_GX_DISPCAPCNT_WSIZE_SHIFT 20 365 #define REG_GX_DISPCAPCNT_WSIZE_SIZE 2 366 #define REG_GX_DISPCAPCNT_WSIZE_MASK 0x00300000 367 368 #define REG_GX_DISPCAPCNT_WOFS_SHIFT 18 369 #define REG_GX_DISPCAPCNT_WOFS_SIZE 2 370 #define REG_GX_DISPCAPCNT_WOFS_MASK 0x000c0000 371 372 #define REG_GX_DISPCAPCNT_DEST_SHIFT 16 373 #define REG_GX_DISPCAPCNT_DEST_SIZE 2 374 #define REG_GX_DISPCAPCNT_DEST_MASK 0x00030000 375 376 #define REG_GX_DISPCAPCNT_EVB_SHIFT 8 377 #define REG_GX_DISPCAPCNT_EVB_SIZE 5 378 #define REG_GX_DISPCAPCNT_EVB_MASK 0x00001f00 379 380 #define REG_GX_DISPCAPCNT_EVA_SHIFT 0 381 #define REG_GX_DISPCAPCNT_EVA_SIZE 5 382 #define REG_GX_DISPCAPCNT_EVA_MASK 0x0000001f 383 384 #ifndef SDK_ASM 385 #define REG_GX_DISPCAPCNT_FIELD( e, mod, cofs, srcb, srca, wsize, wofs, dest, evb, eva ) \ 386 (u32)( \ 387 ((u32)(e) << REG_GX_DISPCAPCNT_E_SHIFT) | \ 388 ((u32)(mod) << REG_GX_DISPCAPCNT_MOD_SHIFT) | \ 389 ((u32)(cofs) << REG_GX_DISPCAPCNT_COFS_SHIFT) | \ 390 ((u32)(srcb) << REG_GX_DISPCAPCNT_SRCB_SHIFT) | \ 391 ((u32)(srca) << REG_GX_DISPCAPCNT_SRCA_SHIFT) | \ 392 ((u32)(wsize) << REG_GX_DISPCAPCNT_WSIZE_SHIFT) | \ 393 ((u32)(wofs) << REG_GX_DISPCAPCNT_WOFS_SHIFT) | \ 394 ((u32)(dest) << REG_GX_DISPCAPCNT_DEST_SHIFT) | \ 395 ((u32)(evb) << REG_GX_DISPCAPCNT_EVB_SHIFT) | \ 396 ((u32)(eva) << REG_GX_DISPCAPCNT_EVA_SHIFT)) 397 #endif 398 399 400 /* DISP_MMEM_FIFO */ 401 402 #define REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT 0 403 #define REG_GX_DISP_MMEM_FIFO_EVEN_SIZE 16 404 #define REG_GX_DISP_MMEM_FIFO_EVEN_MASK 0x0000ffff 405 406 #define REG_GX_DISP_MMEM_FIFO_ODD_SHIFT 16 407 #define REG_GX_DISP_MMEM_FIFO_ODD_SIZE 16 408 #define REG_GX_DISP_MMEM_FIFO_ODD_MASK 0xffff0000 409 410 #ifndef SDK_ASM 411 #define REG_GX_DISP_MMEM_FIFO_FIELD( even, odd ) \ 412 (u32)( \ 413 ((u32)(even) << REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT) | \ 414 ((u32)(odd) << REG_GX_DISP_MMEM_FIFO_ODD_SHIFT)) 415 #endif 416 417 418 /* DISP_MMEM_FIFO_L */ 419 420 #define REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT 0 421 #define REG_GX_DISP_MMEM_FIFO_L_RED_SIZE 5 422 #define REG_GX_DISP_MMEM_FIFO_L_RED_MASK 0x001f 423 424 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT 5 425 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_SIZE 5 426 #define REG_GX_DISP_MMEM_FIFO_L_GREEN_MASK 0x03e0 427 428 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT 10 429 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_SIZE 5 430 #define REG_GX_DISP_MMEM_FIFO_L_BLUE_MASK 0x7c00 431 432 #ifndef SDK_ASM 433 #define REG_GX_DISP_MMEM_FIFO_L_FIELD( red, green, blue ) \ 434 (u16)( \ 435 ((u32)(red) << REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT) | \ 436 ((u32)(green) << REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT) | \ 437 ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT)) 438 #endif 439 440 441 /* DISP_MMEM_FIFO_H */ 442 443 #define REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT 0 444 #define REG_GX_DISP_MMEM_FIFO_H_RED_SIZE 5 445 #define REG_GX_DISP_MMEM_FIFO_H_RED_MASK 0x001f 446 447 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT 5 448 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_SIZE 5 449 #define REG_GX_DISP_MMEM_FIFO_H_GREEN_MASK 0x03e0 450 451 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT 10 452 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_SIZE 5 453 #define REG_GX_DISP_MMEM_FIFO_H_BLUE_MASK 0x7c00 454 455 #ifndef SDK_ASM 456 #define REG_GX_DISP_MMEM_FIFO_H_FIELD( red, green, blue ) \ 457 (u16)( \ 458 ((u32)(red) << REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT) | \ 459 ((u32)(green) << REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT) | \ 460 ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT)) 461 #endif 462 463 464 /* MASTER_BRIGHT */ 465 466 #define REG_GX_MASTER_BRIGHT_E_MOD_SHIFT 14 467 #define REG_GX_MASTER_BRIGHT_E_MOD_SIZE 2 468 #define REG_GX_MASTER_BRIGHT_E_MOD_MASK 0xc000 469 470 #define REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT 0 471 #define REG_GX_MASTER_BRIGHT_E_VALUE_SIZE 5 472 #define REG_GX_MASTER_BRIGHT_E_VALUE_MASK 0x001f 473 474 #ifndef SDK_ASM 475 #define REG_GX_MASTER_BRIGHT_FIELD( e_mod, e_value ) \ 476 (u16)( \ 477 ((u32)(e_mod) << REG_GX_MASTER_BRIGHT_E_MOD_SHIFT) | \ 478 ((u32)(e_value) << REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT)) 479 #endif 480 481 482 /* TVOUTCNT */ 483 484 #define REG_GX_TVOUTCNT_COMMAND3_SHIFT 8 485 #define REG_GX_TVOUTCNT_COMMAND3_SIZE 4 486 #define REG_GX_TVOUTCNT_COMMAND3_MASK 0x0f00 487 488 #define REG_GX_TVOUTCNT_COMMAND2_SHIFT 4 489 #define REG_GX_TVOUTCNT_COMMAND2_SIZE 4 490 #define REG_GX_TVOUTCNT_COMMAND2_MASK 0x00f0 491 492 #define REG_GX_TVOUTCNT_COMMAND_SHIFT 0 493 #define REG_GX_TVOUTCNT_COMMAND_SIZE 4 494 #define REG_GX_TVOUTCNT_COMMAND_MASK 0x000f 495 496 #ifndef SDK_ASM 497 #define REG_GX_TVOUTCNT_FIELD( command3, command2, command ) \ 498 (u16)( \ 499 ((u32)(command3) << REG_GX_TVOUTCNT_COMMAND3_SHIFT) | \ 500 ((u32)(command2) << REG_GX_TVOUTCNT_COMMAND2_SHIFT) | \ 501 ((u32)(command) << REG_GX_TVOUTCNT_COMMAND_SHIFT)) 502 #endif 503 504 505 /* VRAMCNT */ 506 507 /* VRAMCNT_A */ 508 509 #define REG_GX_VRAMCNT_A_E_SHIFT 7 510 #define REG_GX_VRAMCNT_A_E_SIZE 1 511 #define REG_GX_VRAMCNT_A_E_MASK 0x80 512 513 #define REG_GX_VRAMCNT_A_OFS_SHIFT 3 514 #define REG_GX_VRAMCNT_A_OFS_SIZE 2 515 #define REG_GX_VRAMCNT_A_OFS_MASK 0x18 516 517 #define REG_GX_VRAMCNT_A_MST_SHIFT 0 518 #define REG_GX_VRAMCNT_A_MST_SIZE 2 519 #define REG_GX_VRAMCNT_A_MST_MASK 0x03 520 521 #ifndef SDK_ASM 522 #define REG_GX_VRAMCNT_A_FIELD( e, ofs, mst ) \ 523 (u8)( \ 524 ((u32)(e) << REG_GX_VRAMCNT_A_E_SHIFT) | \ 525 ((u32)(ofs) << REG_GX_VRAMCNT_A_OFS_SHIFT) | \ 526 ((u32)(mst) << REG_GX_VRAMCNT_A_MST_SHIFT)) 527 #endif 528 529 530 /* VRAMCNT_B */ 531 532 #define REG_GX_VRAMCNT_B_E_SHIFT 7 533 #define REG_GX_VRAMCNT_B_E_SIZE 1 534 #define REG_GX_VRAMCNT_B_E_MASK 0x80 535 536 #define REG_GX_VRAMCNT_B_OFS_SHIFT 3 537 #define REG_GX_VRAMCNT_B_OFS_SIZE 2 538 #define REG_GX_VRAMCNT_B_OFS_MASK 0x18 539 540 #define REG_GX_VRAMCNT_B_MST_SHIFT 0 541 #define REG_GX_VRAMCNT_B_MST_SIZE 2 542 #define REG_GX_VRAMCNT_B_MST_MASK 0x03 543 544 #ifndef SDK_ASM 545 #define REG_GX_VRAMCNT_B_FIELD( e, ofs, mst ) \ 546 (u8)( \ 547 ((u32)(e) << REG_GX_VRAMCNT_B_E_SHIFT) | \ 548 ((u32)(ofs) << REG_GX_VRAMCNT_B_OFS_SHIFT) | \ 549 ((u32)(mst) << REG_GX_VRAMCNT_B_MST_SHIFT)) 550 #endif 551 552 553 /* VRAMCNT_C */ 554 555 #define REG_GX_VRAMCNT_C_E_SHIFT 7 556 #define REG_GX_VRAMCNT_C_E_SIZE 1 557 #define REG_GX_VRAMCNT_C_E_MASK 0x80 558 559 #define REG_GX_VRAMCNT_C_OFS_SHIFT 3 560 #define REG_GX_VRAMCNT_C_OFS_SIZE 2 561 #define REG_GX_VRAMCNT_C_OFS_MASK 0x18 562 563 #define REG_GX_VRAMCNT_C_MST_SHIFT 0 564 #define REG_GX_VRAMCNT_C_MST_SIZE 3 565 #define REG_GX_VRAMCNT_C_MST_MASK 0x07 566 567 #ifndef SDK_ASM 568 #define REG_GX_VRAMCNT_C_FIELD( e, ofs, mst ) \ 569 (u8)( \ 570 ((u32)(e) << REG_GX_VRAMCNT_C_E_SHIFT) | \ 571 ((u32)(ofs) << REG_GX_VRAMCNT_C_OFS_SHIFT) | \ 572 ((u32)(mst) << REG_GX_VRAMCNT_C_MST_SHIFT)) 573 #endif 574 575 576 /* VRAMCNT_D */ 577 578 #define REG_GX_VRAMCNT_D_E_SHIFT 7 579 #define REG_GX_VRAMCNT_D_E_SIZE 1 580 #define REG_GX_VRAMCNT_D_E_MASK 0x80 581 582 #define REG_GX_VRAMCNT_D_OFS_SHIFT 3 583 #define REG_GX_VRAMCNT_D_OFS_SIZE 2 584 #define REG_GX_VRAMCNT_D_OFS_MASK 0x18 585 586 #define REG_GX_VRAMCNT_D_MST_SHIFT 0 587 #define REG_GX_VRAMCNT_D_MST_SIZE 3 588 #define REG_GX_VRAMCNT_D_MST_MASK 0x07 589 590 #ifndef SDK_ASM 591 #define REG_GX_VRAMCNT_D_FIELD( e, ofs, mst ) \ 592 (u8)( \ 593 ((u32)(e) << REG_GX_VRAMCNT_D_E_SHIFT) | \ 594 ((u32)(ofs) << REG_GX_VRAMCNT_D_OFS_SHIFT) | \ 595 ((u32)(mst) << REG_GX_VRAMCNT_D_MST_SHIFT)) 596 #endif 597 598 599 /* WVRAMCNT */ 600 601 /* VRAMCNT_E */ 602 603 #define REG_GX_VRAMCNT_E_E_SHIFT 7 604 #define REG_GX_VRAMCNT_E_E_SIZE 1 605 #define REG_GX_VRAMCNT_E_E_MASK 0x80 606 607 #define REG_GX_VRAMCNT_E_MST_SHIFT 0 608 #define REG_GX_VRAMCNT_E_MST_SIZE 3 609 #define REG_GX_VRAMCNT_E_MST_MASK 0x07 610 611 #ifndef SDK_ASM 612 #define REG_GX_VRAMCNT_E_FIELD( e, mst ) \ 613 (u8)( \ 614 ((u32)(e) << REG_GX_VRAMCNT_E_E_SHIFT) | \ 615 ((u32)(mst) << REG_GX_VRAMCNT_E_MST_SHIFT)) 616 #endif 617 618 619 /* VRAMCNT_F */ 620 621 #define REG_GX_VRAMCNT_F_E_SHIFT 7 622 #define REG_GX_VRAMCNT_F_E_SIZE 1 623 #define REG_GX_VRAMCNT_F_E_MASK 0x80 624 625 #define REG_GX_VRAMCNT_F_OFS_SHIFT 3 626 #define REG_GX_VRAMCNT_F_OFS_SIZE 2 627 #define REG_GX_VRAMCNT_F_OFS_MASK 0x18 628 629 #define REG_GX_VRAMCNT_F_MST_SHIFT 0 630 #define REG_GX_VRAMCNT_F_MST_SIZE 3 631 #define REG_GX_VRAMCNT_F_MST_MASK 0x07 632 633 #ifndef SDK_ASM 634 #define REG_GX_VRAMCNT_F_FIELD( e, ofs, mst ) \ 635 (u8)( \ 636 ((u32)(e) << REG_GX_VRAMCNT_F_E_SHIFT) | \ 637 ((u32)(ofs) << REG_GX_VRAMCNT_F_OFS_SHIFT) | \ 638 ((u32)(mst) << REG_GX_VRAMCNT_F_MST_SHIFT)) 639 #endif 640 641 642 /* VRAMCNT_G */ 643 644 #define REG_GX_VRAMCNT_G_E_SHIFT 7 645 #define REG_GX_VRAMCNT_G_E_SIZE 1 646 #define REG_GX_VRAMCNT_G_E_MASK 0x80 647 648 #define REG_GX_VRAMCNT_G_OFS_SHIFT 3 649 #define REG_GX_VRAMCNT_G_OFS_SIZE 2 650 #define REG_GX_VRAMCNT_G_OFS_MASK 0x18 651 652 #define REG_GX_VRAMCNT_G_MST_SHIFT 0 653 #define REG_GX_VRAMCNT_G_MST_SIZE 3 654 #define REG_GX_VRAMCNT_G_MST_MASK 0x07 655 656 #ifndef SDK_ASM 657 #define REG_GX_VRAMCNT_G_FIELD( e, ofs, mst ) \ 658 (u8)( \ 659 ((u32)(e) << REG_GX_VRAMCNT_G_E_SHIFT) | \ 660 ((u32)(ofs) << REG_GX_VRAMCNT_G_OFS_SHIFT) | \ 661 ((u32)(mst) << REG_GX_VRAMCNT_G_MST_SHIFT)) 662 #endif 663 664 665 /* VRAMCNT_WRAM */ 666 667 #define REG_GX_VRAMCNT_WRAM_BANK_SHIFT 0 668 #define REG_GX_VRAMCNT_WRAM_BANK_SIZE 2 669 #define REG_GX_VRAMCNT_WRAM_BANK_MASK 0x03 670 671 #ifndef SDK_ASM 672 #define REG_GX_VRAMCNT_WRAM_FIELD( bank ) \ 673 (u8)( \ 674 ((u32)(bank) << REG_GX_VRAMCNT_WRAM_BANK_SHIFT)) 675 #endif 676 677 678 /* VRAM_HI_CNT */ 679 680 /* VRAMCNT_H */ 681 682 #define REG_GX_VRAMCNT_H_E_SHIFT 7 683 #define REG_GX_VRAMCNT_H_E_SIZE 1 684 #define REG_GX_VRAMCNT_H_E_MASK 0x80 685 686 #define REG_GX_VRAMCNT_H_MST_SHIFT 0 687 #define REG_GX_VRAMCNT_H_MST_SIZE 2 688 #define REG_GX_VRAMCNT_H_MST_MASK 0x03 689 690 #ifndef SDK_ASM 691 #define REG_GX_VRAMCNT_H_FIELD( e, mst ) \ 692 (u8)( \ 693 ((u32)(e) << REG_GX_VRAMCNT_H_E_SHIFT) | \ 694 ((u32)(mst) << REG_GX_VRAMCNT_H_MST_SHIFT)) 695 #endif 696 697 698 /* VRAMCNT_I */ 699 700 #define REG_GX_VRAMCNT_I_E_SHIFT 7 701 #define REG_GX_VRAMCNT_I_E_SIZE 1 702 #define REG_GX_VRAMCNT_I_E_MASK 0x80 703 704 #define REG_GX_VRAMCNT_I_MST_SHIFT 0 705 #define REG_GX_VRAMCNT_I_MST_SIZE 2 706 #define REG_GX_VRAMCNT_I_MST_MASK 0x03 707 708 #ifndef SDK_ASM 709 #define REG_GX_VRAMCNT_I_FIELD( e, mst ) \ 710 (u8)( \ 711 ((u32)(e) << REG_GX_VRAMCNT_I_E_SHIFT) | \ 712 ((u32)(mst) << REG_GX_VRAMCNT_I_MST_SHIFT)) 713 #endif 714 715 716 /* POWCNT */ 717 718 #define REG_GX_POWCNT_GE_SHIFT 3 719 #define REG_GX_POWCNT_GE_SIZE 1 720 #define REG_GX_POWCNT_GE_MASK 0x0008 721 722 #define REG_GX_POWCNT_RE_SHIFT 2 723 #define REG_GX_POWCNT_RE_SIZE 1 724 #define REG_GX_POWCNT_RE_MASK 0x0004 725 726 #define REG_GX_POWCNT_E2DG_SHIFT 1 727 #define REG_GX_POWCNT_E2DG_SIZE 1 728 #define REG_GX_POWCNT_E2DG_MASK 0x0002 729 730 #define REG_GX_POWCNT_LCD_SHIFT 0 731 #define REG_GX_POWCNT_LCD_SIZE 1 732 #define REG_GX_POWCNT_LCD_MASK 0x0001 733 734 #define REG_GX_POWCNT_LCDB_SHIFT 8 735 #define REG_GX_POWCNT_LCDB_SIZE 1 736 #define REG_GX_POWCNT_LCDB_MASK 0x0100 737 738 #define REG_GX_POWCNT_E2DGB_SHIFT 9 739 #define REG_GX_POWCNT_E2DGB_SIZE 1 740 #define REG_GX_POWCNT_E2DGB_MASK 0x0200 741 742 #define REG_GX_POWCNT_DSEL_SHIFT 15 743 #define REG_GX_POWCNT_DSEL_SIZE 1 744 #define REG_GX_POWCNT_DSEL_MASK 0x8000 745 746 #ifndef SDK_ASM 747 #define REG_GX_POWCNT_FIELD( ge, re, e2dg, lcd, lcdb, e2dgb, dsel ) \ 748 (u16)( \ 749 ((u32)(ge) << REG_GX_POWCNT_GE_SHIFT) | \ 750 ((u32)(re) << REG_GX_POWCNT_RE_SHIFT) | \ 751 ((u32)(e2dg) << REG_GX_POWCNT_E2DG_SHIFT) | \ 752 ((u32)(lcd) << REG_GX_POWCNT_LCD_SHIFT) | \ 753 ((u32)(lcdb) << REG_GX_POWCNT_LCDB_SHIFT) | \ 754 ((u32)(e2dgb) << REG_GX_POWCNT_E2DGB_SHIFT) | \ 755 ((u32)(dsel) << REG_GX_POWCNT_DSEL_SHIFT)) 756 #endif 757 758 759 #ifdef __cplusplus 760 } /* extern "C" */ 761 #endif 762 763 /* NITRO_HW_ARM9_IOREG_GX_H_ */ 764 #endif 765