1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_G3X.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_G3X_H_ 18 #define NITRO_HW_ARM9_IOREG_G3X_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* DISP3DCNT */ 35 36 #define REG_DISP3DCNT_OFFSET 0x060 37 #define REG_DISP3DCNT_ADDR (HW_REG_BASE + REG_DISP3DCNT_OFFSET) 38 #define reg_G3X_DISP3DCNT (*( REGType16v *) REG_DISP3DCNT_ADDR) 39 40 /* RDLINES_COUNT */ 41 42 #define REG_RDLINES_COUNT_OFFSET 0x320 43 #define REG_RDLINES_COUNT_ADDR (HW_REG_BASE + REG_RDLINES_COUNT_OFFSET) 44 #define reg_G3X_RDLINES_COUNT (*(const REGType16v *) REG_RDLINES_COUNT_ADDR) 45 46 /* EDGE_COLOR_0 */ 47 48 #define REG_EDGE_COLOR_0_OFFSET 0x330 49 #define REG_EDGE_COLOR_0_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_OFFSET) 50 #define reg_G3X_EDGE_COLOR_0 (*( REGType32v *) REG_EDGE_COLOR_0_ADDR) 51 52 /* EDGE_COLOR_0_L */ 53 54 #define REG_EDGE_COLOR_0_L_OFFSET 0x330 55 #define REG_EDGE_COLOR_0_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_L_OFFSET) 56 #define reg_G3X_EDGE_COLOR_0_L (*( REGType16v *) REG_EDGE_COLOR_0_L_ADDR) 57 58 /* EDGE_COLOR_0_H */ 59 60 #define REG_EDGE_COLOR_0_H_OFFSET 0x332 61 #define REG_EDGE_COLOR_0_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_H_OFFSET) 62 #define reg_G3X_EDGE_COLOR_0_H (*( REGType16v *) REG_EDGE_COLOR_0_H_ADDR) 63 64 /* EDGE_COLOR_1 */ 65 66 #define REG_EDGE_COLOR_1_OFFSET 0x334 67 #define REG_EDGE_COLOR_1_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_OFFSET) 68 #define reg_G3X_EDGE_COLOR_1 (*( REGType32v *) REG_EDGE_COLOR_1_ADDR) 69 70 /* EDGE_COLOR_1_L */ 71 72 #define REG_EDGE_COLOR_1_L_OFFSET 0x334 73 #define REG_EDGE_COLOR_1_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_L_OFFSET) 74 #define reg_G3X_EDGE_COLOR_1_L (*( REGType16v *) REG_EDGE_COLOR_1_L_ADDR) 75 76 /* EDGE_COLOR_1_H */ 77 78 #define REG_EDGE_COLOR_1_H_OFFSET 0x336 79 #define REG_EDGE_COLOR_1_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_H_OFFSET) 80 #define reg_G3X_EDGE_COLOR_1_H (*( REGType16v *) REG_EDGE_COLOR_1_H_ADDR) 81 82 /* EDGE_COLOR_2 */ 83 84 #define REG_EDGE_COLOR_2_OFFSET 0x338 85 #define REG_EDGE_COLOR_2_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_OFFSET) 86 #define reg_G3X_EDGE_COLOR_2 (*( REGType32v *) REG_EDGE_COLOR_2_ADDR) 87 88 /* EDGE_COLOR_2_L */ 89 90 #define REG_EDGE_COLOR_2_L_OFFSET 0x338 91 #define REG_EDGE_COLOR_2_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_L_OFFSET) 92 #define reg_G3X_EDGE_COLOR_2_L (*( REGType16v *) REG_EDGE_COLOR_2_L_ADDR) 93 94 /* EDGE_COLOR_2_H */ 95 96 #define REG_EDGE_COLOR_2_H_OFFSET 0x33a 97 #define REG_EDGE_COLOR_2_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_H_OFFSET) 98 #define reg_G3X_EDGE_COLOR_2_H (*( REGType16v *) REG_EDGE_COLOR_2_H_ADDR) 99 100 /* EDGE_COLOR_3 */ 101 102 #define REG_EDGE_COLOR_3_OFFSET 0x33c 103 #define REG_EDGE_COLOR_3_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_OFFSET) 104 #define reg_G3X_EDGE_COLOR_3 (*( REGType32v *) REG_EDGE_COLOR_3_ADDR) 105 106 /* EDGE_COLOR_3_L */ 107 108 #define REG_EDGE_COLOR_3_L_OFFSET 0x33c 109 #define REG_EDGE_COLOR_3_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_L_OFFSET) 110 #define reg_G3X_EDGE_COLOR_3_L (*( REGType16v *) REG_EDGE_COLOR_3_L_ADDR) 111 112 /* EDGE_COLOR_3_H */ 113 114 #define REG_EDGE_COLOR_3_H_OFFSET 0x33e 115 #define REG_EDGE_COLOR_3_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_H_OFFSET) 116 #define reg_G3X_EDGE_COLOR_3_H (*( REGType16v *) REG_EDGE_COLOR_3_H_ADDR) 117 118 /* ALPHA_TEST_REF */ 119 120 #define REG_ALPHA_TEST_REF_OFFSET 0x340 121 #define REG_ALPHA_TEST_REF_ADDR (HW_REG_BASE + REG_ALPHA_TEST_REF_OFFSET) 122 #define reg_G3X_ALPHA_TEST_REF (*( REGType16v *) REG_ALPHA_TEST_REF_ADDR) 123 124 /* CLEAR_COLOR */ 125 126 #define REG_CLEAR_COLOR_OFFSET 0x350 127 #define REG_CLEAR_COLOR_ADDR (HW_REG_BASE + REG_CLEAR_COLOR_OFFSET) 128 #define reg_G3X_CLEAR_COLOR (*( REGType32v *) REG_CLEAR_COLOR_ADDR) 129 130 /* CLEAR_DEPTH */ 131 132 #define REG_CLEAR_DEPTH_OFFSET 0x354 133 #define REG_CLEAR_DEPTH_ADDR (HW_REG_BASE + REG_CLEAR_DEPTH_OFFSET) 134 #define reg_G3X_CLEAR_DEPTH (*( REGType16v *) REG_CLEAR_DEPTH_ADDR) 135 136 /* CLRIMAGE_OFFSET */ 137 138 #define REG_CLRIMAGE_OFFSET_OFFSET 0x356 139 #define REG_CLRIMAGE_OFFSET_ADDR (HW_REG_BASE + REG_CLRIMAGE_OFFSET_OFFSET) 140 #define reg_G3X_CLRIMAGE_OFFSET (*( REGType16v *) REG_CLRIMAGE_OFFSET_ADDR) 141 142 /* FOG_COLOR */ 143 144 #define REG_FOG_COLOR_OFFSET 0x358 145 #define REG_FOG_COLOR_ADDR (HW_REG_BASE + REG_FOG_COLOR_OFFSET) 146 #define reg_G3X_FOG_COLOR (*( REGType32v *) REG_FOG_COLOR_ADDR) 147 148 /* FOG_OFFSET */ 149 150 #define REG_FOG_OFFSET_OFFSET 0x35c 151 #define REG_FOG_OFFSET_ADDR (HW_REG_BASE + REG_FOG_OFFSET_OFFSET) 152 #define reg_G3X_FOG_OFFSET (*( REGType16v *) REG_FOG_OFFSET_ADDR) 153 154 /* FOG_TABLE_0 */ 155 156 #define REG_FOG_TABLE_0_OFFSET 0x360 157 #define REG_FOG_TABLE_0_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_OFFSET) 158 #define reg_G3X_FOG_TABLE_0 (*( REGType32v *) REG_FOG_TABLE_0_ADDR) 159 160 /* FOG_TABLE_0_L */ 161 162 #define REG_FOG_TABLE_0_L_OFFSET 0x360 163 #define REG_FOG_TABLE_0_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_L_OFFSET) 164 #define reg_G3X_FOG_TABLE_0_L (*( REGType16v *) REG_FOG_TABLE_0_L_ADDR) 165 166 /* FOG_TABLE_0_H */ 167 168 #define REG_FOG_TABLE_0_H_OFFSET 0x362 169 #define REG_FOG_TABLE_0_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_H_OFFSET) 170 #define reg_G3X_FOG_TABLE_0_H (*( REGType16v *) REG_FOG_TABLE_0_H_ADDR) 171 172 /* FOG_TABLE_1 */ 173 174 #define REG_FOG_TABLE_1_OFFSET 0x364 175 #define REG_FOG_TABLE_1_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_OFFSET) 176 #define reg_G3X_FOG_TABLE_1 (*( REGType32v *) REG_FOG_TABLE_1_ADDR) 177 178 /* FOG_TABLE_1_L */ 179 180 #define REG_FOG_TABLE_1_L_OFFSET 0x364 181 #define REG_FOG_TABLE_1_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_L_OFFSET) 182 #define reg_G3X_FOG_TABLE_1_L (*( REGType16v *) REG_FOG_TABLE_1_L_ADDR) 183 184 /* FOG_TABLE_1_H */ 185 186 #define REG_FOG_TABLE_1_H_OFFSET 0x366 187 #define REG_FOG_TABLE_1_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_H_OFFSET) 188 #define reg_G3X_FOG_TABLE_1_H (*( REGType16v *) REG_FOG_TABLE_1_H_ADDR) 189 190 /* FOG_TABLE_2 */ 191 192 #define REG_FOG_TABLE_2_OFFSET 0x368 193 #define REG_FOG_TABLE_2_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_OFFSET) 194 #define reg_G3X_FOG_TABLE_2 (*( REGType32v *) REG_FOG_TABLE_2_ADDR) 195 196 /* FOG_TABLE_2_L */ 197 198 #define REG_FOG_TABLE_2_L_OFFSET 0x368 199 #define REG_FOG_TABLE_2_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_L_OFFSET) 200 #define reg_G3X_FOG_TABLE_2_L (*( REGType16v *) REG_FOG_TABLE_2_L_ADDR) 201 202 /* FOG_TABLE_2_H */ 203 204 #define REG_FOG_TABLE_2_H_OFFSET 0x36a 205 #define REG_FOG_TABLE_2_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_H_OFFSET) 206 #define reg_G3X_FOG_TABLE_2_H (*( REGType16v *) REG_FOG_TABLE_2_H_ADDR) 207 208 /* FOG_TABLE_3 */ 209 210 #define REG_FOG_TABLE_3_OFFSET 0x36c 211 #define REG_FOG_TABLE_3_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_OFFSET) 212 #define reg_G3X_FOG_TABLE_3 (*( REGType32v *) REG_FOG_TABLE_3_ADDR) 213 214 /* FOG_TABLE_3_L */ 215 216 #define REG_FOG_TABLE_3_L_OFFSET 0x36c 217 #define REG_FOG_TABLE_3_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_L_OFFSET) 218 #define reg_G3X_FOG_TABLE_3_L (*( REGType16v *) REG_FOG_TABLE_3_L_ADDR) 219 220 /* FOG_TABLE_3_H */ 221 222 #define REG_FOG_TABLE_3_H_OFFSET 0x36e 223 #define REG_FOG_TABLE_3_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_H_OFFSET) 224 #define reg_G3X_FOG_TABLE_3_H (*( REGType16v *) REG_FOG_TABLE_3_H_ADDR) 225 226 /* FOG_TABLE_4 */ 227 228 #define REG_FOG_TABLE_4_OFFSET 0x370 229 #define REG_FOG_TABLE_4_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_OFFSET) 230 #define reg_G3X_FOG_TABLE_4 (*( REGType32v *) REG_FOG_TABLE_4_ADDR) 231 232 /* FOG_TABLE_4_L */ 233 234 #define REG_FOG_TABLE_4_L_OFFSET 0x370 235 #define REG_FOG_TABLE_4_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_L_OFFSET) 236 #define reg_G3X_FOG_TABLE_4_L (*( REGType16v *) REG_FOG_TABLE_4_L_ADDR) 237 238 /* FOG_TABLE_4_H */ 239 240 #define REG_FOG_TABLE_4_H_OFFSET 0x372 241 #define REG_FOG_TABLE_4_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_H_OFFSET) 242 #define reg_G3X_FOG_TABLE_4_H (*( REGType16v *) REG_FOG_TABLE_4_H_ADDR) 243 244 /* FOG_TABLE_5 */ 245 246 #define REG_FOG_TABLE_5_OFFSET 0x374 247 #define REG_FOG_TABLE_5_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_OFFSET) 248 #define reg_G3X_FOG_TABLE_5 (*( REGType32v *) REG_FOG_TABLE_5_ADDR) 249 250 /* FOG_TABLE_5_L */ 251 252 #define REG_FOG_TABLE_5_L_OFFSET 0x374 253 #define REG_FOG_TABLE_5_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_L_OFFSET) 254 #define reg_G3X_FOG_TABLE_5_L (*( REGType16v *) REG_FOG_TABLE_5_L_ADDR) 255 256 /* FOG_TABLE_5_H */ 257 258 #define REG_FOG_TABLE_5_H_OFFSET 0x376 259 #define REG_FOG_TABLE_5_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_H_OFFSET) 260 #define reg_G3X_FOG_TABLE_5_H (*( REGType16v *) REG_FOG_TABLE_5_H_ADDR) 261 262 /* FOG_TABLE_6 */ 263 264 #define REG_FOG_TABLE_6_OFFSET 0x378 265 #define REG_FOG_TABLE_6_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_OFFSET) 266 #define reg_G3X_FOG_TABLE_6 (*( REGType32v *) REG_FOG_TABLE_6_ADDR) 267 268 /* FOG_TABLE_6_L */ 269 270 #define REG_FOG_TABLE_6_L_OFFSET 0x378 271 #define REG_FOG_TABLE_6_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_L_OFFSET) 272 #define reg_G3X_FOG_TABLE_6_L (*( REGType16v *) REG_FOG_TABLE_6_L_ADDR) 273 274 /* FOG_TABLE_6_H */ 275 276 #define REG_FOG_TABLE_6_H_OFFSET 0x37a 277 #define REG_FOG_TABLE_6_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_H_OFFSET) 278 #define reg_G3X_FOG_TABLE_6_H (*( REGType16v *) REG_FOG_TABLE_6_H_ADDR) 279 280 /* FOG_TABLE_7 */ 281 282 #define REG_FOG_TABLE_7_OFFSET 0x37c 283 #define REG_FOG_TABLE_7_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_OFFSET) 284 #define reg_G3X_FOG_TABLE_7 (*( REGType32v *) REG_FOG_TABLE_7_ADDR) 285 286 /* FOG_TABLE_7_L */ 287 288 #define REG_FOG_TABLE_7_L_OFFSET 0x37c 289 #define REG_FOG_TABLE_7_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_L_OFFSET) 290 #define reg_G3X_FOG_TABLE_7_L (*( REGType16v *) REG_FOG_TABLE_7_L_ADDR) 291 292 /* FOG_TABLE_7_H */ 293 294 #define REG_FOG_TABLE_7_H_OFFSET 0x37e 295 #define REG_FOG_TABLE_7_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_H_OFFSET) 296 #define reg_G3X_FOG_TABLE_7_H (*( REGType16v *) REG_FOG_TABLE_7_H_ADDR) 297 298 /* TOON_TABLE_0 */ 299 300 #define REG_TOON_TABLE_0_OFFSET 0x380 301 #define REG_TOON_TABLE_0_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_OFFSET) 302 #define reg_G3X_TOON_TABLE_0 (*( REGType32v *) REG_TOON_TABLE_0_ADDR) 303 304 /* TOON_TABLE_0_L */ 305 306 #define REG_TOON_TABLE_0_L_OFFSET 0x380 307 #define REG_TOON_TABLE_0_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_L_OFFSET) 308 #define reg_G3X_TOON_TABLE_0_L (*( REGType16v *) REG_TOON_TABLE_0_L_ADDR) 309 310 /* TOON_TABLE_0_H */ 311 312 #define REG_TOON_TABLE_0_H_OFFSET 0x382 313 #define REG_TOON_TABLE_0_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_H_OFFSET) 314 #define reg_G3X_TOON_TABLE_0_H (*( REGType16v *) REG_TOON_TABLE_0_H_ADDR) 315 316 /* TOON_TABLE_1 */ 317 318 #define REG_TOON_TABLE_1_OFFSET 0x384 319 #define REG_TOON_TABLE_1_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_OFFSET) 320 #define reg_G3X_TOON_TABLE_1 (*( REGType32v *) REG_TOON_TABLE_1_ADDR) 321 322 /* TOON_TABLE_1_L */ 323 324 #define REG_TOON_TABLE_1_L_OFFSET 0x384 325 #define REG_TOON_TABLE_1_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_L_OFFSET) 326 #define reg_G3X_TOON_TABLE_1_L (*( REGType16v *) REG_TOON_TABLE_1_L_ADDR) 327 328 /* TOON_TABLE_1_H */ 329 330 #define REG_TOON_TABLE_1_H_OFFSET 0x386 331 #define REG_TOON_TABLE_1_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_H_OFFSET) 332 #define reg_G3X_TOON_TABLE_1_H (*( REGType16v *) REG_TOON_TABLE_1_H_ADDR) 333 334 /* TOON_TABLE_2 */ 335 336 #define REG_TOON_TABLE_2_OFFSET 0x388 337 #define REG_TOON_TABLE_2_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_OFFSET) 338 #define reg_G3X_TOON_TABLE_2 (*( REGType32v *) REG_TOON_TABLE_2_ADDR) 339 340 /* TOON_TABLE_2_L */ 341 342 #define REG_TOON_TABLE_2_L_OFFSET 0x388 343 #define REG_TOON_TABLE_2_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_L_OFFSET) 344 #define reg_G3X_TOON_TABLE_2_L (*( REGType16v *) REG_TOON_TABLE_2_L_ADDR) 345 346 /* TOON_TABLE_2_H */ 347 348 #define REG_TOON_TABLE_2_H_OFFSET 0x38a 349 #define REG_TOON_TABLE_2_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_H_OFFSET) 350 #define reg_G3X_TOON_TABLE_2_H (*( REGType16v *) REG_TOON_TABLE_2_H_ADDR) 351 352 /* TOON_TABLE_3 */ 353 354 #define REG_TOON_TABLE_3_OFFSET 0x38c 355 #define REG_TOON_TABLE_3_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_OFFSET) 356 #define reg_G3X_TOON_TABLE_3 (*( REGType32v *) REG_TOON_TABLE_3_ADDR) 357 358 /* TOON_TABLE_3_L */ 359 360 #define REG_TOON_TABLE_3_L_OFFSET 0x38c 361 #define REG_TOON_TABLE_3_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_L_OFFSET) 362 #define reg_G3X_TOON_TABLE_3_L (*( REGType16v *) REG_TOON_TABLE_3_L_ADDR) 363 364 /* TOON_TABLE_3_H */ 365 366 #define REG_TOON_TABLE_3_H_OFFSET 0x38e 367 #define REG_TOON_TABLE_3_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_H_OFFSET) 368 #define reg_G3X_TOON_TABLE_3_H (*( REGType16v *) REG_TOON_TABLE_3_H_ADDR) 369 370 /* TOON_TABLE_4 */ 371 372 #define REG_TOON_TABLE_4_OFFSET 0x390 373 #define REG_TOON_TABLE_4_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_OFFSET) 374 #define reg_G3X_TOON_TABLE_4 (*( REGType32v *) REG_TOON_TABLE_4_ADDR) 375 376 /* TOON_TABLE_4_L */ 377 378 #define REG_TOON_TABLE_4_L_OFFSET 0x390 379 #define REG_TOON_TABLE_4_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_L_OFFSET) 380 #define reg_G3X_TOON_TABLE_4_L (*( REGType16v *) REG_TOON_TABLE_4_L_ADDR) 381 382 /* TOON_TABLE_4_H */ 383 384 #define REG_TOON_TABLE_4_H_OFFSET 0x392 385 #define REG_TOON_TABLE_4_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_H_OFFSET) 386 #define reg_G3X_TOON_TABLE_4_H (*( REGType16v *) REG_TOON_TABLE_4_H_ADDR) 387 388 /* TOON_TABLE_5 */ 389 390 #define REG_TOON_TABLE_5_OFFSET 0x394 391 #define REG_TOON_TABLE_5_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_OFFSET) 392 #define reg_G3X_TOON_TABLE_5 (*( REGType32v *) REG_TOON_TABLE_5_ADDR) 393 394 /* TOON_TABLE_5_L */ 395 396 #define REG_TOON_TABLE_5_L_OFFSET 0x394 397 #define REG_TOON_TABLE_5_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_L_OFFSET) 398 #define reg_G3X_TOON_TABLE_5_L (*( REGType16v *) REG_TOON_TABLE_5_L_ADDR) 399 400 /* TOON_TABLE_5_H */ 401 402 #define REG_TOON_TABLE_5_H_OFFSET 0x396 403 #define REG_TOON_TABLE_5_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_H_OFFSET) 404 #define reg_G3X_TOON_TABLE_5_H (*( REGType16v *) REG_TOON_TABLE_5_H_ADDR) 405 406 /* TOON_TABLE_6 */ 407 408 #define REG_TOON_TABLE_6_OFFSET 0x398 409 #define REG_TOON_TABLE_6_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_OFFSET) 410 #define reg_G3X_TOON_TABLE_6 (*( REGType32v *) REG_TOON_TABLE_6_ADDR) 411 412 /* TOON_TABLE_6_L */ 413 414 #define REG_TOON_TABLE_6_L_OFFSET 0x398 415 #define REG_TOON_TABLE_6_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_L_OFFSET) 416 #define reg_G3X_TOON_TABLE_6_L (*( REGType16v *) REG_TOON_TABLE_6_L_ADDR) 417 418 /* TOON_TABLE_6_H */ 419 420 #define REG_TOON_TABLE_6_H_OFFSET 0x39a 421 #define REG_TOON_TABLE_6_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_H_OFFSET) 422 #define reg_G3X_TOON_TABLE_6_H (*( REGType16v *) REG_TOON_TABLE_6_H_ADDR) 423 424 /* TOON_TABLE_7 */ 425 426 #define REG_TOON_TABLE_7_OFFSET 0x39c 427 #define REG_TOON_TABLE_7_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_OFFSET) 428 #define reg_G3X_TOON_TABLE_7 (*( REGType32v *) REG_TOON_TABLE_7_ADDR) 429 430 /* TOON_TABLE_7_L */ 431 432 #define REG_TOON_TABLE_7_L_OFFSET 0x39c 433 #define REG_TOON_TABLE_7_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_L_OFFSET) 434 #define reg_G3X_TOON_TABLE_7_L (*( REGType16v *) REG_TOON_TABLE_7_L_ADDR) 435 436 /* TOON_TABLE_7_H */ 437 438 #define REG_TOON_TABLE_7_H_OFFSET 0x39e 439 #define REG_TOON_TABLE_7_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_H_OFFSET) 440 #define reg_G3X_TOON_TABLE_7_H (*( REGType16v *) REG_TOON_TABLE_7_H_ADDR) 441 442 /* TOON_TABLE_8 */ 443 444 #define REG_TOON_TABLE_8_OFFSET 0x3a0 445 #define REG_TOON_TABLE_8_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_OFFSET) 446 #define reg_G3X_TOON_TABLE_8 (*( REGType32v *) REG_TOON_TABLE_8_ADDR) 447 448 /* TOON_TABLE_8_L */ 449 450 #define REG_TOON_TABLE_8_L_OFFSET 0x3a0 451 #define REG_TOON_TABLE_8_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_L_OFFSET) 452 #define reg_G3X_TOON_TABLE_8_L (*( REGType16v *) REG_TOON_TABLE_8_L_ADDR) 453 454 /* TOON_TABLE_8_H */ 455 456 #define REG_TOON_TABLE_8_H_OFFSET 0x3a2 457 #define REG_TOON_TABLE_8_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_H_OFFSET) 458 #define reg_G3X_TOON_TABLE_8_H (*( REGType16v *) REG_TOON_TABLE_8_H_ADDR) 459 460 /* TOON_TABLE_9 */ 461 462 #define REG_TOON_TABLE_9_OFFSET 0x3a4 463 #define REG_TOON_TABLE_9_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_OFFSET) 464 #define reg_G3X_TOON_TABLE_9 (*( REGType32v *) REG_TOON_TABLE_9_ADDR) 465 466 /* TOON_TABLE_9_L */ 467 468 #define REG_TOON_TABLE_9_L_OFFSET 0x3a4 469 #define REG_TOON_TABLE_9_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_L_OFFSET) 470 #define reg_G3X_TOON_TABLE_9_L (*( REGType16v *) REG_TOON_TABLE_9_L_ADDR) 471 472 /* TOON_TABLE_9_H */ 473 474 #define REG_TOON_TABLE_9_H_OFFSET 0x3a6 475 #define REG_TOON_TABLE_9_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_H_OFFSET) 476 #define reg_G3X_TOON_TABLE_9_H (*( REGType16v *) REG_TOON_TABLE_9_H_ADDR) 477 478 /* TOON_TABLE_10 */ 479 480 #define REG_TOON_TABLE_10_OFFSET 0x3a8 481 #define REG_TOON_TABLE_10_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_OFFSET) 482 #define reg_G3X_TOON_TABLE_10 (*( REGType32v *) REG_TOON_TABLE_10_ADDR) 483 484 /* TOON_TABLE_10_L */ 485 486 #define REG_TOON_TABLE_10_L_OFFSET 0x3a8 487 #define REG_TOON_TABLE_10_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_L_OFFSET) 488 #define reg_G3X_TOON_TABLE_10_L (*( REGType16v *) REG_TOON_TABLE_10_L_ADDR) 489 490 /* TOON_TABLE_10_H */ 491 492 #define REG_TOON_TABLE_10_H_OFFSET 0x3aa 493 #define REG_TOON_TABLE_10_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_H_OFFSET) 494 #define reg_G3X_TOON_TABLE_10_H (*( REGType16v *) REG_TOON_TABLE_10_H_ADDR) 495 496 /* TOON_TABLE_11 */ 497 498 #define REG_TOON_TABLE_11_OFFSET 0x3ac 499 #define REG_TOON_TABLE_11_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_OFFSET) 500 #define reg_G3X_TOON_TABLE_11 (*( REGType32v *) REG_TOON_TABLE_11_ADDR) 501 502 /* TOON_TABLE_11_L */ 503 504 #define REG_TOON_TABLE_11_L_OFFSET 0x3ac 505 #define REG_TOON_TABLE_11_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_L_OFFSET) 506 #define reg_G3X_TOON_TABLE_11_L (*( REGType16v *) REG_TOON_TABLE_11_L_ADDR) 507 508 /* TOON_TABLE_11_H */ 509 510 #define REG_TOON_TABLE_11_H_OFFSET 0x3ae 511 #define REG_TOON_TABLE_11_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_H_OFFSET) 512 #define reg_G3X_TOON_TABLE_11_H (*( REGType16v *) REG_TOON_TABLE_11_H_ADDR) 513 514 /* TOON_TABLE_12 */ 515 516 #define REG_TOON_TABLE_12_OFFSET 0x3b0 517 #define REG_TOON_TABLE_12_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_OFFSET) 518 #define reg_G3X_TOON_TABLE_12 (*( REGType32v *) REG_TOON_TABLE_12_ADDR) 519 520 /* TOON_TABLE_12_L */ 521 522 #define REG_TOON_TABLE_12_L_OFFSET 0x3b0 523 #define REG_TOON_TABLE_12_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_L_OFFSET) 524 #define reg_G3X_TOON_TABLE_12_L (*( REGType16v *) REG_TOON_TABLE_12_L_ADDR) 525 526 /* TOON_TABLE_12_H */ 527 528 #define REG_TOON_TABLE_12_H_OFFSET 0x3b2 529 #define REG_TOON_TABLE_12_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_H_OFFSET) 530 #define reg_G3X_TOON_TABLE_12_H (*( REGType16v *) REG_TOON_TABLE_12_H_ADDR) 531 532 /* TOON_TABLE_13 */ 533 534 #define REG_TOON_TABLE_13_OFFSET 0x3b4 535 #define REG_TOON_TABLE_13_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_OFFSET) 536 #define reg_G3X_TOON_TABLE_13 (*( REGType32v *) REG_TOON_TABLE_13_ADDR) 537 538 /* TOON_TABLE_13_L */ 539 540 #define REG_TOON_TABLE_13_L_OFFSET 0x3b4 541 #define REG_TOON_TABLE_13_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_L_OFFSET) 542 #define reg_G3X_TOON_TABLE_13_L (*( REGType16v *) REG_TOON_TABLE_13_L_ADDR) 543 544 /* TOON_TABLE_13_H */ 545 546 #define REG_TOON_TABLE_13_H_OFFSET 0x3b6 547 #define REG_TOON_TABLE_13_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_H_OFFSET) 548 #define reg_G3X_TOON_TABLE_13_H (*( REGType16v *) REG_TOON_TABLE_13_H_ADDR) 549 550 /* TOON_TABLE_14 */ 551 552 #define REG_TOON_TABLE_14_OFFSET 0x3b8 553 #define REG_TOON_TABLE_14_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_OFFSET) 554 #define reg_G3X_TOON_TABLE_14 (*( REGType32v *) REG_TOON_TABLE_14_ADDR) 555 556 /* TOON_TABLE_14_L */ 557 558 #define REG_TOON_TABLE_14_L_OFFSET 0x3b8 559 #define REG_TOON_TABLE_14_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_L_OFFSET) 560 #define reg_G3X_TOON_TABLE_14_L (*( REGType16v *) REG_TOON_TABLE_14_L_ADDR) 561 562 /* TOON_TABLE_14_H */ 563 564 #define REG_TOON_TABLE_14_H_OFFSET 0x3ba 565 #define REG_TOON_TABLE_14_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_H_OFFSET) 566 #define reg_G3X_TOON_TABLE_14_H (*( REGType16v *) REG_TOON_TABLE_14_H_ADDR) 567 568 /* TOON_TABLE_15 */ 569 570 #define REG_TOON_TABLE_15_OFFSET 0x3bc 571 #define REG_TOON_TABLE_15_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_OFFSET) 572 #define reg_G3X_TOON_TABLE_15 (*( REGType32v *) REG_TOON_TABLE_15_ADDR) 573 574 /* TOON_TABLE_15_L */ 575 576 #define REG_TOON_TABLE_15_L_OFFSET 0x3bc 577 #define REG_TOON_TABLE_15_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_L_OFFSET) 578 #define reg_G3X_TOON_TABLE_15_L (*( REGType16v *) REG_TOON_TABLE_15_L_ADDR) 579 580 /* TOON_TABLE_15_H */ 581 582 #define REG_TOON_TABLE_15_H_OFFSET 0x3be 583 #define REG_TOON_TABLE_15_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_H_OFFSET) 584 #define reg_G3X_TOON_TABLE_15_H (*( REGType16v *) REG_TOON_TABLE_15_H_ADDR) 585 586 /* GXFIFO */ 587 588 #define REG_GXFIFO_OFFSET 0x400 589 #define REG_GXFIFO_ADDR (HW_REG_BASE + REG_GXFIFO_OFFSET) 590 #define reg_G3X_GXFIFO (*( REGType32v *) REG_GXFIFO_ADDR) 591 592 /* GXSTAT */ 593 594 #define REG_GXSTAT_OFFSET 0x600 595 #define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET) 596 #define reg_G3X_GXSTAT (*( REGType32v *) REG_GXSTAT_ADDR) 597 598 /* LISTRAM_COUNT */ 599 600 #define REG_LISTRAM_COUNT_OFFSET 0x604 601 #define REG_LISTRAM_COUNT_ADDR (HW_REG_BASE + REG_LISTRAM_COUNT_OFFSET) 602 #define reg_G3X_LISTRAM_COUNT (*(const REGType16v *) REG_LISTRAM_COUNT_ADDR) 603 604 /* VTXRAM_COUNT */ 605 606 #define REG_VTXRAM_COUNT_OFFSET 0x606 607 #define REG_VTXRAM_COUNT_ADDR (HW_REG_BASE + REG_VTXRAM_COUNT_OFFSET) 608 #define reg_G3X_VTXRAM_COUNT (*(const REGType16v *) REG_VTXRAM_COUNT_ADDR) 609 610 /* DISP_1DOT_DEPTH */ 611 612 #define REG_DISP_1DOT_DEPTH_OFFSET 0x610 613 #define REG_DISP_1DOT_DEPTH_ADDR (HW_REG_BASE + REG_DISP_1DOT_DEPTH_OFFSET) 614 #define reg_G3X_DISP_1DOT_DEPTH (*( REGType16v *) REG_DISP_1DOT_DEPTH_ADDR) 615 616 /* POS_RESULT_X */ 617 618 #define REG_POS_RESULT_X_OFFSET 0x620 619 #define REG_POS_RESULT_X_ADDR (HW_REG_BASE + REG_POS_RESULT_X_OFFSET) 620 #define reg_G3X_POS_RESULT_X (*(const REGType32v *) REG_POS_RESULT_X_ADDR) 621 622 /* POS_RESULT_Y */ 623 624 #define REG_POS_RESULT_Y_OFFSET 0x624 625 #define REG_POS_RESULT_Y_ADDR (HW_REG_BASE + REG_POS_RESULT_Y_OFFSET) 626 #define reg_G3X_POS_RESULT_Y (*(const REGType32v *) REG_POS_RESULT_Y_ADDR) 627 628 /* POS_RESULT_Z */ 629 630 #define REG_POS_RESULT_Z_OFFSET 0x628 631 #define REG_POS_RESULT_Z_ADDR (HW_REG_BASE + REG_POS_RESULT_Z_OFFSET) 632 #define reg_G3X_POS_RESULT_Z (*(const REGType32v *) REG_POS_RESULT_Z_ADDR) 633 634 /* POS_RESULT_W */ 635 636 #define REG_POS_RESULT_W_OFFSET 0x62c 637 #define REG_POS_RESULT_W_ADDR (HW_REG_BASE + REG_POS_RESULT_W_OFFSET) 638 #define reg_G3X_POS_RESULT_W (*(const REGType32v *) REG_POS_RESULT_W_ADDR) 639 640 /* VEC_RESULT_X */ 641 642 #define REG_VEC_RESULT_X_OFFSET 0x630 643 #define REG_VEC_RESULT_X_ADDR (HW_REG_BASE + REG_VEC_RESULT_X_OFFSET) 644 #define reg_G3X_VEC_RESULT_X (*(const REGType16v *) REG_VEC_RESULT_X_ADDR) 645 646 /* VEC_RESULT_Y */ 647 648 #define REG_VEC_RESULT_Y_OFFSET 0x632 649 #define REG_VEC_RESULT_Y_ADDR (HW_REG_BASE + REG_VEC_RESULT_Y_OFFSET) 650 #define reg_G3X_VEC_RESULT_Y (*(const REGType16v *) REG_VEC_RESULT_Y_ADDR) 651 652 /* VEC_RESULT_Z */ 653 654 #define REG_VEC_RESULT_Z_OFFSET 0x634 655 #define REG_VEC_RESULT_Z_ADDR (HW_REG_BASE + REG_VEC_RESULT_Z_OFFSET) 656 #define reg_G3X_VEC_RESULT_Z (*(const REGType16v *) REG_VEC_RESULT_Z_ADDR) 657 658 /* CLIPMTX_RESULT_0 */ 659 660 #define REG_CLIPMTX_RESULT_0_OFFSET 0x640 661 #define REG_CLIPMTX_RESULT_0_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_0_OFFSET) 662 #define reg_G3X_CLIPMTX_RESULT_0 (*(const REGType32v *) REG_CLIPMTX_RESULT_0_ADDR) 663 664 /* CLIPMTX_RESULT_1 */ 665 666 #define REG_CLIPMTX_RESULT_1_OFFSET 0x644 667 #define REG_CLIPMTX_RESULT_1_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_1_OFFSET) 668 #define reg_G3X_CLIPMTX_RESULT_1 (*(const REGType32v *) REG_CLIPMTX_RESULT_1_ADDR) 669 670 /* CLIPMTX_RESULT_2 */ 671 672 #define REG_CLIPMTX_RESULT_2_OFFSET 0x648 673 #define REG_CLIPMTX_RESULT_2_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_2_OFFSET) 674 #define reg_G3X_CLIPMTX_RESULT_2 (*(const REGType32v *) REG_CLIPMTX_RESULT_2_ADDR) 675 676 /* CLIPMTX_RESULT_3 */ 677 678 #define REG_CLIPMTX_RESULT_3_OFFSET 0x64c 679 #define REG_CLIPMTX_RESULT_3_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_3_OFFSET) 680 #define reg_G3X_CLIPMTX_RESULT_3 (*(const REGType32v *) REG_CLIPMTX_RESULT_3_ADDR) 681 682 /* CLIPMTX_RESULT_4 */ 683 684 #define REG_CLIPMTX_RESULT_4_OFFSET 0x650 685 #define REG_CLIPMTX_RESULT_4_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_4_OFFSET) 686 #define reg_G3X_CLIPMTX_RESULT_4 (*(const REGType32v *) REG_CLIPMTX_RESULT_4_ADDR) 687 688 /* CLIPMTX_RESULT_5 */ 689 690 #define REG_CLIPMTX_RESULT_5_OFFSET 0x654 691 #define REG_CLIPMTX_RESULT_5_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_5_OFFSET) 692 #define reg_G3X_CLIPMTX_RESULT_5 (*(const REGType32v *) REG_CLIPMTX_RESULT_5_ADDR) 693 694 /* CLIPMTX_RESULT_6 */ 695 696 #define REG_CLIPMTX_RESULT_6_OFFSET 0x658 697 #define REG_CLIPMTX_RESULT_6_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_6_OFFSET) 698 #define reg_G3X_CLIPMTX_RESULT_6 (*(const REGType32v *) REG_CLIPMTX_RESULT_6_ADDR) 699 700 /* CLIPMTX_RESULT_7 */ 701 702 #define REG_CLIPMTX_RESULT_7_OFFSET 0x65c 703 #define REG_CLIPMTX_RESULT_7_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_7_OFFSET) 704 #define reg_G3X_CLIPMTX_RESULT_7 (*(const REGType32v *) REG_CLIPMTX_RESULT_7_ADDR) 705 706 /* CLIPMTX_RESULT_8 */ 707 708 #define REG_CLIPMTX_RESULT_8_OFFSET 0x660 709 #define REG_CLIPMTX_RESULT_8_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_8_OFFSET) 710 #define reg_G3X_CLIPMTX_RESULT_8 (*(const REGType32v *) REG_CLIPMTX_RESULT_8_ADDR) 711 712 /* CLIPMTX_RESULT_9 */ 713 714 #define REG_CLIPMTX_RESULT_9_OFFSET 0x664 715 #define REG_CLIPMTX_RESULT_9_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_9_OFFSET) 716 #define reg_G3X_CLIPMTX_RESULT_9 (*(const REGType32v *) REG_CLIPMTX_RESULT_9_ADDR) 717 718 /* CLIPMTX_RESULT_10 */ 719 720 #define REG_CLIPMTX_RESULT_10_OFFSET 0x668 721 #define REG_CLIPMTX_RESULT_10_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_10_OFFSET) 722 #define reg_G3X_CLIPMTX_RESULT_10 (*(const REGType32v *) REG_CLIPMTX_RESULT_10_ADDR) 723 724 /* CLIPMTX_RESULT_11 */ 725 726 #define REG_CLIPMTX_RESULT_11_OFFSET 0x66c 727 #define REG_CLIPMTX_RESULT_11_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_11_OFFSET) 728 #define reg_G3X_CLIPMTX_RESULT_11 (*(const REGType32v *) REG_CLIPMTX_RESULT_11_ADDR) 729 730 /* CLIPMTX_RESULT_12 */ 731 732 #define REG_CLIPMTX_RESULT_12_OFFSET 0x670 733 #define REG_CLIPMTX_RESULT_12_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_12_OFFSET) 734 #define reg_G3X_CLIPMTX_RESULT_12 (*(const REGType32v *) REG_CLIPMTX_RESULT_12_ADDR) 735 736 /* CLIPMTX_RESULT_13 */ 737 738 #define REG_CLIPMTX_RESULT_13_OFFSET 0x674 739 #define REG_CLIPMTX_RESULT_13_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_13_OFFSET) 740 #define reg_G3X_CLIPMTX_RESULT_13 (*(const REGType32v *) REG_CLIPMTX_RESULT_13_ADDR) 741 742 /* CLIPMTX_RESULT_14 */ 743 744 #define REG_CLIPMTX_RESULT_14_OFFSET 0x678 745 #define REG_CLIPMTX_RESULT_14_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_14_OFFSET) 746 #define reg_G3X_CLIPMTX_RESULT_14 (*(const REGType32v *) REG_CLIPMTX_RESULT_14_ADDR) 747 748 /* CLIPMTX_RESULT_15 */ 749 750 #define REG_CLIPMTX_RESULT_15_OFFSET 0x67c 751 #define REG_CLIPMTX_RESULT_15_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_15_OFFSET) 752 #define reg_G3X_CLIPMTX_RESULT_15 (*(const REGType32v *) REG_CLIPMTX_RESULT_15_ADDR) 753 754 /* VECMTX_RESULT_0 */ 755 756 #define REG_VECMTX_RESULT_0_OFFSET 0x680 757 #define REG_VECMTX_RESULT_0_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_0_OFFSET) 758 #define reg_G3X_VECMTX_RESULT_0 (*(const REGType32v *) REG_VECMTX_RESULT_0_ADDR) 759 760 /* VECMTX_RESULT_1 */ 761 762 #define REG_VECMTX_RESULT_1_OFFSET 0x684 763 #define REG_VECMTX_RESULT_1_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_1_OFFSET) 764 #define reg_G3X_VECMTX_RESULT_1 (*(const REGType32v *) REG_VECMTX_RESULT_1_ADDR) 765 766 /* VECMTX_RESULT_2 */ 767 768 #define REG_VECMTX_RESULT_2_OFFSET 0x688 769 #define REG_VECMTX_RESULT_2_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_2_OFFSET) 770 #define reg_G3X_VECMTX_RESULT_2 (*(const REGType32v *) REG_VECMTX_RESULT_2_ADDR) 771 772 /* VECMTX_RESULT_3 */ 773 774 #define REG_VECMTX_RESULT_3_OFFSET 0x68c 775 #define REG_VECMTX_RESULT_3_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_3_OFFSET) 776 #define reg_G3X_VECMTX_RESULT_3 (*(const REGType32v *) REG_VECMTX_RESULT_3_ADDR) 777 778 /* VECMTX_RESULT_4 */ 779 780 #define REG_VECMTX_RESULT_4_OFFSET 0x690 781 #define REG_VECMTX_RESULT_4_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_4_OFFSET) 782 #define reg_G3X_VECMTX_RESULT_4 (*(const REGType32v *) REG_VECMTX_RESULT_4_ADDR) 783 784 /* VECMTX_RESULT_5 */ 785 786 #define REG_VECMTX_RESULT_5_OFFSET 0x694 787 #define REG_VECMTX_RESULT_5_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_5_OFFSET) 788 #define reg_G3X_VECMTX_RESULT_5 (*(const REGType32v *) REG_VECMTX_RESULT_5_ADDR) 789 790 /* VECMTX_RESULT_6 */ 791 792 #define REG_VECMTX_RESULT_6_OFFSET 0x698 793 #define REG_VECMTX_RESULT_6_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_6_OFFSET) 794 #define reg_G3X_VECMTX_RESULT_6 (*(const REGType32v *) REG_VECMTX_RESULT_6_ADDR) 795 796 /* VECMTX_RESULT_7 */ 797 798 #define REG_VECMTX_RESULT_7_OFFSET 0x69c 799 #define REG_VECMTX_RESULT_7_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_7_OFFSET) 800 #define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *) REG_VECMTX_RESULT_7_ADDR) 801 802 /* VECMTX_RESULT_8 */ 803 804 #define REG_VECMTX_RESULT_8_OFFSET 0x6a0 805 #define REG_VECMTX_RESULT_8_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_8_OFFSET) 806 #define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *) REG_VECMTX_RESULT_8_ADDR) 807 808 809 /* 810 * Definitions of Register fields 811 */ 812 813 814 /* DISP3DCNT */ 815 816 #define REG_G3X_DISP3DCNT_PRI_SHIFT 14 817 #define REG_G3X_DISP3DCNT_PRI_SIZE 1 818 #define REG_G3X_DISP3DCNT_PRI_MASK 0x4000 819 820 #define REG_G3X_DISP3DCNT_GO_SHIFT 13 821 #define REG_G3X_DISP3DCNT_GO_SIZE 1 822 #define REG_G3X_DISP3DCNT_GO_MASK 0x2000 823 824 #define REG_G3X_DISP3DCNT_RO_SHIFT 12 825 #define REG_G3X_DISP3DCNT_RO_SIZE 1 826 #define REG_G3X_DISP3DCNT_RO_MASK 0x1000 827 828 #define REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT 8 829 #define REG_G3X_DISP3DCNT_FOG_SHIFT_SIZE 4 830 #define REG_G3X_DISP3DCNT_FOG_SHIFT_MASK 0x0f00 831 832 #define REG_G3X_DISP3DCNT_FME_SHIFT 7 833 #define REG_G3X_DISP3DCNT_FME_SIZE 1 834 #define REG_G3X_DISP3DCNT_FME_MASK 0x0080 835 836 #define REG_G3X_DISP3DCNT_FMOD_SHIFT 6 837 #define REG_G3X_DISP3DCNT_FMOD_SIZE 1 838 #define REG_G3X_DISP3DCNT_FMOD_MASK 0x0040 839 840 #define REG_G3X_DISP3DCNT_EME_SHIFT 5 841 #define REG_G3X_DISP3DCNT_EME_SIZE 1 842 #define REG_G3X_DISP3DCNT_EME_MASK 0x0020 843 844 #define REG_G3X_DISP3DCNT_AAE_SHIFT 4 845 #define REG_G3X_DISP3DCNT_AAE_SIZE 1 846 #define REG_G3X_DISP3DCNT_AAE_MASK 0x0010 847 848 #define REG_G3X_DISP3DCNT_ABE_SHIFT 3 849 #define REG_G3X_DISP3DCNT_ABE_SIZE 1 850 #define REG_G3X_DISP3DCNT_ABE_MASK 0x0008 851 852 #define REG_G3X_DISP3DCNT_ATE_SHIFT 2 853 #define REG_G3X_DISP3DCNT_ATE_SIZE 1 854 #define REG_G3X_DISP3DCNT_ATE_MASK 0x0004 855 856 #define REG_G3X_DISP3DCNT_THS_SHIFT 1 857 #define REG_G3X_DISP3DCNT_THS_SIZE 1 858 #define REG_G3X_DISP3DCNT_THS_MASK 0x0002 859 860 #define REG_G3X_DISP3DCNT_TME_SHIFT 0 861 #define REG_G3X_DISP3DCNT_TME_SIZE 1 862 #define REG_G3X_DISP3DCNT_TME_MASK 0x0001 863 864 #ifndef SDK_ASM 865 #define REG_G3X_DISP3DCNT_FIELD( pri, go, ro, fog_shift, fme, fmod, eme, aae, abe, ate, ths, tme ) \ 866 (u16)( \ 867 ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \ 868 ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \ 869 ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \ 870 ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \ 871 ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \ 872 ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \ 873 ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \ 874 ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \ 875 ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \ 876 ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \ 877 ((u32)(ths) << REG_G3X_DISP3DCNT_THS_SHIFT) | \ 878 ((u32)(tme) << REG_G3X_DISP3DCNT_TME_SHIFT)) 879 #endif 880 881 882 /* RDLINES_COUNT */ 883 884 #define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT 0 885 #define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SIZE 6 886 #define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_MASK 0x003f 887 888 #ifndef SDK_ASM 889 #define REG_G3X_RDLINES_COUNT_FIELD( rendered_lines_min ) \ 890 (u16)( \ 891 ((u32)(rendered_lines_min) << REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT)) 892 #endif 893 894 895 /* EDGE_COLOR_0 */ 896 897 #define REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT 26 898 #define REG_G3X_EDGE_COLOR_0_BLUE1_SIZE 5 899 #define REG_G3X_EDGE_COLOR_0_BLUE1_MASK 0x7c000000 900 901 #define REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT 21 902 #define REG_G3X_EDGE_COLOR_0_GREEN1_SIZE 5 903 #define REG_G3X_EDGE_COLOR_0_GREEN1_MASK 0x03e00000 904 905 #define REG_G3X_EDGE_COLOR_0_RED1_SHIFT 16 906 #define REG_G3X_EDGE_COLOR_0_RED1_SIZE 5 907 #define REG_G3X_EDGE_COLOR_0_RED1_MASK 0x001f0000 908 909 #define REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT 10 910 #define REG_G3X_EDGE_COLOR_0_BLUE0_SIZE 5 911 #define REG_G3X_EDGE_COLOR_0_BLUE0_MASK 0x00007c00 912 913 #define REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT 5 914 #define REG_G3X_EDGE_COLOR_0_GREEN0_SIZE 5 915 #define REG_G3X_EDGE_COLOR_0_GREEN0_MASK 0x000003e0 916 917 #define REG_G3X_EDGE_COLOR_0_RED0_SHIFT 0 918 #define REG_G3X_EDGE_COLOR_0_RED0_SIZE 5 919 #define REG_G3X_EDGE_COLOR_0_RED0_MASK 0x0000001f 920 921 #ifndef SDK_ASM 922 #define REG_G3X_EDGE_COLOR_0_FIELD( blue1, green1, red1, blue0, green0, red0 ) \ 923 (u32)( \ 924 ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT) | \ 925 ((u32)(green1) << REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT) | \ 926 ((u32)(red1) << REG_G3X_EDGE_COLOR_0_RED1_SHIFT) | \ 927 ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT) | \ 928 ((u32)(green0) << REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT) | \ 929 ((u32)(red0) << REG_G3X_EDGE_COLOR_0_RED0_SHIFT)) 930 #endif 931 932 933 /* EDGE_COLOR_0_L */ 934 935 #define REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT 10 936 #define REG_G3X_EDGE_COLOR_0_L_BLUE0_SIZE 5 937 #define REG_G3X_EDGE_COLOR_0_L_BLUE0_MASK 0x7c00 938 939 #define REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT 5 940 #define REG_G3X_EDGE_COLOR_0_L_GREEN0_SIZE 5 941 #define REG_G3X_EDGE_COLOR_0_L_GREEN0_MASK 0x03e0 942 943 #define REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT 0 944 #define REG_G3X_EDGE_COLOR_0_L_RED0_SIZE 5 945 #define REG_G3X_EDGE_COLOR_0_L_RED0_MASK 0x001f 946 947 #ifndef SDK_ASM 948 #define REG_G3X_EDGE_COLOR_0_L_FIELD( blue0, green0, red0 ) \ 949 (u16)( \ 950 ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT) | \ 951 ((u32)(green0) << REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT) | \ 952 ((u32)(red0) << REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT)) 953 #endif 954 955 956 /* EDGE_COLOR_0_H */ 957 958 #define REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT 10 959 #define REG_G3X_EDGE_COLOR_0_H_BLUE1_SIZE 5 960 #define REG_G3X_EDGE_COLOR_0_H_BLUE1_MASK 0x7c00 961 962 #define REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT 5 963 #define REG_G3X_EDGE_COLOR_0_H_GREEN1_SIZE 5 964 #define REG_G3X_EDGE_COLOR_0_H_GREEN1_MASK 0x03e0 965 966 #define REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT 0 967 #define REG_G3X_EDGE_COLOR_0_H_RED1_SIZE 5 968 #define REG_G3X_EDGE_COLOR_0_H_RED1_MASK 0x001f 969 970 #ifndef SDK_ASM 971 #define REG_G3X_EDGE_COLOR_0_H_FIELD( blue1, green1, red1 ) \ 972 (u16)( \ 973 ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT) | \ 974 ((u32)(green1) << REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT) | \ 975 ((u32)(red1) << REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT)) 976 #endif 977 978 979 /* EDGE_COLOR_1 */ 980 981 #define REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT 26 982 #define REG_G3X_EDGE_COLOR_1_BLUE3_SIZE 5 983 #define REG_G3X_EDGE_COLOR_1_BLUE3_MASK 0x7c000000 984 985 #define REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT 21 986 #define REG_G3X_EDGE_COLOR_1_GREEN3_SIZE 5 987 #define REG_G3X_EDGE_COLOR_1_GREEN3_MASK 0x03e00000 988 989 #define REG_G3X_EDGE_COLOR_1_RED3_SHIFT 16 990 #define REG_G3X_EDGE_COLOR_1_RED3_SIZE 5 991 #define REG_G3X_EDGE_COLOR_1_RED3_MASK 0x001f0000 992 993 #define REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT 10 994 #define REG_G3X_EDGE_COLOR_1_BLUE2_SIZE 5 995 #define REG_G3X_EDGE_COLOR_1_BLUE2_MASK 0x00007c00 996 997 #define REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT 5 998 #define REG_G3X_EDGE_COLOR_1_GREEN2_SIZE 5 999 #define REG_G3X_EDGE_COLOR_1_GREEN2_MASK 0x000003e0 1000 1001 #define REG_G3X_EDGE_COLOR_1_RED2_SHIFT 0 1002 #define REG_G3X_EDGE_COLOR_1_RED2_SIZE 5 1003 #define REG_G3X_EDGE_COLOR_1_RED2_MASK 0x0000001f 1004 1005 #ifndef SDK_ASM 1006 #define REG_G3X_EDGE_COLOR_1_FIELD( blue3, green3, red3, blue2, green2, red2 ) \ 1007 (u32)( \ 1008 ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT) | \ 1009 ((u32)(green3) << REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT) | \ 1010 ((u32)(red3) << REG_G3X_EDGE_COLOR_1_RED3_SHIFT) | \ 1011 ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT) | \ 1012 ((u32)(green2) << REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT) | \ 1013 ((u32)(red2) << REG_G3X_EDGE_COLOR_1_RED2_SHIFT)) 1014 #endif 1015 1016 1017 /* EDGE_COLOR_1_L */ 1018 1019 #define REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT 10 1020 #define REG_G3X_EDGE_COLOR_1_L_BLUE2_SIZE 5 1021 #define REG_G3X_EDGE_COLOR_1_L_BLUE2_MASK 0x7c00 1022 1023 #define REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT 5 1024 #define REG_G3X_EDGE_COLOR_1_L_GREEN2_SIZE 5 1025 #define REG_G3X_EDGE_COLOR_1_L_GREEN2_MASK 0x03e0 1026 1027 #define REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT 0 1028 #define REG_G3X_EDGE_COLOR_1_L_RED2_SIZE 5 1029 #define REG_G3X_EDGE_COLOR_1_L_RED2_MASK 0x001f 1030 1031 #ifndef SDK_ASM 1032 #define REG_G3X_EDGE_COLOR_1_L_FIELD( blue2, green2, red2 ) \ 1033 (u16)( \ 1034 ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT) | \ 1035 ((u32)(green2) << REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT) | \ 1036 ((u32)(red2) << REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT)) 1037 #endif 1038 1039 1040 /* EDGE_COLOR_1_H */ 1041 1042 #define REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT 10 1043 #define REG_G3X_EDGE_COLOR_1_H_BLUE3_SIZE 5 1044 #define REG_G3X_EDGE_COLOR_1_H_BLUE3_MASK 0x7c00 1045 1046 #define REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT 5 1047 #define REG_G3X_EDGE_COLOR_1_H_GREEN3_SIZE 5 1048 #define REG_G3X_EDGE_COLOR_1_H_GREEN3_MASK 0x03e0 1049 1050 #define REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT 0 1051 #define REG_G3X_EDGE_COLOR_1_H_RED3_SIZE 5 1052 #define REG_G3X_EDGE_COLOR_1_H_RED3_MASK 0x001f 1053 1054 #ifndef SDK_ASM 1055 #define REG_G3X_EDGE_COLOR_1_H_FIELD( blue3, green3, red3 ) \ 1056 (u16)( \ 1057 ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT) | \ 1058 ((u32)(green3) << REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT) | \ 1059 ((u32)(red3) << REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT)) 1060 #endif 1061 1062 1063 /* EDGE_COLOR_2 */ 1064 1065 #define REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT 26 1066 #define REG_G3X_EDGE_COLOR_2_BLUE5_SIZE 5 1067 #define REG_G3X_EDGE_COLOR_2_BLUE5_MASK 0x7c000000 1068 1069 #define REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT 21 1070 #define REG_G3X_EDGE_COLOR_2_GREEN5_SIZE 5 1071 #define REG_G3X_EDGE_COLOR_2_GREEN5_MASK 0x03e00000 1072 1073 #define REG_G3X_EDGE_COLOR_2_RED5_SHIFT 16 1074 #define REG_G3X_EDGE_COLOR_2_RED5_SIZE 5 1075 #define REG_G3X_EDGE_COLOR_2_RED5_MASK 0x001f0000 1076 1077 #define REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT 10 1078 #define REG_G3X_EDGE_COLOR_2_BLUE4_SIZE 5 1079 #define REG_G3X_EDGE_COLOR_2_BLUE4_MASK 0x00007c00 1080 1081 #define REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT 5 1082 #define REG_G3X_EDGE_COLOR_2_GREEN4_SIZE 5 1083 #define REG_G3X_EDGE_COLOR_2_GREEN4_MASK 0x000003e0 1084 1085 #define REG_G3X_EDGE_COLOR_2_RED4_SHIFT 0 1086 #define REG_G3X_EDGE_COLOR_2_RED4_SIZE 5 1087 #define REG_G3X_EDGE_COLOR_2_RED4_MASK 0x0000001f 1088 1089 #ifndef SDK_ASM 1090 #define REG_G3X_EDGE_COLOR_2_FIELD( blue5, green5, red5, blue4, green4, red4 ) \ 1091 (u32)( \ 1092 ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT) | \ 1093 ((u32)(green5) << REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT) | \ 1094 ((u32)(red5) << REG_G3X_EDGE_COLOR_2_RED5_SHIFT) | \ 1095 ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT) | \ 1096 ((u32)(green4) << REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT) | \ 1097 ((u32)(red4) << REG_G3X_EDGE_COLOR_2_RED4_SHIFT)) 1098 #endif 1099 1100 1101 /* EDGE_COLOR_2_L */ 1102 1103 #define REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT 10 1104 #define REG_G3X_EDGE_COLOR_2_L_BLUE4_SIZE 5 1105 #define REG_G3X_EDGE_COLOR_2_L_BLUE4_MASK 0x7c00 1106 1107 #define REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT 5 1108 #define REG_G3X_EDGE_COLOR_2_L_GREEN4_SIZE 5 1109 #define REG_G3X_EDGE_COLOR_2_L_GREEN4_MASK 0x03e0 1110 1111 #define REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT 0 1112 #define REG_G3X_EDGE_COLOR_2_L_RED4_SIZE 5 1113 #define REG_G3X_EDGE_COLOR_2_L_RED4_MASK 0x001f 1114 1115 #ifndef SDK_ASM 1116 #define REG_G3X_EDGE_COLOR_2_L_FIELD( blue4, green4, red4 ) \ 1117 (u16)( \ 1118 ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT) | \ 1119 ((u32)(green4) << REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT) | \ 1120 ((u32)(red4) << REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT)) 1121 #endif 1122 1123 1124 /* EDGE_COLOR_2_H */ 1125 1126 #define REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT 10 1127 #define REG_G3X_EDGE_COLOR_2_H_BLUE5_SIZE 5 1128 #define REG_G3X_EDGE_COLOR_2_H_BLUE5_MASK 0x7c00 1129 1130 #define REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT 5 1131 #define REG_G3X_EDGE_COLOR_2_H_GREEN5_SIZE 5 1132 #define REG_G3X_EDGE_COLOR_2_H_GREEN5_MASK 0x03e0 1133 1134 #define REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT 0 1135 #define REG_G3X_EDGE_COLOR_2_H_RED5_SIZE 5 1136 #define REG_G3X_EDGE_COLOR_2_H_RED5_MASK 0x001f 1137 1138 #ifndef SDK_ASM 1139 #define REG_G3X_EDGE_COLOR_2_H_FIELD( blue5, green5, red5 ) \ 1140 (u16)( \ 1141 ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT) | \ 1142 ((u32)(green5) << REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT) | \ 1143 ((u32)(red5) << REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT)) 1144 #endif 1145 1146 1147 /* EDGE_COLOR_3 */ 1148 1149 #define REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT 26 1150 #define REG_G3X_EDGE_COLOR_3_BLUE7_SIZE 5 1151 #define REG_G3X_EDGE_COLOR_3_BLUE7_MASK 0x7c000000 1152 1153 #define REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT 21 1154 #define REG_G3X_EDGE_COLOR_3_GREEN7_SIZE 5 1155 #define REG_G3X_EDGE_COLOR_3_GREEN7_MASK 0x03e00000 1156 1157 #define REG_G3X_EDGE_COLOR_3_RED7_SHIFT 16 1158 #define REG_G3X_EDGE_COLOR_3_RED7_SIZE 5 1159 #define REG_G3X_EDGE_COLOR_3_RED7_MASK 0x001f0000 1160 1161 #define REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT 10 1162 #define REG_G3X_EDGE_COLOR_3_BLUE6_SIZE 5 1163 #define REG_G3X_EDGE_COLOR_3_BLUE6_MASK 0x00007c00 1164 1165 #define REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT 5 1166 #define REG_G3X_EDGE_COLOR_3_GREEN6_SIZE 5 1167 #define REG_G3X_EDGE_COLOR_3_GREEN6_MASK 0x000003e0 1168 1169 #define REG_G3X_EDGE_COLOR_3_RED6_SHIFT 0 1170 #define REG_G3X_EDGE_COLOR_3_RED6_SIZE 5 1171 #define REG_G3X_EDGE_COLOR_3_RED6_MASK 0x0000001f 1172 1173 #ifndef SDK_ASM 1174 #define REG_G3X_EDGE_COLOR_3_FIELD( blue7, green7, red7, blue6, green6, red6 ) \ 1175 (u32)( \ 1176 ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT) | \ 1177 ((u32)(green7) << REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT) | \ 1178 ((u32)(red7) << REG_G3X_EDGE_COLOR_3_RED7_SHIFT) | \ 1179 ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT) | \ 1180 ((u32)(green6) << REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT) | \ 1181 ((u32)(red6) << REG_G3X_EDGE_COLOR_3_RED6_SHIFT)) 1182 #endif 1183 1184 1185 /* EDGE_COLOR_3_L */ 1186 1187 #define REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT 10 1188 #define REG_G3X_EDGE_COLOR_3_L_BLUE6_SIZE 5 1189 #define REG_G3X_EDGE_COLOR_3_L_BLUE6_MASK 0x7c00 1190 1191 #define REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT 5 1192 #define REG_G3X_EDGE_COLOR_3_L_GREEN6_SIZE 5 1193 #define REG_G3X_EDGE_COLOR_3_L_GREEN6_MASK 0x03e0 1194 1195 #define REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT 0 1196 #define REG_G3X_EDGE_COLOR_3_L_RED6_SIZE 5 1197 #define REG_G3X_EDGE_COLOR_3_L_RED6_MASK 0x001f 1198 1199 #ifndef SDK_ASM 1200 #define REG_G3X_EDGE_COLOR_3_L_FIELD( blue6, green6, red6 ) \ 1201 (u16)( \ 1202 ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT) | \ 1203 ((u32)(green6) << REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT) | \ 1204 ((u32)(red6) << REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT)) 1205 #endif 1206 1207 1208 /* EDGE_COLOR_3_H */ 1209 1210 #define REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT 10 1211 #define REG_G3X_EDGE_COLOR_3_H_BLUE7_SIZE 5 1212 #define REG_G3X_EDGE_COLOR_3_H_BLUE7_MASK 0x7c00 1213 1214 #define REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT 5 1215 #define REG_G3X_EDGE_COLOR_3_H_GREEN7_SIZE 5 1216 #define REG_G3X_EDGE_COLOR_3_H_GREEN7_MASK 0x03e0 1217 1218 #define REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT 0 1219 #define REG_G3X_EDGE_COLOR_3_H_RED7_SIZE 5 1220 #define REG_G3X_EDGE_COLOR_3_H_RED7_MASK 0x001f 1221 1222 #ifndef SDK_ASM 1223 #define REG_G3X_EDGE_COLOR_3_H_FIELD( blue7, green7, red7 ) \ 1224 (u16)( \ 1225 ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT) | \ 1226 ((u32)(green7) << REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT) | \ 1227 ((u32)(red7) << REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT)) 1228 #endif 1229 1230 1231 /* ALPHA_TEST_REF */ 1232 1233 #define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT 0 1234 #define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SIZE 5 1235 #define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_MASK 0x001f 1236 1237 #ifndef SDK_ASM 1238 #define REG_G3X_ALPHA_TEST_REF_FIELD( alpha_reference ) \ 1239 (u16)( \ 1240 ((u32)(alpha_reference) << REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT)) 1241 #endif 1242 1243 1244 /* CLEAR_COLOR */ 1245 1246 #define REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT 24 1247 #define REG_G3X_CLEAR_COLOR_POLYGONID_SIZE 6 1248 #define REG_G3X_CLEAR_COLOR_POLYGONID_MASK 0x3f000000 1249 1250 #define REG_G3X_CLEAR_COLOR_ALPHA_SHIFT 16 1251 #define REG_G3X_CLEAR_COLOR_ALPHA_SIZE 5 1252 #define REG_G3X_CLEAR_COLOR_ALPHA_MASK 0x001f0000 1253 1254 #define REG_G3X_CLEAR_COLOR_F_SHIFT 15 1255 #define REG_G3X_CLEAR_COLOR_F_SIZE 1 1256 #define REG_G3X_CLEAR_COLOR_F_MASK 0x00008000 1257 1258 #define REG_G3X_CLEAR_COLOR_BLUE_SHIFT 10 1259 #define REG_G3X_CLEAR_COLOR_BLUE_SIZE 5 1260 #define REG_G3X_CLEAR_COLOR_BLUE_MASK 0x00007c00 1261 1262 #define REG_G3X_CLEAR_COLOR_GREEN_SHIFT 5 1263 #define REG_G3X_CLEAR_COLOR_GREEN_SIZE 5 1264 #define REG_G3X_CLEAR_COLOR_GREEN_MASK 0x000003e0 1265 1266 #define REG_G3X_CLEAR_COLOR_RED_SHIFT 0 1267 #define REG_G3X_CLEAR_COLOR_RED_SIZE 5 1268 #define REG_G3X_CLEAR_COLOR_RED_MASK 0x0000001f 1269 1270 #ifndef SDK_ASM 1271 #define REG_G3X_CLEAR_COLOR_FIELD( polygonid, alpha, f, blue, green, red ) \ 1272 (u32)( \ 1273 ((u32)(polygonid) << REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT) | \ 1274 ((u32)(alpha) << REG_G3X_CLEAR_COLOR_ALPHA_SHIFT) | \ 1275 ((u32)(f) << REG_G3X_CLEAR_COLOR_F_SHIFT) | \ 1276 ((u32)(blue) << REG_G3X_CLEAR_COLOR_BLUE_SHIFT) | \ 1277 ((u32)(green) << REG_G3X_CLEAR_COLOR_GREEN_SHIFT) | \ 1278 ((u32)(red) << REG_G3X_CLEAR_COLOR_RED_SHIFT)) 1279 #endif 1280 1281 1282 /* CLEAR_DEPTH */ 1283 1284 #define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT 0 1285 #define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SIZE 15 1286 #define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_MASK 0x7fff 1287 1288 #ifndef SDK_ASM 1289 #define REG_G3X_CLEAR_DEPTH_FIELD( cleardepth ) \ 1290 (u16)( \ 1291 ((u32)(cleardepth) << REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT)) 1292 #endif 1293 1294 1295 /* CLRIMAGE_OFFSET */ 1296 1297 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT 8 1298 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SIZE 8 1299 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_MASK 0xff00 1300 1301 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT 0 1302 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SIZE 8 1303 #define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_MASK 0x00ff 1304 1305 #ifndef SDK_ASM 1306 #define REG_G3X_CLRIMAGE_OFFSET_FIELD( offsety, offsetx ) \ 1307 (u16)( \ 1308 ((u32)(offsety) << REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT) | \ 1309 ((u32)(offsetx) << REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT)) 1310 #endif 1311 1312 1313 /* FOG_COLOR */ 1314 1315 #define REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT 16 1316 #define REG_G3X_FOG_COLOR_FOG_ALPHA_SIZE 5 1317 #define REG_G3X_FOG_COLOR_FOG_ALPHA_MASK 0x001f0000 1318 1319 #define REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT 10 1320 #define REG_G3X_FOG_COLOR_FOG_BLUE_SIZE 5 1321 #define REG_G3X_FOG_COLOR_FOG_BLUE_MASK 0x00007c00 1322 1323 #define REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT 5 1324 #define REG_G3X_FOG_COLOR_FOG_GREEN_SIZE 5 1325 #define REG_G3X_FOG_COLOR_FOG_GREEN_MASK 0x000003e0 1326 1327 #define REG_G3X_FOG_COLOR_FOG_RED_SHIFT 0 1328 #define REG_G3X_FOG_COLOR_FOG_RED_SIZE 5 1329 #define REG_G3X_FOG_COLOR_FOG_RED_MASK 0x0000001f 1330 1331 #ifndef SDK_ASM 1332 #define REG_G3X_FOG_COLOR_FIELD( fog_alpha, fog_blue, fog_green, fog_red ) \ 1333 (u32)( \ 1334 ((u32)(fog_alpha) << REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT) | \ 1335 ((u32)(fog_blue) << REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT) | \ 1336 ((u32)(fog_green) << REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT) | \ 1337 ((u32)(fog_red) << REG_G3X_FOG_COLOR_FOG_RED_SHIFT)) 1338 #endif 1339 1340 1341 /* FOG_OFFSET */ 1342 1343 #define REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT 0 1344 #define REG_G3X_FOG_OFFSET_FOG_OFFSET_SIZE 15 1345 #define REG_G3X_FOG_OFFSET_FOG_OFFSET_MASK 0x7fff 1346 1347 #ifndef SDK_ASM 1348 #define REG_G3X_FOG_OFFSET_FIELD( fog_offset ) \ 1349 (u16)( \ 1350 ((u32)(fog_offset) << REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT)) 1351 #endif 1352 1353 1354 /* FOG_TABLE_0 */ 1355 1356 #define REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT 24 1357 #define REG_G3X_FOG_TABLE_0_DENSITY3_SIZE 7 1358 #define REG_G3X_FOG_TABLE_0_DENSITY3_MASK 0x7f000000 1359 1360 #define REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT 16 1361 #define REG_G3X_FOG_TABLE_0_DENSITY2_SIZE 7 1362 #define REG_G3X_FOG_TABLE_0_DENSITY2_MASK 0x007f0000 1363 1364 #define REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT 8 1365 #define REG_G3X_FOG_TABLE_0_DENSITY1_SIZE 7 1366 #define REG_G3X_FOG_TABLE_0_DENSITY1_MASK 0x00007f00 1367 1368 #define REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT 0 1369 #define REG_G3X_FOG_TABLE_0_DENSITY0_SIZE 7 1370 #define REG_G3X_FOG_TABLE_0_DENSITY0_MASK 0x0000007f 1371 1372 #ifndef SDK_ASM 1373 #define REG_G3X_FOG_TABLE_0_FIELD( density3, density2, density1, density0 ) \ 1374 (u32)( \ 1375 ((u32)(density3) << REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT) | \ 1376 ((u32)(density2) << REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT) | \ 1377 ((u32)(density1) << REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT) | \ 1378 ((u32)(density0) << REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT)) 1379 #endif 1380 1381 1382 /* FOG_TABLE_0_L */ 1383 1384 #define REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT 8 1385 #define REG_G3X_FOG_TABLE_0_L_DENSITY1_SIZE 7 1386 #define REG_G3X_FOG_TABLE_0_L_DENSITY1_MASK 0x7f00 1387 1388 #define REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT 0 1389 #define REG_G3X_FOG_TABLE_0_L_DENSITY0_SIZE 7 1390 #define REG_G3X_FOG_TABLE_0_L_DENSITY0_MASK 0x007f 1391 1392 #ifndef SDK_ASM 1393 #define REG_G3X_FOG_TABLE_0_L_FIELD( density1, density0 ) \ 1394 (u16)( \ 1395 ((u32)(density1) << REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT) | \ 1396 ((u32)(density0) << REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT)) 1397 #endif 1398 1399 1400 /* FOG_TABLE_0_H */ 1401 1402 #define REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT 8 1403 #define REG_G3X_FOG_TABLE_0_H_DENSITY3_SIZE 7 1404 #define REG_G3X_FOG_TABLE_0_H_DENSITY3_MASK 0x7f00 1405 1406 #define REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT 0 1407 #define REG_G3X_FOG_TABLE_0_H_DENSITY2_SIZE 7 1408 #define REG_G3X_FOG_TABLE_0_H_DENSITY2_MASK 0x007f 1409 1410 #ifndef SDK_ASM 1411 #define REG_G3X_FOG_TABLE_0_H_FIELD( density3, density2 ) \ 1412 (u16)( \ 1413 ((u32)(density3) << REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT) | \ 1414 ((u32)(density2) << REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT)) 1415 #endif 1416 1417 1418 /* FOG_TABLE_1 */ 1419 1420 #define REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT 24 1421 #define REG_G3X_FOG_TABLE_1_DENSITY7_SIZE 7 1422 #define REG_G3X_FOG_TABLE_1_DENSITY7_MASK 0x7f000000 1423 1424 #define REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT 16 1425 #define REG_G3X_FOG_TABLE_1_DENSITY6_SIZE 7 1426 #define REG_G3X_FOG_TABLE_1_DENSITY6_MASK 0x007f0000 1427 1428 #define REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT 8 1429 #define REG_G3X_FOG_TABLE_1_DENSITY5_SIZE 7 1430 #define REG_G3X_FOG_TABLE_1_DENSITY5_MASK 0x00007f00 1431 1432 #define REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT 0 1433 #define REG_G3X_FOG_TABLE_1_DENSITY4_SIZE 7 1434 #define REG_G3X_FOG_TABLE_1_DENSITY4_MASK 0x0000007f 1435 1436 #ifndef SDK_ASM 1437 #define REG_G3X_FOG_TABLE_1_FIELD( density7, density6, density5, density4 ) \ 1438 (u32)( \ 1439 ((u32)(density7) << REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT) | \ 1440 ((u32)(density6) << REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT) | \ 1441 ((u32)(density5) << REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT) | \ 1442 ((u32)(density4) << REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT)) 1443 #endif 1444 1445 1446 /* FOG_TABLE_1_L */ 1447 1448 #define REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT 8 1449 #define REG_G3X_FOG_TABLE_1_L_DENSITY5_SIZE 7 1450 #define REG_G3X_FOG_TABLE_1_L_DENSITY5_MASK 0x7f00 1451 1452 #define REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT 0 1453 #define REG_G3X_FOG_TABLE_1_L_DENSITY4_SIZE 7 1454 #define REG_G3X_FOG_TABLE_1_L_DENSITY4_MASK 0x007f 1455 1456 #ifndef SDK_ASM 1457 #define REG_G3X_FOG_TABLE_1_L_FIELD( density5, density4 ) \ 1458 (u16)( \ 1459 ((u32)(density5) << REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT) | \ 1460 ((u32)(density4) << REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT)) 1461 #endif 1462 1463 1464 /* FOG_TABLE_1_H */ 1465 1466 #define REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT 8 1467 #define REG_G3X_FOG_TABLE_1_H_DENSITY7_SIZE 7 1468 #define REG_G3X_FOG_TABLE_1_H_DENSITY7_MASK 0x7f00 1469 1470 #define REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT 0 1471 #define REG_G3X_FOG_TABLE_1_H_DENSITY6_SIZE 7 1472 #define REG_G3X_FOG_TABLE_1_H_DENSITY6_MASK 0x007f 1473 1474 #ifndef SDK_ASM 1475 #define REG_G3X_FOG_TABLE_1_H_FIELD( density7, density6 ) \ 1476 (u16)( \ 1477 ((u32)(density7) << REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT) | \ 1478 ((u32)(density6) << REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT)) 1479 #endif 1480 1481 1482 /* FOG_TABLE_2 */ 1483 1484 #define REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT 24 1485 #define REG_G3X_FOG_TABLE_2_DENSITY11_SIZE 7 1486 #define REG_G3X_FOG_TABLE_2_DENSITY11_MASK 0x7f000000 1487 1488 #define REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT 16 1489 #define REG_G3X_FOG_TABLE_2_DENSITY10_SIZE 7 1490 #define REG_G3X_FOG_TABLE_2_DENSITY10_MASK 0x007f0000 1491 1492 #define REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT 8 1493 #define REG_G3X_FOG_TABLE_2_DENSITY9_SIZE 7 1494 #define REG_G3X_FOG_TABLE_2_DENSITY9_MASK 0x00007f00 1495 1496 #define REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT 0 1497 #define REG_G3X_FOG_TABLE_2_DENSITY8_SIZE 7 1498 #define REG_G3X_FOG_TABLE_2_DENSITY8_MASK 0x0000007f 1499 1500 #ifndef SDK_ASM 1501 #define REG_G3X_FOG_TABLE_2_FIELD( density11, density10, density9, density8 ) \ 1502 (u32)( \ 1503 ((u32)(density11) << REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT) | \ 1504 ((u32)(density10) << REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT) | \ 1505 ((u32)(density9) << REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT) | \ 1506 ((u32)(density8) << REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT)) 1507 #endif 1508 1509 1510 /* FOG_TABLE_2_L */ 1511 1512 #define REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT 8 1513 #define REG_G3X_FOG_TABLE_2_L_DENSITY9_SIZE 7 1514 #define REG_G3X_FOG_TABLE_2_L_DENSITY9_MASK 0x7f00 1515 1516 #define REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT 0 1517 #define REG_G3X_FOG_TABLE_2_L_DENSITY8_SIZE 7 1518 #define REG_G3X_FOG_TABLE_2_L_DENSITY8_MASK 0x007f 1519 1520 #ifndef SDK_ASM 1521 #define REG_G3X_FOG_TABLE_2_L_FIELD( density9, density8 ) \ 1522 (u16)( \ 1523 ((u32)(density9) << REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT) | \ 1524 ((u32)(density8) << REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT)) 1525 #endif 1526 1527 1528 /* FOG_TABLE_2_H */ 1529 1530 #define REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT 8 1531 #define REG_G3X_FOG_TABLE_2_H_DENSITY11_SIZE 7 1532 #define REG_G3X_FOG_TABLE_2_H_DENSITY11_MASK 0x7f00 1533 1534 #define REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT 0 1535 #define REG_G3X_FOG_TABLE_2_H_DENSITY10_SIZE 7 1536 #define REG_G3X_FOG_TABLE_2_H_DENSITY10_MASK 0x007f 1537 1538 #ifndef SDK_ASM 1539 #define REG_G3X_FOG_TABLE_2_H_FIELD( density11, density10 ) \ 1540 (u16)( \ 1541 ((u32)(density11) << REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT) | \ 1542 ((u32)(density10) << REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT)) 1543 #endif 1544 1545 1546 /* FOG_TABLE_3 */ 1547 1548 #define REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT 24 1549 #define REG_G3X_FOG_TABLE_3_DENSITY15_SIZE 7 1550 #define REG_G3X_FOG_TABLE_3_DENSITY15_MASK 0x7f000000 1551 1552 #define REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT 16 1553 #define REG_G3X_FOG_TABLE_3_DENSITY14_SIZE 7 1554 #define REG_G3X_FOG_TABLE_3_DENSITY14_MASK 0x007f0000 1555 1556 #define REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT 8 1557 #define REG_G3X_FOG_TABLE_3_DENSITY13_SIZE 7 1558 #define REG_G3X_FOG_TABLE_3_DENSITY13_MASK 0x00007f00 1559 1560 #define REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT 0 1561 #define REG_G3X_FOG_TABLE_3_DENSITY12_SIZE 7 1562 #define REG_G3X_FOG_TABLE_3_DENSITY12_MASK 0x0000007f 1563 1564 #ifndef SDK_ASM 1565 #define REG_G3X_FOG_TABLE_3_FIELD( density15, density14, density13, density12 ) \ 1566 (u32)( \ 1567 ((u32)(density15) << REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT) | \ 1568 ((u32)(density14) << REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT) | \ 1569 ((u32)(density13) << REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT) | \ 1570 ((u32)(density12) << REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT)) 1571 #endif 1572 1573 1574 /* FOG_TABLE_3_L */ 1575 1576 #define REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT 8 1577 #define REG_G3X_FOG_TABLE_3_L_DENSITY13_SIZE 7 1578 #define REG_G3X_FOG_TABLE_3_L_DENSITY13_MASK 0x7f00 1579 1580 #define REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT 0 1581 #define REG_G3X_FOG_TABLE_3_L_DENSITY12_SIZE 7 1582 #define REG_G3X_FOG_TABLE_3_L_DENSITY12_MASK 0x007f 1583 1584 #ifndef SDK_ASM 1585 #define REG_G3X_FOG_TABLE_3_L_FIELD( density13, density12 ) \ 1586 (u16)( \ 1587 ((u32)(density13) << REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT) | \ 1588 ((u32)(density12) << REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT)) 1589 #endif 1590 1591 1592 /* FOG_TABLE_3_H */ 1593 1594 #define REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT 8 1595 #define REG_G3X_FOG_TABLE_3_H_DENSITY15_SIZE 7 1596 #define REG_G3X_FOG_TABLE_3_H_DENSITY15_MASK 0x7f00 1597 1598 #define REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT 0 1599 #define REG_G3X_FOG_TABLE_3_H_DENSITY14_SIZE 7 1600 #define REG_G3X_FOG_TABLE_3_H_DENSITY14_MASK 0x007f 1601 1602 #ifndef SDK_ASM 1603 #define REG_G3X_FOG_TABLE_3_H_FIELD( density15, density14 ) \ 1604 (u16)( \ 1605 ((u32)(density15) << REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT) | \ 1606 ((u32)(density14) << REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT)) 1607 #endif 1608 1609 1610 /* FOG_TABLE_4 */ 1611 1612 #define REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT 24 1613 #define REG_G3X_FOG_TABLE_4_DENSITY19_SIZE 7 1614 #define REG_G3X_FOG_TABLE_4_DENSITY19_MASK 0x7f000000 1615 1616 #define REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT 16 1617 #define REG_G3X_FOG_TABLE_4_DENSITY18_SIZE 7 1618 #define REG_G3X_FOG_TABLE_4_DENSITY18_MASK 0x007f0000 1619 1620 #define REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT 8 1621 #define REG_G3X_FOG_TABLE_4_DENSITY17_SIZE 7 1622 #define REG_G3X_FOG_TABLE_4_DENSITY17_MASK 0x00007f00 1623 1624 #define REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT 0 1625 #define REG_G3X_FOG_TABLE_4_DENSITY16_SIZE 7 1626 #define REG_G3X_FOG_TABLE_4_DENSITY16_MASK 0x0000007f 1627 1628 #ifndef SDK_ASM 1629 #define REG_G3X_FOG_TABLE_4_FIELD( density19, density18, density17, density16 ) \ 1630 (u32)( \ 1631 ((u32)(density19) << REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT) | \ 1632 ((u32)(density18) << REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT) | \ 1633 ((u32)(density17) << REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT) | \ 1634 ((u32)(density16) << REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT)) 1635 #endif 1636 1637 1638 /* FOG_TABLE_4_L */ 1639 1640 #define REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT 8 1641 #define REG_G3X_FOG_TABLE_4_L_DENSITY17_SIZE 7 1642 #define REG_G3X_FOG_TABLE_4_L_DENSITY17_MASK 0x7f00 1643 1644 #define REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT 0 1645 #define REG_G3X_FOG_TABLE_4_L_DENSITY16_SIZE 7 1646 #define REG_G3X_FOG_TABLE_4_L_DENSITY16_MASK 0x007f 1647 1648 #ifndef SDK_ASM 1649 #define REG_G3X_FOG_TABLE_4_L_FIELD( density17, density16 ) \ 1650 (u16)( \ 1651 ((u32)(density17) << REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT) | \ 1652 ((u32)(density16) << REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT)) 1653 #endif 1654 1655 1656 /* FOG_TABLE_4_H */ 1657 1658 #define REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT 8 1659 #define REG_G3X_FOG_TABLE_4_H_DENSITY19_SIZE 7 1660 #define REG_G3X_FOG_TABLE_4_H_DENSITY19_MASK 0x7f00 1661 1662 #define REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT 0 1663 #define REG_G3X_FOG_TABLE_4_H_DENSITY18_SIZE 7 1664 #define REG_G3X_FOG_TABLE_4_H_DENSITY18_MASK 0x007f 1665 1666 #ifndef SDK_ASM 1667 #define REG_G3X_FOG_TABLE_4_H_FIELD( density19, density18 ) \ 1668 (u16)( \ 1669 ((u32)(density19) << REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT) | \ 1670 ((u32)(density18) << REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT)) 1671 #endif 1672 1673 1674 /* FOG_TABLE_5 */ 1675 1676 #define REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT 24 1677 #define REG_G3X_FOG_TABLE_5_DENSITY23_SIZE 7 1678 #define REG_G3X_FOG_TABLE_5_DENSITY23_MASK 0x7f000000 1679 1680 #define REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT 16 1681 #define REG_G3X_FOG_TABLE_5_DENSITY22_SIZE 7 1682 #define REG_G3X_FOG_TABLE_5_DENSITY22_MASK 0x007f0000 1683 1684 #define REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT 8 1685 #define REG_G3X_FOG_TABLE_5_DENSITY21_SIZE 7 1686 #define REG_G3X_FOG_TABLE_5_DENSITY21_MASK 0x00007f00 1687 1688 #define REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT 0 1689 #define REG_G3X_FOG_TABLE_5_DENSITY20_SIZE 7 1690 #define REG_G3X_FOG_TABLE_5_DENSITY20_MASK 0x0000007f 1691 1692 #ifndef SDK_ASM 1693 #define REG_G3X_FOG_TABLE_5_FIELD( density23, density22, density21, density20 ) \ 1694 (u32)( \ 1695 ((u32)(density23) << REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT) | \ 1696 ((u32)(density22) << REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT) | \ 1697 ((u32)(density21) << REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT) | \ 1698 ((u32)(density20) << REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT)) 1699 #endif 1700 1701 1702 /* FOG_TABLE_5_L */ 1703 1704 #define REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT 8 1705 #define REG_G3X_FOG_TABLE_5_L_DENSITY21_SIZE 7 1706 #define REG_G3X_FOG_TABLE_5_L_DENSITY21_MASK 0x7f00 1707 1708 #define REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT 0 1709 #define REG_G3X_FOG_TABLE_5_L_DENSITY20_SIZE 7 1710 #define REG_G3X_FOG_TABLE_5_L_DENSITY20_MASK 0x007f 1711 1712 #ifndef SDK_ASM 1713 #define REG_G3X_FOG_TABLE_5_L_FIELD( density21, density20 ) \ 1714 (u16)( \ 1715 ((u32)(density21) << REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT) | \ 1716 ((u32)(density20) << REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT)) 1717 #endif 1718 1719 1720 /* FOG_TABLE_5_H */ 1721 1722 #define REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT 8 1723 #define REG_G3X_FOG_TABLE_5_H_DENSITY23_SIZE 7 1724 #define REG_G3X_FOG_TABLE_5_H_DENSITY23_MASK 0x7f00 1725 1726 #define REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT 0 1727 #define REG_G3X_FOG_TABLE_5_H_DENSITY22_SIZE 7 1728 #define REG_G3X_FOG_TABLE_5_H_DENSITY22_MASK 0x007f 1729 1730 #ifndef SDK_ASM 1731 #define REG_G3X_FOG_TABLE_5_H_FIELD( density23, density22 ) \ 1732 (u16)( \ 1733 ((u32)(density23) << REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT) | \ 1734 ((u32)(density22) << REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT)) 1735 #endif 1736 1737 1738 /* FOG_TABLE_6 */ 1739 1740 #define REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT 24 1741 #define REG_G3X_FOG_TABLE_6_DENSITY27_SIZE 7 1742 #define REG_G3X_FOG_TABLE_6_DENSITY27_MASK 0x7f000000 1743 1744 #define REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT 16 1745 #define REG_G3X_FOG_TABLE_6_DENSITY26_SIZE 7 1746 #define REG_G3X_FOG_TABLE_6_DENSITY26_MASK 0x007f0000 1747 1748 #define REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT 8 1749 #define REG_G3X_FOG_TABLE_6_DENSITY25_SIZE 7 1750 #define REG_G3X_FOG_TABLE_6_DENSITY25_MASK 0x00007f00 1751 1752 #define REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT 0 1753 #define REG_G3X_FOG_TABLE_6_DENSITY24_SIZE 7 1754 #define REG_G3X_FOG_TABLE_6_DENSITY24_MASK 0x0000007f 1755 1756 #ifndef SDK_ASM 1757 #define REG_G3X_FOG_TABLE_6_FIELD( density27, density26, density25, density24 ) \ 1758 (u32)( \ 1759 ((u32)(density27) << REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT) | \ 1760 ((u32)(density26) << REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT) | \ 1761 ((u32)(density25) << REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT) | \ 1762 ((u32)(density24) << REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT)) 1763 #endif 1764 1765 1766 /* FOG_TABLE_6_L */ 1767 1768 #define REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT 8 1769 #define REG_G3X_FOG_TABLE_6_L_DENSITY25_SIZE 7 1770 #define REG_G3X_FOG_TABLE_6_L_DENSITY25_MASK 0x7f00 1771 1772 #define REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT 0 1773 #define REG_G3X_FOG_TABLE_6_L_DENSITY24_SIZE 7 1774 #define REG_G3X_FOG_TABLE_6_L_DENSITY24_MASK 0x007f 1775 1776 #ifndef SDK_ASM 1777 #define REG_G3X_FOG_TABLE_6_L_FIELD( density25, density24 ) \ 1778 (u16)( \ 1779 ((u32)(density25) << REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT) | \ 1780 ((u32)(density24) << REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT)) 1781 #endif 1782 1783 1784 /* FOG_TABLE_6_H */ 1785 1786 #define REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT 8 1787 #define REG_G3X_FOG_TABLE_6_H_DENSITY27_SIZE 7 1788 #define REG_G3X_FOG_TABLE_6_H_DENSITY27_MASK 0x7f00 1789 1790 #define REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT 0 1791 #define REG_G3X_FOG_TABLE_6_H_DENSITY26_SIZE 7 1792 #define REG_G3X_FOG_TABLE_6_H_DENSITY26_MASK 0x007f 1793 1794 #ifndef SDK_ASM 1795 #define REG_G3X_FOG_TABLE_6_H_FIELD( density27, density26 ) \ 1796 (u16)( \ 1797 ((u32)(density27) << REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT) | \ 1798 ((u32)(density26) << REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT)) 1799 #endif 1800 1801 1802 /* FOG_TABLE_7 */ 1803 1804 #define REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT 24 1805 #define REG_G3X_FOG_TABLE_7_DENSITY31_SIZE 7 1806 #define REG_G3X_FOG_TABLE_7_DENSITY31_MASK 0x7f000000 1807 1808 #define REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT 16 1809 #define REG_G3X_FOG_TABLE_7_DENSITY30_SIZE 7 1810 #define REG_G3X_FOG_TABLE_7_DENSITY30_MASK 0x007f0000 1811 1812 #define REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT 8 1813 #define REG_G3X_FOG_TABLE_7_DENSITY29_SIZE 7 1814 #define REG_G3X_FOG_TABLE_7_DENSITY29_MASK 0x00007f00 1815 1816 #define REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT 0 1817 #define REG_G3X_FOG_TABLE_7_DENSITY28_SIZE 7 1818 #define REG_G3X_FOG_TABLE_7_DENSITY28_MASK 0x0000007f 1819 1820 #ifndef SDK_ASM 1821 #define REG_G3X_FOG_TABLE_7_FIELD( density31, density30, density29, density28 ) \ 1822 (u32)( \ 1823 ((u32)(density31) << REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT) | \ 1824 ((u32)(density30) << REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT) | \ 1825 ((u32)(density29) << REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT) | \ 1826 ((u32)(density28) << REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT)) 1827 #endif 1828 1829 1830 /* FOG_TABLE_7_L */ 1831 1832 #define REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT 8 1833 #define REG_G3X_FOG_TABLE_7_L_DENSITY29_SIZE 7 1834 #define REG_G3X_FOG_TABLE_7_L_DENSITY29_MASK 0x7f00 1835 1836 #define REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT 0 1837 #define REG_G3X_FOG_TABLE_7_L_DENSITY28_SIZE 7 1838 #define REG_G3X_FOG_TABLE_7_L_DENSITY28_MASK 0x007f 1839 1840 #ifndef SDK_ASM 1841 #define REG_G3X_FOG_TABLE_7_L_FIELD( density29, density28 ) \ 1842 (u16)( \ 1843 ((u32)(density29) << REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT) | \ 1844 ((u32)(density28) << REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT)) 1845 #endif 1846 1847 1848 /* FOG_TABLE_7_H */ 1849 1850 #define REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT 8 1851 #define REG_G3X_FOG_TABLE_7_H_DENSITY31_SIZE 7 1852 #define REG_G3X_FOG_TABLE_7_H_DENSITY31_MASK 0x7f00 1853 1854 #define REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT 0 1855 #define REG_G3X_FOG_TABLE_7_H_DENSITY30_SIZE 7 1856 #define REG_G3X_FOG_TABLE_7_H_DENSITY30_MASK 0x007f 1857 1858 #ifndef SDK_ASM 1859 #define REG_G3X_FOG_TABLE_7_H_FIELD( density31, density30 ) \ 1860 (u16)( \ 1861 ((u32)(density31) << REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT) | \ 1862 ((u32)(density30) << REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT)) 1863 #endif 1864 1865 1866 /* TOON_TABLE_0 */ 1867 1868 #define REG_G3X_TOON_TABLE_0_BLUE1_SHIFT 26 1869 #define REG_G3X_TOON_TABLE_0_BLUE1_SIZE 5 1870 #define REG_G3X_TOON_TABLE_0_BLUE1_MASK 0x7c000000 1871 1872 #define REG_G3X_TOON_TABLE_0_GREEN1_SHIFT 21 1873 #define REG_G3X_TOON_TABLE_0_GREEN1_SIZE 5 1874 #define REG_G3X_TOON_TABLE_0_GREEN1_MASK 0x03e00000 1875 1876 #define REG_G3X_TOON_TABLE_0_RED1_SHIFT 16 1877 #define REG_G3X_TOON_TABLE_0_RED1_SIZE 5 1878 #define REG_G3X_TOON_TABLE_0_RED1_MASK 0x001f0000 1879 1880 #define REG_G3X_TOON_TABLE_0_BLUE0_SHIFT 10 1881 #define REG_G3X_TOON_TABLE_0_BLUE0_SIZE 5 1882 #define REG_G3X_TOON_TABLE_0_BLUE0_MASK 0x00007c00 1883 1884 #define REG_G3X_TOON_TABLE_0_GREEN0_SHIFT 5 1885 #define REG_G3X_TOON_TABLE_0_GREEN0_SIZE 5 1886 #define REG_G3X_TOON_TABLE_0_GREEN0_MASK 0x000003e0 1887 1888 #define REG_G3X_TOON_TABLE_0_RED0_SHIFT 0 1889 #define REG_G3X_TOON_TABLE_0_RED0_SIZE 5 1890 #define REG_G3X_TOON_TABLE_0_RED0_MASK 0x0000001f 1891 1892 #ifndef SDK_ASM 1893 #define REG_G3X_TOON_TABLE_0_FIELD( blue1, green1, red1, blue0, green0, red0 ) \ 1894 (u32)( \ 1895 ((u32)(blue1) << REG_G3X_TOON_TABLE_0_BLUE1_SHIFT) | \ 1896 ((u32)(green1) << REG_G3X_TOON_TABLE_0_GREEN1_SHIFT) | \ 1897 ((u32)(red1) << REG_G3X_TOON_TABLE_0_RED1_SHIFT) | \ 1898 ((u32)(blue0) << REG_G3X_TOON_TABLE_0_BLUE0_SHIFT) | \ 1899 ((u32)(green0) << REG_G3X_TOON_TABLE_0_GREEN0_SHIFT) | \ 1900 ((u32)(red0) << REG_G3X_TOON_TABLE_0_RED0_SHIFT)) 1901 #endif 1902 1903 1904 /* TOON_TABLE_0_L */ 1905 1906 #define REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT 10 1907 #define REG_G3X_TOON_TABLE_0_L_BLUE0_SIZE 5 1908 #define REG_G3X_TOON_TABLE_0_L_BLUE0_MASK 0x7c00 1909 1910 #define REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT 5 1911 #define REG_G3X_TOON_TABLE_0_L_GREEN0_SIZE 5 1912 #define REG_G3X_TOON_TABLE_0_L_GREEN0_MASK 0x03e0 1913 1914 #define REG_G3X_TOON_TABLE_0_L_RED0_SHIFT 0 1915 #define REG_G3X_TOON_TABLE_0_L_RED0_SIZE 5 1916 #define REG_G3X_TOON_TABLE_0_L_RED0_MASK 0x001f 1917 1918 #ifndef SDK_ASM 1919 #define REG_G3X_TOON_TABLE_0_L_FIELD( blue0, green0, red0 ) \ 1920 (u16)( \ 1921 ((u32)(blue0) << REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT) | \ 1922 ((u32)(green0) << REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT) | \ 1923 ((u32)(red0) << REG_G3X_TOON_TABLE_0_L_RED0_SHIFT)) 1924 #endif 1925 1926 1927 /* TOON_TABLE_0_H */ 1928 1929 #define REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT 10 1930 #define REG_G3X_TOON_TABLE_0_H_BLUE1_SIZE 5 1931 #define REG_G3X_TOON_TABLE_0_H_BLUE1_MASK 0x7c00 1932 1933 #define REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT 5 1934 #define REG_G3X_TOON_TABLE_0_H_GREEN1_SIZE 5 1935 #define REG_G3X_TOON_TABLE_0_H_GREEN1_MASK 0x03e0 1936 1937 #define REG_G3X_TOON_TABLE_0_H_RED1_SHIFT 0 1938 #define REG_G3X_TOON_TABLE_0_H_RED1_SIZE 5 1939 #define REG_G3X_TOON_TABLE_0_H_RED1_MASK 0x001f 1940 1941 #ifndef SDK_ASM 1942 #define REG_G3X_TOON_TABLE_0_H_FIELD( blue1, green1, red1 ) \ 1943 (u16)( \ 1944 ((u32)(blue1) << REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT) | \ 1945 ((u32)(green1) << REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT) | \ 1946 ((u32)(red1) << REG_G3X_TOON_TABLE_0_H_RED1_SHIFT)) 1947 #endif 1948 1949 1950 /* TOON_TABLE_1 */ 1951 1952 #define REG_G3X_TOON_TABLE_1_BLUE3_SHIFT 26 1953 #define REG_G3X_TOON_TABLE_1_BLUE3_SIZE 5 1954 #define REG_G3X_TOON_TABLE_1_BLUE3_MASK 0x7c000000 1955 1956 #define REG_G3X_TOON_TABLE_1_GREEN3_SHIFT 21 1957 #define REG_G3X_TOON_TABLE_1_GREEN3_SIZE 5 1958 #define REG_G3X_TOON_TABLE_1_GREEN3_MASK 0x03e00000 1959 1960 #define REG_G3X_TOON_TABLE_1_RED3_SHIFT 16 1961 #define REG_G3X_TOON_TABLE_1_RED3_SIZE 5 1962 #define REG_G3X_TOON_TABLE_1_RED3_MASK 0x001f0000 1963 1964 #define REG_G3X_TOON_TABLE_1_BLUE2_SHIFT 10 1965 #define REG_G3X_TOON_TABLE_1_BLUE2_SIZE 5 1966 #define REG_G3X_TOON_TABLE_1_BLUE2_MASK 0x00007c00 1967 1968 #define REG_G3X_TOON_TABLE_1_GREEN2_SHIFT 5 1969 #define REG_G3X_TOON_TABLE_1_GREEN2_SIZE 5 1970 #define REG_G3X_TOON_TABLE_1_GREEN2_MASK 0x000003e0 1971 1972 #define REG_G3X_TOON_TABLE_1_RED2_SHIFT 0 1973 #define REG_G3X_TOON_TABLE_1_RED2_SIZE 5 1974 #define REG_G3X_TOON_TABLE_1_RED2_MASK 0x0000001f 1975 1976 #ifndef SDK_ASM 1977 #define REG_G3X_TOON_TABLE_1_FIELD( blue3, green3, red3, blue2, green2, red2 ) \ 1978 (u32)( \ 1979 ((u32)(blue3) << REG_G3X_TOON_TABLE_1_BLUE3_SHIFT) | \ 1980 ((u32)(green3) << REG_G3X_TOON_TABLE_1_GREEN3_SHIFT) | \ 1981 ((u32)(red3) << REG_G3X_TOON_TABLE_1_RED3_SHIFT) | \ 1982 ((u32)(blue2) << REG_G3X_TOON_TABLE_1_BLUE2_SHIFT) | \ 1983 ((u32)(green2) << REG_G3X_TOON_TABLE_1_GREEN2_SHIFT) | \ 1984 ((u32)(red2) << REG_G3X_TOON_TABLE_1_RED2_SHIFT)) 1985 #endif 1986 1987 1988 /* TOON_TABLE_1_L */ 1989 1990 #define REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT 10 1991 #define REG_G3X_TOON_TABLE_1_L_BLUE2_SIZE 5 1992 #define REG_G3X_TOON_TABLE_1_L_BLUE2_MASK 0x7c00 1993 1994 #define REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT 5 1995 #define REG_G3X_TOON_TABLE_1_L_GREEN2_SIZE 5 1996 #define REG_G3X_TOON_TABLE_1_L_GREEN2_MASK 0x03e0 1997 1998 #define REG_G3X_TOON_TABLE_1_L_RED2_SHIFT 0 1999 #define REG_G3X_TOON_TABLE_1_L_RED2_SIZE 5 2000 #define REG_G3X_TOON_TABLE_1_L_RED2_MASK 0x001f 2001 2002 #ifndef SDK_ASM 2003 #define REG_G3X_TOON_TABLE_1_L_FIELD( blue2, green2, red2 ) \ 2004 (u16)( \ 2005 ((u32)(blue2) << REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT) | \ 2006 ((u32)(green2) << REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT) | \ 2007 ((u32)(red2) << REG_G3X_TOON_TABLE_1_L_RED2_SHIFT)) 2008 #endif 2009 2010 2011 /* TOON_TABLE_1_H */ 2012 2013 #define REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT 10 2014 #define REG_G3X_TOON_TABLE_1_H_BLUE3_SIZE 5 2015 #define REG_G3X_TOON_TABLE_1_H_BLUE3_MASK 0x7c00 2016 2017 #define REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT 5 2018 #define REG_G3X_TOON_TABLE_1_H_GREEN3_SIZE 5 2019 #define REG_G3X_TOON_TABLE_1_H_GREEN3_MASK 0x03e0 2020 2021 #define REG_G3X_TOON_TABLE_1_H_RED3_SHIFT 0 2022 #define REG_G3X_TOON_TABLE_1_H_RED3_SIZE 5 2023 #define REG_G3X_TOON_TABLE_1_H_RED3_MASK 0x001f 2024 2025 #ifndef SDK_ASM 2026 #define REG_G3X_TOON_TABLE_1_H_FIELD( blue3, green3, red3 ) \ 2027 (u16)( \ 2028 ((u32)(blue3) << REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT) | \ 2029 ((u32)(green3) << REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT) | \ 2030 ((u32)(red3) << REG_G3X_TOON_TABLE_1_H_RED3_SHIFT)) 2031 #endif 2032 2033 2034 /* TOON_TABLE_2 */ 2035 2036 #define REG_G3X_TOON_TABLE_2_BLUE5_SHIFT 26 2037 #define REG_G3X_TOON_TABLE_2_BLUE5_SIZE 5 2038 #define REG_G3X_TOON_TABLE_2_BLUE5_MASK 0x7c000000 2039 2040 #define REG_G3X_TOON_TABLE_2_GREEN5_SHIFT 21 2041 #define REG_G3X_TOON_TABLE_2_GREEN5_SIZE 5 2042 #define REG_G3X_TOON_TABLE_2_GREEN5_MASK 0x03e00000 2043 2044 #define REG_G3X_TOON_TABLE_2_RED5_SHIFT 16 2045 #define REG_G3X_TOON_TABLE_2_RED5_SIZE 5 2046 #define REG_G3X_TOON_TABLE_2_RED5_MASK 0x001f0000 2047 2048 #define REG_G3X_TOON_TABLE_2_BLUE4_SHIFT 10 2049 #define REG_G3X_TOON_TABLE_2_BLUE4_SIZE 5 2050 #define REG_G3X_TOON_TABLE_2_BLUE4_MASK 0x00007c00 2051 2052 #define REG_G3X_TOON_TABLE_2_GREEN4_SHIFT 5 2053 #define REG_G3X_TOON_TABLE_2_GREEN4_SIZE 5 2054 #define REG_G3X_TOON_TABLE_2_GREEN4_MASK 0x000003e0 2055 2056 #define REG_G3X_TOON_TABLE_2_RED4_SHIFT 0 2057 #define REG_G3X_TOON_TABLE_2_RED4_SIZE 5 2058 #define REG_G3X_TOON_TABLE_2_RED4_MASK 0x0000001f 2059 2060 #ifndef SDK_ASM 2061 #define REG_G3X_TOON_TABLE_2_FIELD( blue5, green5, red5, blue4, green4, red4 ) \ 2062 (u32)( \ 2063 ((u32)(blue5) << REG_G3X_TOON_TABLE_2_BLUE5_SHIFT) | \ 2064 ((u32)(green5) << REG_G3X_TOON_TABLE_2_GREEN5_SHIFT) | \ 2065 ((u32)(red5) << REG_G3X_TOON_TABLE_2_RED5_SHIFT) | \ 2066 ((u32)(blue4) << REG_G3X_TOON_TABLE_2_BLUE4_SHIFT) | \ 2067 ((u32)(green4) << REG_G3X_TOON_TABLE_2_GREEN4_SHIFT) | \ 2068 ((u32)(red4) << REG_G3X_TOON_TABLE_2_RED4_SHIFT)) 2069 #endif 2070 2071 2072 /* TOON_TABLE_2_L */ 2073 2074 #define REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT 10 2075 #define REG_G3X_TOON_TABLE_2_L_BLUE4_SIZE 5 2076 #define REG_G3X_TOON_TABLE_2_L_BLUE4_MASK 0x7c00 2077 2078 #define REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT 5 2079 #define REG_G3X_TOON_TABLE_2_L_GREEN4_SIZE 5 2080 #define REG_G3X_TOON_TABLE_2_L_GREEN4_MASK 0x03e0 2081 2082 #define REG_G3X_TOON_TABLE_2_L_RED4_SHIFT 0 2083 #define REG_G3X_TOON_TABLE_2_L_RED4_SIZE 5 2084 #define REG_G3X_TOON_TABLE_2_L_RED4_MASK 0x001f 2085 2086 #ifndef SDK_ASM 2087 #define REG_G3X_TOON_TABLE_2_L_FIELD( blue4, green4, red4 ) \ 2088 (u16)( \ 2089 ((u32)(blue4) << REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT) | \ 2090 ((u32)(green4) << REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT) | \ 2091 ((u32)(red4) << REG_G3X_TOON_TABLE_2_L_RED4_SHIFT)) 2092 #endif 2093 2094 2095 /* TOON_TABLE_2_H */ 2096 2097 #define REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT 10 2098 #define REG_G3X_TOON_TABLE_2_H_BLUE5_SIZE 5 2099 #define REG_G3X_TOON_TABLE_2_H_BLUE5_MASK 0x7c00 2100 2101 #define REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT 5 2102 #define REG_G3X_TOON_TABLE_2_H_GREEN5_SIZE 5 2103 #define REG_G3X_TOON_TABLE_2_H_GREEN5_MASK 0x03e0 2104 2105 #define REG_G3X_TOON_TABLE_2_H_RED5_SHIFT 0 2106 #define REG_G3X_TOON_TABLE_2_H_RED5_SIZE 5 2107 #define REG_G3X_TOON_TABLE_2_H_RED5_MASK 0x001f 2108 2109 #ifndef SDK_ASM 2110 #define REG_G3X_TOON_TABLE_2_H_FIELD( blue5, green5, red5 ) \ 2111 (u16)( \ 2112 ((u32)(blue5) << REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT) | \ 2113 ((u32)(green5) << REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT) | \ 2114 ((u32)(red5) << REG_G3X_TOON_TABLE_2_H_RED5_SHIFT)) 2115 #endif 2116 2117 2118 /* TOON_TABLE_3 */ 2119 2120 #define REG_G3X_TOON_TABLE_3_BLUE7_SHIFT 26 2121 #define REG_G3X_TOON_TABLE_3_BLUE7_SIZE 5 2122 #define REG_G3X_TOON_TABLE_3_BLUE7_MASK 0x7c000000 2123 2124 #define REG_G3X_TOON_TABLE_3_GREEN7_SHIFT 21 2125 #define REG_G3X_TOON_TABLE_3_GREEN7_SIZE 5 2126 #define REG_G3X_TOON_TABLE_3_GREEN7_MASK 0x03e00000 2127 2128 #define REG_G3X_TOON_TABLE_3_RED7_SHIFT 16 2129 #define REG_G3X_TOON_TABLE_3_RED7_SIZE 5 2130 #define REG_G3X_TOON_TABLE_3_RED7_MASK 0x001f0000 2131 2132 #define REG_G3X_TOON_TABLE_3_BLUE6_SHIFT 10 2133 #define REG_G3X_TOON_TABLE_3_BLUE6_SIZE 5 2134 #define REG_G3X_TOON_TABLE_3_BLUE6_MASK 0x00007c00 2135 2136 #define REG_G3X_TOON_TABLE_3_GREEN6_SHIFT 5 2137 #define REG_G3X_TOON_TABLE_3_GREEN6_SIZE 5 2138 #define REG_G3X_TOON_TABLE_3_GREEN6_MASK 0x000003e0 2139 2140 #define REG_G3X_TOON_TABLE_3_RED6_SHIFT 0 2141 #define REG_G3X_TOON_TABLE_3_RED6_SIZE 5 2142 #define REG_G3X_TOON_TABLE_3_RED6_MASK 0x0000001f 2143 2144 #ifndef SDK_ASM 2145 #define REG_G3X_TOON_TABLE_3_FIELD( blue7, green7, red7, blue6, green6, red6 ) \ 2146 (u32)( \ 2147 ((u32)(blue7) << REG_G3X_TOON_TABLE_3_BLUE7_SHIFT) | \ 2148 ((u32)(green7) << REG_G3X_TOON_TABLE_3_GREEN7_SHIFT) | \ 2149 ((u32)(red7) << REG_G3X_TOON_TABLE_3_RED7_SHIFT) | \ 2150 ((u32)(blue6) << REG_G3X_TOON_TABLE_3_BLUE6_SHIFT) | \ 2151 ((u32)(green6) << REG_G3X_TOON_TABLE_3_GREEN6_SHIFT) | \ 2152 ((u32)(red6) << REG_G3X_TOON_TABLE_3_RED6_SHIFT)) 2153 #endif 2154 2155 2156 /* TOON_TABLE_3_L */ 2157 2158 #define REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT 10 2159 #define REG_G3X_TOON_TABLE_3_L_BLUE6_SIZE 5 2160 #define REG_G3X_TOON_TABLE_3_L_BLUE6_MASK 0x7c00 2161 2162 #define REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT 5 2163 #define REG_G3X_TOON_TABLE_3_L_GREEN6_SIZE 5 2164 #define REG_G3X_TOON_TABLE_3_L_GREEN6_MASK 0x03e0 2165 2166 #define REG_G3X_TOON_TABLE_3_L_RED6_SHIFT 0 2167 #define REG_G3X_TOON_TABLE_3_L_RED6_SIZE 5 2168 #define REG_G3X_TOON_TABLE_3_L_RED6_MASK 0x001f 2169 2170 #ifndef SDK_ASM 2171 #define REG_G3X_TOON_TABLE_3_L_FIELD( blue6, green6, red6 ) \ 2172 (u16)( \ 2173 ((u32)(blue6) << REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT) | \ 2174 ((u32)(green6) << REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT) | \ 2175 ((u32)(red6) << REG_G3X_TOON_TABLE_3_L_RED6_SHIFT)) 2176 #endif 2177 2178 2179 /* TOON_TABLE_3_H */ 2180 2181 #define REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT 10 2182 #define REG_G3X_TOON_TABLE_3_H_BLUE7_SIZE 5 2183 #define REG_G3X_TOON_TABLE_3_H_BLUE7_MASK 0x7c00 2184 2185 #define REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT 5 2186 #define REG_G3X_TOON_TABLE_3_H_GREEN7_SIZE 5 2187 #define REG_G3X_TOON_TABLE_3_H_GREEN7_MASK 0x03e0 2188 2189 #define REG_G3X_TOON_TABLE_3_H_RED7_SHIFT 0 2190 #define REG_G3X_TOON_TABLE_3_H_RED7_SIZE 5 2191 #define REG_G3X_TOON_TABLE_3_H_RED7_MASK 0x001f 2192 2193 #ifndef SDK_ASM 2194 #define REG_G3X_TOON_TABLE_3_H_FIELD( blue7, green7, red7 ) \ 2195 (u16)( \ 2196 ((u32)(blue7) << REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT) | \ 2197 ((u32)(green7) << REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT) | \ 2198 ((u32)(red7) << REG_G3X_TOON_TABLE_3_H_RED7_SHIFT)) 2199 #endif 2200 2201 2202 /* TOON_TABLE_4 */ 2203 2204 #define REG_G3X_TOON_TABLE_4_BLUE9_SHIFT 26 2205 #define REG_G3X_TOON_TABLE_4_BLUE9_SIZE 5 2206 #define REG_G3X_TOON_TABLE_4_BLUE9_MASK 0x7c000000 2207 2208 #define REG_G3X_TOON_TABLE_4_GREEN9_SHIFT 21 2209 #define REG_G3X_TOON_TABLE_4_GREEN9_SIZE 5 2210 #define REG_G3X_TOON_TABLE_4_GREEN9_MASK 0x03e00000 2211 2212 #define REG_G3X_TOON_TABLE_4_RED9_SHIFT 16 2213 #define REG_G3X_TOON_TABLE_4_RED9_SIZE 5 2214 #define REG_G3X_TOON_TABLE_4_RED9_MASK 0x001f0000 2215 2216 #define REG_G3X_TOON_TABLE_4_BLUE8_SHIFT 10 2217 #define REG_G3X_TOON_TABLE_4_BLUE8_SIZE 5 2218 #define REG_G3X_TOON_TABLE_4_BLUE8_MASK 0x00007c00 2219 2220 #define REG_G3X_TOON_TABLE_4_GREEN8_SHIFT 5 2221 #define REG_G3X_TOON_TABLE_4_GREEN8_SIZE 5 2222 #define REG_G3X_TOON_TABLE_4_GREEN8_MASK 0x000003e0 2223 2224 #define REG_G3X_TOON_TABLE_4_RED8_SHIFT 0 2225 #define REG_G3X_TOON_TABLE_4_RED8_SIZE 5 2226 #define REG_G3X_TOON_TABLE_4_RED8_MASK 0x0000001f 2227 2228 #ifndef SDK_ASM 2229 #define REG_G3X_TOON_TABLE_4_FIELD( blue9, green9, red9, blue8, green8, red8 ) \ 2230 (u32)( \ 2231 ((u32)(blue9) << REG_G3X_TOON_TABLE_4_BLUE9_SHIFT) | \ 2232 ((u32)(green9) << REG_G3X_TOON_TABLE_4_GREEN9_SHIFT) | \ 2233 ((u32)(red9) << REG_G3X_TOON_TABLE_4_RED9_SHIFT) | \ 2234 ((u32)(blue8) << REG_G3X_TOON_TABLE_4_BLUE8_SHIFT) | \ 2235 ((u32)(green8) << REG_G3X_TOON_TABLE_4_GREEN8_SHIFT) | \ 2236 ((u32)(red8) << REG_G3X_TOON_TABLE_4_RED8_SHIFT)) 2237 #endif 2238 2239 2240 /* TOON_TABLE_4_L */ 2241 2242 #define REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT 10 2243 #define REG_G3X_TOON_TABLE_4_L_BLUE8_SIZE 5 2244 #define REG_G3X_TOON_TABLE_4_L_BLUE8_MASK 0x7c00 2245 2246 #define REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT 5 2247 #define REG_G3X_TOON_TABLE_4_L_GREEN8_SIZE 5 2248 #define REG_G3X_TOON_TABLE_4_L_GREEN8_MASK 0x03e0 2249 2250 #define REG_G3X_TOON_TABLE_4_L_RED8_SHIFT 0 2251 #define REG_G3X_TOON_TABLE_4_L_RED8_SIZE 5 2252 #define REG_G3X_TOON_TABLE_4_L_RED8_MASK 0x001f 2253 2254 #ifndef SDK_ASM 2255 #define REG_G3X_TOON_TABLE_4_L_FIELD( blue8, green8, red8 ) \ 2256 (u16)( \ 2257 ((u32)(blue8) << REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT) | \ 2258 ((u32)(green8) << REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT) | \ 2259 ((u32)(red8) << REG_G3X_TOON_TABLE_4_L_RED8_SHIFT)) 2260 #endif 2261 2262 2263 /* TOON_TABLE_4_H */ 2264 2265 #define REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT 10 2266 #define REG_G3X_TOON_TABLE_4_H_BLUE9_SIZE 5 2267 #define REG_G3X_TOON_TABLE_4_H_BLUE9_MASK 0x7c00 2268 2269 #define REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT 5 2270 #define REG_G3X_TOON_TABLE_4_H_GREEN9_SIZE 5 2271 #define REG_G3X_TOON_TABLE_4_H_GREEN9_MASK 0x03e0 2272 2273 #define REG_G3X_TOON_TABLE_4_H_RED9_SHIFT 0 2274 #define REG_G3X_TOON_TABLE_4_H_RED9_SIZE 5 2275 #define REG_G3X_TOON_TABLE_4_H_RED9_MASK 0x001f 2276 2277 #ifndef SDK_ASM 2278 #define REG_G3X_TOON_TABLE_4_H_FIELD( blue9, green9, red9 ) \ 2279 (u16)( \ 2280 ((u32)(blue9) << REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT) | \ 2281 ((u32)(green9) << REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT) | \ 2282 ((u32)(red9) << REG_G3X_TOON_TABLE_4_H_RED9_SHIFT)) 2283 #endif 2284 2285 2286 /* TOON_TABLE_5 */ 2287 2288 #define REG_G3X_TOON_TABLE_5_BLUE11_SHIFT 26 2289 #define REG_G3X_TOON_TABLE_5_BLUE11_SIZE 5 2290 #define REG_G3X_TOON_TABLE_5_BLUE11_MASK 0x7c000000 2291 2292 #define REG_G3X_TOON_TABLE_5_GREEN11_SHIFT 21 2293 #define REG_G3X_TOON_TABLE_5_GREEN11_SIZE 5 2294 #define REG_G3X_TOON_TABLE_5_GREEN11_MASK 0x03e00000 2295 2296 #define REG_G3X_TOON_TABLE_5_RED11_SHIFT 16 2297 #define REG_G3X_TOON_TABLE_5_RED11_SIZE 5 2298 #define REG_G3X_TOON_TABLE_5_RED11_MASK 0x001f0000 2299 2300 #define REG_G3X_TOON_TABLE_5_BLUE10_SHIFT 10 2301 #define REG_G3X_TOON_TABLE_5_BLUE10_SIZE 5 2302 #define REG_G3X_TOON_TABLE_5_BLUE10_MASK 0x00007c00 2303 2304 #define REG_G3X_TOON_TABLE_5_GREEN10_SHIFT 5 2305 #define REG_G3X_TOON_TABLE_5_GREEN10_SIZE 5 2306 #define REG_G3X_TOON_TABLE_5_GREEN10_MASK 0x000003e0 2307 2308 #define REG_G3X_TOON_TABLE_5_RED10_SHIFT 0 2309 #define REG_G3X_TOON_TABLE_5_RED10_SIZE 5 2310 #define REG_G3X_TOON_TABLE_5_RED10_MASK 0x0000001f 2311 2312 #ifndef SDK_ASM 2313 #define REG_G3X_TOON_TABLE_5_FIELD( blue11, green11, red11, blue10, green10, red10 ) \ 2314 (u32)( \ 2315 ((u32)(blue11) << REG_G3X_TOON_TABLE_5_BLUE11_SHIFT) | \ 2316 ((u32)(green11) << REG_G3X_TOON_TABLE_5_GREEN11_SHIFT) | \ 2317 ((u32)(red11) << REG_G3X_TOON_TABLE_5_RED11_SHIFT) | \ 2318 ((u32)(blue10) << REG_G3X_TOON_TABLE_5_BLUE10_SHIFT) | \ 2319 ((u32)(green10) << REG_G3X_TOON_TABLE_5_GREEN10_SHIFT) | \ 2320 ((u32)(red10) << REG_G3X_TOON_TABLE_5_RED10_SHIFT)) 2321 #endif 2322 2323 2324 /* TOON_TABLE_5_L */ 2325 2326 #define REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT 10 2327 #define REG_G3X_TOON_TABLE_5_L_BLUE10_SIZE 5 2328 #define REG_G3X_TOON_TABLE_5_L_BLUE10_MASK 0x7c00 2329 2330 #define REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT 5 2331 #define REG_G3X_TOON_TABLE_5_L_GREEN10_SIZE 5 2332 #define REG_G3X_TOON_TABLE_5_L_GREEN10_MASK 0x03e0 2333 2334 #define REG_G3X_TOON_TABLE_5_L_RED10_SHIFT 0 2335 #define REG_G3X_TOON_TABLE_5_L_RED10_SIZE 5 2336 #define REG_G3X_TOON_TABLE_5_L_RED10_MASK 0x001f 2337 2338 #ifndef SDK_ASM 2339 #define REG_G3X_TOON_TABLE_5_L_FIELD( blue10, green10, red10 ) \ 2340 (u16)( \ 2341 ((u32)(blue10) << REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT) | \ 2342 ((u32)(green10) << REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT) | \ 2343 ((u32)(red10) << REG_G3X_TOON_TABLE_5_L_RED10_SHIFT)) 2344 #endif 2345 2346 2347 /* TOON_TABLE_5_H */ 2348 2349 #define REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT 10 2350 #define REG_G3X_TOON_TABLE_5_H_BLUE11_SIZE 5 2351 #define REG_G3X_TOON_TABLE_5_H_BLUE11_MASK 0x7c00 2352 2353 #define REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT 5 2354 #define REG_G3X_TOON_TABLE_5_H_GREEN11_SIZE 5 2355 #define REG_G3X_TOON_TABLE_5_H_GREEN11_MASK 0x03e0 2356 2357 #define REG_G3X_TOON_TABLE_5_H_RED11_SHIFT 0 2358 #define REG_G3X_TOON_TABLE_5_H_RED11_SIZE 5 2359 #define REG_G3X_TOON_TABLE_5_H_RED11_MASK 0x001f 2360 2361 #ifndef SDK_ASM 2362 #define REG_G3X_TOON_TABLE_5_H_FIELD( blue11, green11, red11 ) \ 2363 (u16)( \ 2364 ((u32)(blue11) << REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT) | \ 2365 ((u32)(green11) << REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT) | \ 2366 ((u32)(red11) << REG_G3X_TOON_TABLE_5_H_RED11_SHIFT)) 2367 #endif 2368 2369 2370 /* TOON_TABLE_6 */ 2371 2372 #define REG_G3X_TOON_TABLE_6_BLUE13_SHIFT 26 2373 #define REG_G3X_TOON_TABLE_6_BLUE13_SIZE 5 2374 #define REG_G3X_TOON_TABLE_6_BLUE13_MASK 0x7c000000 2375 2376 #define REG_G3X_TOON_TABLE_6_GREEN13_SHIFT 21 2377 #define REG_G3X_TOON_TABLE_6_GREEN13_SIZE 5 2378 #define REG_G3X_TOON_TABLE_6_GREEN13_MASK 0x03e00000 2379 2380 #define REG_G3X_TOON_TABLE_6_RED13_SHIFT 16 2381 #define REG_G3X_TOON_TABLE_6_RED13_SIZE 5 2382 #define REG_G3X_TOON_TABLE_6_RED13_MASK 0x001f0000 2383 2384 #define REG_G3X_TOON_TABLE_6_BLUE12_SHIFT 10 2385 #define REG_G3X_TOON_TABLE_6_BLUE12_SIZE 5 2386 #define REG_G3X_TOON_TABLE_6_BLUE12_MASK 0x00007c00 2387 2388 #define REG_G3X_TOON_TABLE_6_GREEN12_SHIFT 5 2389 #define REG_G3X_TOON_TABLE_6_GREEN12_SIZE 5 2390 #define REG_G3X_TOON_TABLE_6_GREEN12_MASK 0x000003e0 2391 2392 #define REG_G3X_TOON_TABLE_6_RED12_SHIFT 0 2393 #define REG_G3X_TOON_TABLE_6_RED12_SIZE 5 2394 #define REG_G3X_TOON_TABLE_6_RED12_MASK 0x0000001f 2395 2396 #ifndef SDK_ASM 2397 #define REG_G3X_TOON_TABLE_6_FIELD( blue13, green13, red13, blue12, green12, red12 ) \ 2398 (u32)( \ 2399 ((u32)(blue13) << REG_G3X_TOON_TABLE_6_BLUE13_SHIFT) | \ 2400 ((u32)(green13) << REG_G3X_TOON_TABLE_6_GREEN13_SHIFT) | \ 2401 ((u32)(red13) << REG_G3X_TOON_TABLE_6_RED13_SHIFT) | \ 2402 ((u32)(blue12) << REG_G3X_TOON_TABLE_6_BLUE12_SHIFT) | \ 2403 ((u32)(green12) << REG_G3X_TOON_TABLE_6_GREEN12_SHIFT) | \ 2404 ((u32)(red12) << REG_G3X_TOON_TABLE_6_RED12_SHIFT)) 2405 #endif 2406 2407 2408 /* TOON_TABLE_6_L */ 2409 2410 #define REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT 10 2411 #define REG_G3X_TOON_TABLE_6_L_BLUE12_SIZE 5 2412 #define REG_G3X_TOON_TABLE_6_L_BLUE12_MASK 0x7c00 2413 2414 #define REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT 5 2415 #define REG_G3X_TOON_TABLE_6_L_GREEN12_SIZE 5 2416 #define REG_G3X_TOON_TABLE_6_L_GREEN12_MASK 0x03e0 2417 2418 #define REG_G3X_TOON_TABLE_6_L_RED12_SHIFT 0 2419 #define REG_G3X_TOON_TABLE_6_L_RED12_SIZE 5 2420 #define REG_G3X_TOON_TABLE_6_L_RED12_MASK 0x001f 2421 2422 #ifndef SDK_ASM 2423 #define REG_G3X_TOON_TABLE_6_L_FIELD( blue12, green12, red12 ) \ 2424 (u16)( \ 2425 ((u32)(blue12) << REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT) | \ 2426 ((u32)(green12) << REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT) | \ 2427 ((u32)(red12) << REG_G3X_TOON_TABLE_6_L_RED12_SHIFT)) 2428 #endif 2429 2430 2431 /* TOON_TABLE_6_H */ 2432 2433 #define REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT 10 2434 #define REG_G3X_TOON_TABLE_6_H_BLUE13_SIZE 5 2435 #define REG_G3X_TOON_TABLE_6_H_BLUE13_MASK 0x7c00 2436 2437 #define REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT 5 2438 #define REG_G3X_TOON_TABLE_6_H_GREEN13_SIZE 5 2439 #define REG_G3X_TOON_TABLE_6_H_GREEN13_MASK 0x03e0 2440 2441 #define REG_G3X_TOON_TABLE_6_H_RED13_SHIFT 0 2442 #define REG_G3X_TOON_TABLE_6_H_RED13_SIZE 5 2443 #define REG_G3X_TOON_TABLE_6_H_RED13_MASK 0x001f 2444 2445 #ifndef SDK_ASM 2446 #define REG_G3X_TOON_TABLE_6_H_FIELD( blue13, green13, red13 ) \ 2447 (u16)( \ 2448 ((u32)(blue13) << REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT) | \ 2449 ((u32)(green13) << REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT) | \ 2450 ((u32)(red13) << REG_G3X_TOON_TABLE_6_H_RED13_SHIFT)) 2451 #endif 2452 2453 2454 /* TOON_TABLE_7 */ 2455 2456 #define REG_G3X_TOON_TABLE_7_BLUE15_SHIFT 26 2457 #define REG_G3X_TOON_TABLE_7_BLUE15_SIZE 5 2458 #define REG_G3X_TOON_TABLE_7_BLUE15_MASK 0x7c000000 2459 2460 #define REG_G3X_TOON_TABLE_7_GREEN15_SHIFT 21 2461 #define REG_G3X_TOON_TABLE_7_GREEN15_SIZE 5 2462 #define REG_G3X_TOON_TABLE_7_GREEN15_MASK 0x03e00000 2463 2464 #define REG_G3X_TOON_TABLE_7_RED15_SHIFT 16 2465 #define REG_G3X_TOON_TABLE_7_RED15_SIZE 5 2466 #define REG_G3X_TOON_TABLE_7_RED15_MASK 0x001f0000 2467 2468 #define REG_G3X_TOON_TABLE_7_BLUE14_SHIFT 10 2469 #define REG_G3X_TOON_TABLE_7_BLUE14_SIZE 5 2470 #define REG_G3X_TOON_TABLE_7_BLUE14_MASK 0x00007c00 2471 2472 #define REG_G3X_TOON_TABLE_7_GREEN14_SHIFT 5 2473 #define REG_G3X_TOON_TABLE_7_GREEN14_SIZE 5 2474 #define REG_G3X_TOON_TABLE_7_GREEN14_MASK 0x000003e0 2475 2476 #define REG_G3X_TOON_TABLE_7_RED14_SHIFT 0 2477 #define REG_G3X_TOON_TABLE_7_RED14_SIZE 5 2478 #define REG_G3X_TOON_TABLE_7_RED14_MASK 0x0000001f 2479 2480 #ifndef SDK_ASM 2481 #define REG_G3X_TOON_TABLE_7_FIELD( blue15, green15, red15, blue14, green14, red14 ) \ 2482 (u32)( \ 2483 ((u32)(blue15) << REG_G3X_TOON_TABLE_7_BLUE15_SHIFT) | \ 2484 ((u32)(green15) << REG_G3X_TOON_TABLE_7_GREEN15_SHIFT) | \ 2485 ((u32)(red15) << REG_G3X_TOON_TABLE_7_RED15_SHIFT) | \ 2486 ((u32)(blue14) << REG_G3X_TOON_TABLE_7_BLUE14_SHIFT) | \ 2487 ((u32)(green14) << REG_G3X_TOON_TABLE_7_GREEN14_SHIFT) | \ 2488 ((u32)(red14) << REG_G3X_TOON_TABLE_7_RED14_SHIFT)) 2489 #endif 2490 2491 2492 /* TOON_TABLE_7_L */ 2493 2494 #define REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT 10 2495 #define REG_G3X_TOON_TABLE_7_L_BLUE14_SIZE 5 2496 #define REG_G3X_TOON_TABLE_7_L_BLUE14_MASK 0x7c00 2497 2498 #define REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT 5 2499 #define REG_G3X_TOON_TABLE_7_L_GREEN14_SIZE 5 2500 #define REG_G3X_TOON_TABLE_7_L_GREEN14_MASK 0x03e0 2501 2502 #define REG_G3X_TOON_TABLE_7_L_RED14_SHIFT 0 2503 #define REG_G3X_TOON_TABLE_7_L_RED14_SIZE 5 2504 #define REG_G3X_TOON_TABLE_7_L_RED14_MASK 0x001f 2505 2506 #ifndef SDK_ASM 2507 #define REG_G3X_TOON_TABLE_7_L_FIELD( blue14, green14, red14 ) \ 2508 (u16)( \ 2509 ((u32)(blue14) << REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT) | \ 2510 ((u32)(green14) << REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT) | \ 2511 ((u32)(red14) << REG_G3X_TOON_TABLE_7_L_RED14_SHIFT)) 2512 #endif 2513 2514 2515 /* TOON_TABLE_7_H */ 2516 2517 #define REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT 10 2518 #define REG_G3X_TOON_TABLE_7_H_BLUE15_SIZE 5 2519 #define REG_G3X_TOON_TABLE_7_H_BLUE15_MASK 0x7c00 2520 2521 #define REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT 5 2522 #define REG_G3X_TOON_TABLE_7_H_GREEN15_SIZE 5 2523 #define REG_G3X_TOON_TABLE_7_H_GREEN15_MASK 0x03e0 2524 2525 #define REG_G3X_TOON_TABLE_7_H_RED15_SHIFT 0 2526 #define REG_G3X_TOON_TABLE_7_H_RED15_SIZE 5 2527 #define REG_G3X_TOON_TABLE_7_H_RED15_MASK 0x001f 2528 2529 #ifndef SDK_ASM 2530 #define REG_G3X_TOON_TABLE_7_H_FIELD( blue15, green15, red15 ) \ 2531 (u16)( \ 2532 ((u32)(blue15) << REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT) | \ 2533 ((u32)(green15) << REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT) | \ 2534 ((u32)(red15) << REG_G3X_TOON_TABLE_7_H_RED15_SHIFT)) 2535 #endif 2536 2537 2538 /* TOON_TABLE_8 */ 2539 2540 #define REG_G3X_TOON_TABLE_8_BLUE17_SHIFT 26 2541 #define REG_G3X_TOON_TABLE_8_BLUE17_SIZE 5 2542 #define REG_G3X_TOON_TABLE_8_BLUE17_MASK 0x7c000000 2543 2544 #define REG_G3X_TOON_TABLE_8_GREEN17_SHIFT 21 2545 #define REG_G3X_TOON_TABLE_8_GREEN17_SIZE 5 2546 #define REG_G3X_TOON_TABLE_8_GREEN17_MASK 0x03e00000 2547 2548 #define REG_G3X_TOON_TABLE_8_RED17_SHIFT 16 2549 #define REG_G3X_TOON_TABLE_8_RED17_SIZE 5 2550 #define REG_G3X_TOON_TABLE_8_RED17_MASK 0x001f0000 2551 2552 #define REG_G3X_TOON_TABLE_8_BLUE16_SHIFT 10 2553 #define REG_G3X_TOON_TABLE_8_BLUE16_SIZE 5 2554 #define REG_G3X_TOON_TABLE_8_BLUE16_MASK 0x00007c00 2555 2556 #define REG_G3X_TOON_TABLE_8_GREEN16_SHIFT 5 2557 #define REG_G3X_TOON_TABLE_8_GREEN16_SIZE 5 2558 #define REG_G3X_TOON_TABLE_8_GREEN16_MASK 0x000003e0 2559 2560 #define REG_G3X_TOON_TABLE_8_RED16_SHIFT 0 2561 #define REG_G3X_TOON_TABLE_8_RED16_SIZE 5 2562 #define REG_G3X_TOON_TABLE_8_RED16_MASK 0x0000001f 2563 2564 #ifndef SDK_ASM 2565 #define REG_G3X_TOON_TABLE_8_FIELD( blue17, green17, red17, blue16, green16, red16 ) \ 2566 (u32)( \ 2567 ((u32)(blue17) << REG_G3X_TOON_TABLE_8_BLUE17_SHIFT) | \ 2568 ((u32)(green17) << REG_G3X_TOON_TABLE_8_GREEN17_SHIFT) | \ 2569 ((u32)(red17) << REG_G3X_TOON_TABLE_8_RED17_SHIFT) | \ 2570 ((u32)(blue16) << REG_G3X_TOON_TABLE_8_BLUE16_SHIFT) | \ 2571 ((u32)(green16) << REG_G3X_TOON_TABLE_8_GREEN16_SHIFT) | \ 2572 ((u32)(red16) << REG_G3X_TOON_TABLE_8_RED16_SHIFT)) 2573 #endif 2574 2575 2576 /* TOON_TABLE_8_L */ 2577 2578 #define REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT 10 2579 #define REG_G3X_TOON_TABLE_8_L_BLUE16_SIZE 5 2580 #define REG_G3X_TOON_TABLE_8_L_BLUE16_MASK 0x7c00 2581 2582 #define REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT 5 2583 #define REG_G3X_TOON_TABLE_8_L_GREEN16_SIZE 5 2584 #define REG_G3X_TOON_TABLE_8_L_GREEN16_MASK 0x03e0 2585 2586 #define REG_G3X_TOON_TABLE_8_L_RED16_SHIFT 0 2587 #define REG_G3X_TOON_TABLE_8_L_RED16_SIZE 5 2588 #define REG_G3X_TOON_TABLE_8_L_RED16_MASK 0x001f 2589 2590 #ifndef SDK_ASM 2591 #define REG_G3X_TOON_TABLE_8_L_FIELD( blue16, green16, red16 ) \ 2592 (u16)( \ 2593 ((u32)(blue16) << REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT) | \ 2594 ((u32)(green16) << REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT) | \ 2595 ((u32)(red16) << REG_G3X_TOON_TABLE_8_L_RED16_SHIFT)) 2596 #endif 2597 2598 2599 /* TOON_TABLE_8_H */ 2600 2601 #define REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT 10 2602 #define REG_G3X_TOON_TABLE_8_H_BLUE17_SIZE 5 2603 #define REG_G3X_TOON_TABLE_8_H_BLUE17_MASK 0x7c00 2604 2605 #define REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT 5 2606 #define REG_G3X_TOON_TABLE_8_H_GREEN17_SIZE 5 2607 #define REG_G3X_TOON_TABLE_8_H_GREEN17_MASK 0x03e0 2608 2609 #define REG_G3X_TOON_TABLE_8_H_RED17_SHIFT 0 2610 #define REG_G3X_TOON_TABLE_8_H_RED17_SIZE 5 2611 #define REG_G3X_TOON_TABLE_8_H_RED17_MASK 0x001f 2612 2613 #ifndef SDK_ASM 2614 #define REG_G3X_TOON_TABLE_8_H_FIELD( blue17, green17, red17 ) \ 2615 (u16)( \ 2616 ((u32)(blue17) << REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT) | \ 2617 ((u32)(green17) << REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT) | \ 2618 ((u32)(red17) << REG_G3X_TOON_TABLE_8_H_RED17_SHIFT)) 2619 #endif 2620 2621 2622 /* TOON_TABLE_9 */ 2623 2624 #define REG_G3X_TOON_TABLE_9_BLUE19_SHIFT 26 2625 #define REG_G3X_TOON_TABLE_9_BLUE19_SIZE 5 2626 #define REG_G3X_TOON_TABLE_9_BLUE19_MASK 0x7c000000 2627 2628 #define REG_G3X_TOON_TABLE_9_GREEN19_SHIFT 21 2629 #define REG_G3X_TOON_TABLE_9_GREEN19_SIZE 5 2630 #define REG_G3X_TOON_TABLE_9_GREEN19_MASK 0x03e00000 2631 2632 #define REG_G3X_TOON_TABLE_9_RED19_SHIFT 16 2633 #define REG_G3X_TOON_TABLE_9_RED19_SIZE 5 2634 #define REG_G3X_TOON_TABLE_9_RED19_MASK 0x001f0000 2635 2636 #define REG_G3X_TOON_TABLE_9_BLUE18_SHIFT 10 2637 #define REG_G3X_TOON_TABLE_9_BLUE18_SIZE 5 2638 #define REG_G3X_TOON_TABLE_9_BLUE18_MASK 0x00007c00 2639 2640 #define REG_G3X_TOON_TABLE_9_GREEN18_SHIFT 5 2641 #define REG_G3X_TOON_TABLE_9_GREEN18_SIZE 5 2642 #define REG_G3X_TOON_TABLE_9_GREEN18_MASK 0x000003e0 2643 2644 #define REG_G3X_TOON_TABLE_9_RED18_SHIFT 0 2645 #define REG_G3X_TOON_TABLE_9_RED18_SIZE 5 2646 #define REG_G3X_TOON_TABLE_9_RED18_MASK 0x0000001f 2647 2648 #ifndef SDK_ASM 2649 #define REG_G3X_TOON_TABLE_9_FIELD( blue19, green19, red19, blue18, green18, red18 ) \ 2650 (u32)( \ 2651 ((u32)(blue19) << REG_G3X_TOON_TABLE_9_BLUE19_SHIFT) | \ 2652 ((u32)(green19) << REG_G3X_TOON_TABLE_9_GREEN19_SHIFT) | \ 2653 ((u32)(red19) << REG_G3X_TOON_TABLE_9_RED19_SHIFT) | \ 2654 ((u32)(blue18) << REG_G3X_TOON_TABLE_9_BLUE18_SHIFT) | \ 2655 ((u32)(green18) << REG_G3X_TOON_TABLE_9_GREEN18_SHIFT) | \ 2656 ((u32)(red18) << REG_G3X_TOON_TABLE_9_RED18_SHIFT)) 2657 #endif 2658 2659 2660 /* TOON_TABLE_9_L */ 2661 2662 #define REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT 10 2663 #define REG_G3X_TOON_TABLE_9_L_BLUE18_SIZE 5 2664 #define REG_G3X_TOON_TABLE_9_L_BLUE18_MASK 0x7c00 2665 2666 #define REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT 5 2667 #define REG_G3X_TOON_TABLE_9_L_GREEN18_SIZE 5 2668 #define REG_G3X_TOON_TABLE_9_L_GREEN18_MASK 0x03e0 2669 2670 #define REG_G3X_TOON_TABLE_9_L_RED18_SHIFT 0 2671 #define REG_G3X_TOON_TABLE_9_L_RED18_SIZE 5 2672 #define REG_G3X_TOON_TABLE_9_L_RED18_MASK 0x001f 2673 2674 #ifndef SDK_ASM 2675 #define REG_G3X_TOON_TABLE_9_L_FIELD( blue18, green18, red18 ) \ 2676 (u16)( \ 2677 ((u32)(blue18) << REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT) | \ 2678 ((u32)(green18) << REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT) | \ 2679 ((u32)(red18) << REG_G3X_TOON_TABLE_9_L_RED18_SHIFT)) 2680 #endif 2681 2682 2683 /* TOON_TABLE_9_H */ 2684 2685 #define REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT 10 2686 #define REG_G3X_TOON_TABLE_9_H_BLUE19_SIZE 5 2687 #define REG_G3X_TOON_TABLE_9_H_BLUE19_MASK 0x7c00 2688 2689 #define REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT 5 2690 #define REG_G3X_TOON_TABLE_9_H_GREEN19_SIZE 5 2691 #define REG_G3X_TOON_TABLE_9_H_GREEN19_MASK 0x03e0 2692 2693 #define REG_G3X_TOON_TABLE_9_H_RED19_SHIFT 0 2694 #define REG_G3X_TOON_TABLE_9_H_RED19_SIZE 5 2695 #define REG_G3X_TOON_TABLE_9_H_RED19_MASK 0x001f 2696 2697 #ifndef SDK_ASM 2698 #define REG_G3X_TOON_TABLE_9_H_FIELD( blue19, green19, red19 ) \ 2699 (u16)( \ 2700 ((u32)(blue19) << REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT) | \ 2701 ((u32)(green19) << REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT) | \ 2702 ((u32)(red19) << REG_G3X_TOON_TABLE_9_H_RED19_SHIFT)) 2703 #endif 2704 2705 2706 /* TOON_TABLE_10 */ 2707 2708 #define REG_G3X_TOON_TABLE_10_BLUE21_SHIFT 26 2709 #define REG_G3X_TOON_TABLE_10_BLUE21_SIZE 5 2710 #define REG_G3X_TOON_TABLE_10_BLUE21_MASK 0x7c000000 2711 2712 #define REG_G3X_TOON_TABLE_10_GREEN21_SHIFT 21 2713 #define REG_G3X_TOON_TABLE_10_GREEN21_SIZE 5 2714 #define REG_G3X_TOON_TABLE_10_GREEN21_MASK 0x03e00000 2715 2716 #define REG_G3X_TOON_TABLE_10_RED21_SHIFT 16 2717 #define REG_G3X_TOON_TABLE_10_RED21_SIZE 5 2718 #define REG_G3X_TOON_TABLE_10_RED21_MASK 0x001f0000 2719 2720 #define REG_G3X_TOON_TABLE_10_BLUE20_SHIFT 10 2721 #define REG_G3X_TOON_TABLE_10_BLUE20_SIZE 5 2722 #define REG_G3X_TOON_TABLE_10_BLUE20_MASK 0x00007c00 2723 2724 #define REG_G3X_TOON_TABLE_10_GREEN20_SHIFT 5 2725 #define REG_G3X_TOON_TABLE_10_GREEN20_SIZE 5 2726 #define REG_G3X_TOON_TABLE_10_GREEN20_MASK 0x000003e0 2727 2728 #define REG_G3X_TOON_TABLE_10_RED20_SHIFT 0 2729 #define REG_G3X_TOON_TABLE_10_RED20_SIZE 5 2730 #define REG_G3X_TOON_TABLE_10_RED20_MASK 0x0000001f 2731 2732 #ifndef SDK_ASM 2733 #define REG_G3X_TOON_TABLE_10_FIELD( blue21, green21, red21, blue20, green20, red20 ) \ 2734 (u32)( \ 2735 ((u32)(blue21) << REG_G3X_TOON_TABLE_10_BLUE21_SHIFT) | \ 2736 ((u32)(green21) << REG_G3X_TOON_TABLE_10_GREEN21_SHIFT) | \ 2737 ((u32)(red21) << REG_G3X_TOON_TABLE_10_RED21_SHIFT) | \ 2738 ((u32)(blue20) << REG_G3X_TOON_TABLE_10_BLUE20_SHIFT) | \ 2739 ((u32)(green20) << REG_G3X_TOON_TABLE_10_GREEN20_SHIFT) | \ 2740 ((u32)(red20) << REG_G3X_TOON_TABLE_10_RED20_SHIFT)) 2741 #endif 2742 2743 2744 /* TOON_TABLE_10_L */ 2745 2746 #define REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT 10 2747 #define REG_G3X_TOON_TABLE_10_L_BLUE20_SIZE 5 2748 #define REG_G3X_TOON_TABLE_10_L_BLUE20_MASK 0x7c00 2749 2750 #define REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT 5 2751 #define REG_G3X_TOON_TABLE_10_L_GREEN20_SIZE 5 2752 #define REG_G3X_TOON_TABLE_10_L_GREEN20_MASK 0x03e0 2753 2754 #define REG_G3X_TOON_TABLE_10_L_RED20_SHIFT 0 2755 #define REG_G3X_TOON_TABLE_10_L_RED20_SIZE 5 2756 #define REG_G3X_TOON_TABLE_10_L_RED20_MASK 0x001f 2757 2758 #ifndef SDK_ASM 2759 #define REG_G3X_TOON_TABLE_10_L_FIELD( blue20, green20, red20 ) \ 2760 (u16)( \ 2761 ((u32)(blue20) << REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT) | \ 2762 ((u32)(green20) << REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT) | \ 2763 ((u32)(red20) << REG_G3X_TOON_TABLE_10_L_RED20_SHIFT)) 2764 #endif 2765 2766 2767 /* TOON_TABLE_10_H */ 2768 2769 #define REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT 10 2770 #define REG_G3X_TOON_TABLE_10_H_BLUE21_SIZE 5 2771 #define REG_G3X_TOON_TABLE_10_H_BLUE21_MASK 0x7c00 2772 2773 #define REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT 5 2774 #define REG_G3X_TOON_TABLE_10_H_GREEN21_SIZE 5 2775 #define REG_G3X_TOON_TABLE_10_H_GREEN21_MASK 0x03e0 2776 2777 #define REG_G3X_TOON_TABLE_10_H_RED21_SHIFT 0 2778 #define REG_G3X_TOON_TABLE_10_H_RED21_SIZE 5 2779 #define REG_G3X_TOON_TABLE_10_H_RED21_MASK 0x001f 2780 2781 #ifndef SDK_ASM 2782 #define REG_G3X_TOON_TABLE_10_H_FIELD( blue21, green21, red21 ) \ 2783 (u16)( \ 2784 ((u32)(blue21) << REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT) | \ 2785 ((u32)(green21) << REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT) | \ 2786 ((u32)(red21) << REG_G3X_TOON_TABLE_10_H_RED21_SHIFT)) 2787 #endif 2788 2789 2790 /* TOON_TABLE_11 */ 2791 2792 #define REG_G3X_TOON_TABLE_11_BLUE23_SHIFT 26 2793 #define REG_G3X_TOON_TABLE_11_BLUE23_SIZE 5 2794 #define REG_G3X_TOON_TABLE_11_BLUE23_MASK 0x7c000000 2795 2796 #define REG_G3X_TOON_TABLE_11_GREEN23_SHIFT 21 2797 #define REG_G3X_TOON_TABLE_11_GREEN23_SIZE 5 2798 #define REG_G3X_TOON_TABLE_11_GREEN23_MASK 0x03e00000 2799 2800 #define REG_G3X_TOON_TABLE_11_RED23_SHIFT 16 2801 #define REG_G3X_TOON_TABLE_11_RED23_SIZE 5 2802 #define REG_G3X_TOON_TABLE_11_RED23_MASK 0x001f0000 2803 2804 #define REG_G3X_TOON_TABLE_11_BLUE22_SHIFT 10 2805 #define REG_G3X_TOON_TABLE_11_BLUE22_SIZE 5 2806 #define REG_G3X_TOON_TABLE_11_BLUE22_MASK 0x00007c00 2807 2808 #define REG_G3X_TOON_TABLE_11_GREEN22_SHIFT 5 2809 #define REG_G3X_TOON_TABLE_11_GREEN22_SIZE 5 2810 #define REG_G3X_TOON_TABLE_11_GREEN22_MASK 0x000003e0 2811 2812 #define REG_G3X_TOON_TABLE_11_RED22_SHIFT 0 2813 #define REG_G3X_TOON_TABLE_11_RED22_SIZE 5 2814 #define REG_G3X_TOON_TABLE_11_RED22_MASK 0x0000001f 2815 2816 #ifndef SDK_ASM 2817 #define REG_G3X_TOON_TABLE_11_FIELD( blue23, green23, red23, blue22, green22, red22 ) \ 2818 (u32)( \ 2819 ((u32)(blue23) << REG_G3X_TOON_TABLE_11_BLUE23_SHIFT) | \ 2820 ((u32)(green23) << REG_G3X_TOON_TABLE_11_GREEN23_SHIFT) | \ 2821 ((u32)(red23) << REG_G3X_TOON_TABLE_11_RED23_SHIFT) | \ 2822 ((u32)(blue22) << REG_G3X_TOON_TABLE_11_BLUE22_SHIFT) | \ 2823 ((u32)(green22) << REG_G3X_TOON_TABLE_11_GREEN22_SHIFT) | \ 2824 ((u32)(red22) << REG_G3X_TOON_TABLE_11_RED22_SHIFT)) 2825 #endif 2826 2827 2828 /* TOON_TABLE_11_L */ 2829 2830 #define REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT 10 2831 #define REG_G3X_TOON_TABLE_11_L_BLUE22_SIZE 5 2832 #define REG_G3X_TOON_TABLE_11_L_BLUE22_MASK 0x7c00 2833 2834 #define REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT 5 2835 #define REG_G3X_TOON_TABLE_11_L_GREEN22_SIZE 5 2836 #define REG_G3X_TOON_TABLE_11_L_GREEN22_MASK 0x03e0 2837 2838 #define REG_G3X_TOON_TABLE_11_L_RED22_SHIFT 0 2839 #define REG_G3X_TOON_TABLE_11_L_RED22_SIZE 5 2840 #define REG_G3X_TOON_TABLE_11_L_RED22_MASK 0x001f 2841 2842 #ifndef SDK_ASM 2843 #define REG_G3X_TOON_TABLE_11_L_FIELD( blue22, green22, red22 ) \ 2844 (u16)( \ 2845 ((u32)(blue22) << REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT) | \ 2846 ((u32)(green22) << REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT) | \ 2847 ((u32)(red22) << REG_G3X_TOON_TABLE_11_L_RED22_SHIFT)) 2848 #endif 2849 2850 2851 /* TOON_TABLE_11_H */ 2852 2853 #define REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT 10 2854 #define REG_G3X_TOON_TABLE_11_H_BLUE23_SIZE 5 2855 #define REG_G3X_TOON_TABLE_11_H_BLUE23_MASK 0x7c00 2856 2857 #define REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT 5 2858 #define REG_G3X_TOON_TABLE_11_H_GREEN23_SIZE 5 2859 #define REG_G3X_TOON_TABLE_11_H_GREEN23_MASK 0x03e0 2860 2861 #define REG_G3X_TOON_TABLE_11_H_RED23_SHIFT 0 2862 #define REG_G3X_TOON_TABLE_11_H_RED23_SIZE 5 2863 #define REG_G3X_TOON_TABLE_11_H_RED23_MASK 0x001f 2864 2865 #ifndef SDK_ASM 2866 #define REG_G3X_TOON_TABLE_11_H_FIELD( blue23, green23, red23 ) \ 2867 (u16)( \ 2868 ((u32)(blue23) << REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT) | \ 2869 ((u32)(green23) << REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT) | \ 2870 ((u32)(red23) << REG_G3X_TOON_TABLE_11_H_RED23_SHIFT)) 2871 #endif 2872 2873 2874 /* TOON_TABLE_12 */ 2875 2876 #define REG_G3X_TOON_TABLE_12_BLUE25_SHIFT 26 2877 #define REG_G3X_TOON_TABLE_12_BLUE25_SIZE 5 2878 #define REG_G3X_TOON_TABLE_12_BLUE25_MASK 0x7c000000 2879 2880 #define REG_G3X_TOON_TABLE_12_GREEN25_SHIFT 21 2881 #define REG_G3X_TOON_TABLE_12_GREEN25_SIZE 5 2882 #define REG_G3X_TOON_TABLE_12_GREEN25_MASK 0x03e00000 2883 2884 #define REG_G3X_TOON_TABLE_12_RED25_SHIFT 16 2885 #define REG_G3X_TOON_TABLE_12_RED25_SIZE 5 2886 #define REG_G3X_TOON_TABLE_12_RED25_MASK 0x001f0000 2887 2888 #define REG_G3X_TOON_TABLE_12_BLUE24_SHIFT 10 2889 #define REG_G3X_TOON_TABLE_12_BLUE24_SIZE 5 2890 #define REG_G3X_TOON_TABLE_12_BLUE24_MASK 0x00007c00 2891 2892 #define REG_G3X_TOON_TABLE_12_GREEN24_SHIFT 5 2893 #define REG_G3X_TOON_TABLE_12_GREEN24_SIZE 5 2894 #define REG_G3X_TOON_TABLE_12_GREEN24_MASK 0x000003e0 2895 2896 #define REG_G3X_TOON_TABLE_12_RED24_SHIFT 0 2897 #define REG_G3X_TOON_TABLE_12_RED24_SIZE 5 2898 #define REG_G3X_TOON_TABLE_12_RED24_MASK 0x0000001f 2899 2900 #ifndef SDK_ASM 2901 #define REG_G3X_TOON_TABLE_12_FIELD( blue25, green25, red25, blue24, green24, red24 ) \ 2902 (u32)( \ 2903 ((u32)(blue25) << REG_G3X_TOON_TABLE_12_BLUE25_SHIFT) | \ 2904 ((u32)(green25) << REG_G3X_TOON_TABLE_12_GREEN25_SHIFT) | \ 2905 ((u32)(red25) << REG_G3X_TOON_TABLE_12_RED25_SHIFT) | \ 2906 ((u32)(blue24) << REG_G3X_TOON_TABLE_12_BLUE24_SHIFT) | \ 2907 ((u32)(green24) << REG_G3X_TOON_TABLE_12_GREEN24_SHIFT) | \ 2908 ((u32)(red24) << REG_G3X_TOON_TABLE_12_RED24_SHIFT)) 2909 #endif 2910 2911 2912 /* TOON_TABLE_12_L */ 2913 2914 #define REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT 10 2915 #define REG_G3X_TOON_TABLE_12_L_BLUE24_SIZE 5 2916 #define REG_G3X_TOON_TABLE_12_L_BLUE24_MASK 0x7c00 2917 2918 #define REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT 5 2919 #define REG_G3X_TOON_TABLE_12_L_GREEN24_SIZE 5 2920 #define REG_G3X_TOON_TABLE_12_L_GREEN24_MASK 0x03e0 2921 2922 #define REG_G3X_TOON_TABLE_12_L_RED24_SHIFT 0 2923 #define REG_G3X_TOON_TABLE_12_L_RED24_SIZE 5 2924 #define REG_G3X_TOON_TABLE_12_L_RED24_MASK 0x001f 2925 2926 #ifndef SDK_ASM 2927 #define REG_G3X_TOON_TABLE_12_L_FIELD( blue24, green24, red24 ) \ 2928 (u16)( \ 2929 ((u32)(blue24) << REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT) | \ 2930 ((u32)(green24) << REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT) | \ 2931 ((u32)(red24) << REG_G3X_TOON_TABLE_12_L_RED24_SHIFT)) 2932 #endif 2933 2934 2935 /* TOON_TABLE_12_H */ 2936 2937 #define REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT 10 2938 #define REG_G3X_TOON_TABLE_12_H_BLUE25_SIZE 5 2939 #define REG_G3X_TOON_TABLE_12_H_BLUE25_MASK 0x7c00 2940 2941 #define REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT 5 2942 #define REG_G3X_TOON_TABLE_12_H_GREEN25_SIZE 5 2943 #define REG_G3X_TOON_TABLE_12_H_GREEN25_MASK 0x03e0 2944 2945 #define REG_G3X_TOON_TABLE_12_H_RED25_SHIFT 0 2946 #define REG_G3X_TOON_TABLE_12_H_RED25_SIZE 5 2947 #define REG_G3X_TOON_TABLE_12_H_RED25_MASK 0x001f 2948 2949 #ifndef SDK_ASM 2950 #define REG_G3X_TOON_TABLE_12_H_FIELD( blue25, green25, red25 ) \ 2951 (u16)( \ 2952 ((u32)(blue25) << REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT) | \ 2953 ((u32)(green25) << REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT) | \ 2954 ((u32)(red25) << REG_G3X_TOON_TABLE_12_H_RED25_SHIFT)) 2955 #endif 2956 2957 2958 /* TOON_TABLE_13 */ 2959 2960 #define REG_G3X_TOON_TABLE_13_BLUE27_SHIFT 26 2961 #define REG_G3X_TOON_TABLE_13_BLUE27_SIZE 5 2962 #define REG_G3X_TOON_TABLE_13_BLUE27_MASK 0x7c000000 2963 2964 #define REG_G3X_TOON_TABLE_13_GREEN27_SHIFT 21 2965 #define REG_G3X_TOON_TABLE_13_GREEN27_SIZE 5 2966 #define REG_G3X_TOON_TABLE_13_GREEN27_MASK 0x03e00000 2967 2968 #define REG_G3X_TOON_TABLE_13_RED27_SHIFT 16 2969 #define REG_G3X_TOON_TABLE_13_RED27_SIZE 5 2970 #define REG_G3X_TOON_TABLE_13_RED27_MASK 0x001f0000 2971 2972 #define REG_G3X_TOON_TABLE_13_BLUE26_SHIFT 10 2973 #define REG_G3X_TOON_TABLE_13_BLUE26_SIZE 5 2974 #define REG_G3X_TOON_TABLE_13_BLUE26_MASK 0x00007c00 2975 2976 #define REG_G3X_TOON_TABLE_13_GREEN26_SHIFT 5 2977 #define REG_G3X_TOON_TABLE_13_GREEN26_SIZE 5 2978 #define REG_G3X_TOON_TABLE_13_GREEN26_MASK 0x000003e0 2979 2980 #define REG_G3X_TOON_TABLE_13_RED26_SHIFT 0 2981 #define REG_G3X_TOON_TABLE_13_RED26_SIZE 5 2982 #define REG_G3X_TOON_TABLE_13_RED26_MASK 0x0000001f 2983 2984 #ifndef SDK_ASM 2985 #define REG_G3X_TOON_TABLE_13_FIELD( blue27, green27, red27, blue26, green26, red26 ) \ 2986 (u32)( \ 2987 ((u32)(blue27) << REG_G3X_TOON_TABLE_13_BLUE27_SHIFT) | \ 2988 ((u32)(green27) << REG_G3X_TOON_TABLE_13_GREEN27_SHIFT) | \ 2989 ((u32)(red27) << REG_G3X_TOON_TABLE_13_RED27_SHIFT) | \ 2990 ((u32)(blue26) << REG_G3X_TOON_TABLE_13_BLUE26_SHIFT) | \ 2991 ((u32)(green26) << REG_G3X_TOON_TABLE_13_GREEN26_SHIFT) | \ 2992 ((u32)(red26) << REG_G3X_TOON_TABLE_13_RED26_SHIFT)) 2993 #endif 2994 2995 2996 /* TOON_TABLE_13_L */ 2997 2998 #define REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT 10 2999 #define REG_G3X_TOON_TABLE_13_L_BLUE26_SIZE 5 3000 #define REG_G3X_TOON_TABLE_13_L_BLUE26_MASK 0x7c00 3001 3002 #define REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT 5 3003 #define REG_G3X_TOON_TABLE_13_L_GREEN26_SIZE 5 3004 #define REG_G3X_TOON_TABLE_13_L_GREEN26_MASK 0x03e0 3005 3006 #define REG_G3X_TOON_TABLE_13_L_RED26_SHIFT 0 3007 #define REG_G3X_TOON_TABLE_13_L_RED26_SIZE 5 3008 #define REG_G3X_TOON_TABLE_13_L_RED26_MASK 0x001f 3009 3010 #ifndef SDK_ASM 3011 #define REG_G3X_TOON_TABLE_13_L_FIELD( blue26, green26, red26 ) \ 3012 (u16)( \ 3013 ((u32)(blue26) << REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT) | \ 3014 ((u32)(green26) << REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT) | \ 3015 ((u32)(red26) << REG_G3X_TOON_TABLE_13_L_RED26_SHIFT)) 3016 #endif 3017 3018 3019 /* TOON_TABLE_13_H */ 3020 3021 #define REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT 10 3022 #define REG_G3X_TOON_TABLE_13_H_BLUE27_SIZE 5 3023 #define REG_G3X_TOON_TABLE_13_H_BLUE27_MASK 0x7c00 3024 3025 #define REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT 5 3026 #define REG_G3X_TOON_TABLE_13_H_GREEN27_SIZE 5 3027 #define REG_G3X_TOON_TABLE_13_H_GREEN27_MASK 0x03e0 3028 3029 #define REG_G3X_TOON_TABLE_13_H_RED27_SHIFT 0 3030 #define REG_G3X_TOON_TABLE_13_H_RED27_SIZE 5 3031 #define REG_G3X_TOON_TABLE_13_H_RED27_MASK 0x001f 3032 3033 #ifndef SDK_ASM 3034 #define REG_G3X_TOON_TABLE_13_H_FIELD( blue27, green27, red27 ) \ 3035 (u16)( \ 3036 ((u32)(blue27) << REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT) | \ 3037 ((u32)(green27) << REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT) | \ 3038 ((u32)(red27) << REG_G3X_TOON_TABLE_13_H_RED27_SHIFT)) 3039 #endif 3040 3041 3042 /* TOON_TABLE_14 */ 3043 3044 #define REG_G3X_TOON_TABLE_14_BLUE29_SHIFT 26 3045 #define REG_G3X_TOON_TABLE_14_BLUE29_SIZE 5 3046 #define REG_G3X_TOON_TABLE_14_BLUE29_MASK 0x7c000000 3047 3048 #define REG_G3X_TOON_TABLE_14_GREEN29_SHIFT 21 3049 #define REG_G3X_TOON_TABLE_14_GREEN29_SIZE 5 3050 #define REG_G3X_TOON_TABLE_14_GREEN29_MASK 0x03e00000 3051 3052 #define REG_G3X_TOON_TABLE_14_RED29_SHIFT 16 3053 #define REG_G3X_TOON_TABLE_14_RED29_SIZE 5 3054 #define REG_G3X_TOON_TABLE_14_RED29_MASK 0x001f0000 3055 3056 #define REG_G3X_TOON_TABLE_14_BLUE28_SHIFT 10 3057 #define REG_G3X_TOON_TABLE_14_BLUE28_SIZE 5 3058 #define REG_G3X_TOON_TABLE_14_BLUE28_MASK 0x00007c00 3059 3060 #define REG_G3X_TOON_TABLE_14_GREEN28_SHIFT 5 3061 #define REG_G3X_TOON_TABLE_14_GREEN28_SIZE 5 3062 #define REG_G3X_TOON_TABLE_14_GREEN28_MASK 0x000003e0 3063 3064 #define REG_G3X_TOON_TABLE_14_RED28_SHIFT 0 3065 #define REG_G3X_TOON_TABLE_14_RED28_SIZE 5 3066 #define REG_G3X_TOON_TABLE_14_RED28_MASK 0x0000001f 3067 3068 #ifndef SDK_ASM 3069 #define REG_G3X_TOON_TABLE_14_FIELD( blue29, green29, red29, blue28, green28, red28 ) \ 3070 (u32)( \ 3071 ((u32)(blue29) << REG_G3X_TOON_TABLE_14_BLUE29_SHIFT) | \ 3072 ((u32)(green29) << REG_G3X_TOON_TABLE_14_GREEN29_SHIFT) | \ 3073 ((u32)(red29) << REG_G3X_TOON_TABLE_14_RED29_SHIFT) | \ 3074 ((u32)(blue28) << REG_G3X_TOON_TABLE_14_BLUE28_SHIFT) | \ 3075 ((u32)(green28) << REG_G3X_TOON_TABLE_14_GREEN28_SHIFT) | \ 3076 ((u32)(red28) << REG_G3X_TOON_TABLE_14_RED28_SHIFT)) 3077 #endif 3078 3079 3080 /* TOON_TABLE_14_L */ 3081 3082 #define REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT 10 3083 #define REG_G3X_TOON_TABLE_14_L_BLUE28_SIZE 5 3084 #define REG_G3X_TOON_TABLE_14_L_BLUE28_MASK 0x7c00 3085 3086 #define REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT 5 3087 #define REG_G3X_TOON_TABLE_14_L_GREEN28_SIZE 5 3088 #define REG_G3X_TOON_TABLE_14_L_GREEN28_MASK 0x03e0 3089 3090 #define REG_G3X_TOON_TABLE_14_L_RED28_SHIFT 0 3091 #define REG_G3X_TOON_TABLE_14_L_RED28_SIZE 5 3092 #define REG_G3X_TOON_TABLE_14_L_RED28_MASK 0x001f 3093 3094 #ifndef SDK_ASM 3095 #define REG_G3X_TOON_TABLE_14_L_FIELD( blue28, green28, red28 ) \ 3096 (u16)( \ 3097 ((u32)(blue28) << REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT) | \ 3098 ((u32)(green28) << REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT) | \ 3099 ((u32)(red28) << REG_G3X_TOON_TABLE_14_L_RED28_SHIFT)) 3100 #endif 3101 3102 3103 /* TOON_TABLE_14_H */ 3104 3105 #define REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT 10 3106 #define REG_G3X_TOON_TABLE_14_H_BLUE29_SIZE 5 3107 #define REG_G3X_TOON_TABLE_14_H_BLUE29_MASK 0x7c00 3108 3109 #define REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT 5 3110 #define REG_G3X_TOON_TABLE_14_H_GREEN29_SIZE 5 3111 #define REG_G3X_TOON_TABLE_14_H_GREEN29_MASK 0x03e0 3112 3113 #define REG_G3X_TOON_TABLE_14_H_RED29_SHIFT 0 3114 #define REG_G3X_TOON_TABLE_14_H_RED29_SIZE 5 3115 #define REG_G3X_TOON_TABLE_14_H_RED29_MASK 0x001f 3116 3117 #ifndef SDK_ASM 3118 #define REG_G3X_TOON_TABLE_14_H_FIELD( blue29, green29, red29 ) \ 3119 (u16)( \ 3120 ((u32)(blue29) << REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT) | \ 3121 ((u32)(green29) << REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT) | \ 3122 ((u32)(red29) << REG_G3X_TOON_TABLE_14_H_RED29_SHIFT)) 3123 #endif 3124 3125 3126 /* TOON_TABLE_15 */ 3127 3128 #define REG_G3X_TOON_TABLE_15_BLUE31_SHIFT 26 3129 #define REG_G3X_TOON_TABLE_15_BLUE31_SIZE 5 3130 #define REG_G3X_TOON_TABLE_15_BLUE31_MASK 0x7c000000 3131 3132 #define REG_G3X_TOON_TABLE_15_GREEN31_SHIFT 21 3133 #define REG_G3X_TOON_TABLE_15_GREEN31_SIZE 5 3134 #define REG_G3X_TOON_TABLE_15_GREEN31_MASK 0x03e00000 3135 3136 #define REG_G3X_TOON_TABLE_15_RED31_SHIFT 16 3137 #define REG_G3X_TOON_TABLE_15_RED31_SIZE 5 3138 #define REG_G3X_TOON_TABLE_15_RED31_MASK 0x001f0000 3139 3140 #define REG_G3X_TOON_TABLE_15_BLUE30_SHIFT 10 3141 #define REG_G3X_TOON_TABLE_15_BLUE30_SIZE 5 3142 #define REG_G3X_TOON_TABLE_15_BLUE30_MASK 0x00007c00 3143 3144 #define REG_G3X_TOON_TABLE_15_GREEN30_SHIFT 5 3145 #define REG_G3X_TOON_TABLE_15_GREEN30_SIZE 5 3146 #define REG_G3X_TOON_TABLE_15_GREEN30_MASK 0x000003e0 3147 3148 #define REG_G3X_TOON_TABLE_15_RED30_SHIFT 0 3149 #define REG_G3X_TOON_TABLE_15_RED30_SIZE 5 3150 #define REG_G3X_TOON_TABLE_15_RED30_MASK 0x0000001f 3151 3152 #ifndef SDK_ASM 3153 #define REG_G3X_TOON_TABLE_15_FIELD( blue31, green31, red31, blue30, green30, red30 ) \ 3154 (u32)( \ 3155 ((u32)(blue31) << REG_G3X_TOON_TABLE_15_BLUE31_SHIFT) | \ 3156 ((u32)(green31) << REG_G3X_TOON_TABLE_15_GREEN31_SHIFT) | \ 3157 ((u32)(red31) << REG_G3X_TOON_TABLE_15_RED31_SHIFT) | \ 3158 ((u32)(blue30) << REG_G3X_TOON_TABLE_15_BLUE30_SHIFT) | \ 3159 ((u32)(green30) << REG_G3X_TOON_TABLE_15_GREEN30_SHIFT) | \ 3160 ((u32)(red30) << REG_G3X_TOON_TABLE_15_RED30_SHIFT)) 3161 #endif 3162 3163 3164 /* TOON_TABLE_15_L */ 3165 3166 #define REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT 10 3167 #define REG_G3X_TOON_TABLE_15_L_BLUE30_SIZE 5 3168 #define REG_G3X_TOON_TABLE_15_L_BLUE30_MASK 0x7c00 3169 3170 #define REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT 5 3171 #define REG_G3X_TOON_TABLE_15_L_GREEN30_SIZE 5 3172 #define REG_G3X_TOON_TABLE_15_L_GREEN30_MASK 0x03e0 3173 3174 #define REG_G3X_TOON_TABLE_15_L_RED30_SHIFT 0 3175 #define REG_G3X_TOON_TABLE_15_L_RED30_SIZE 5 3176 #define REG_G3X_TOON_TABLE_15_L_RED30_MASK 0x001f 3177 3178 #ifndef SDK_ASM 3179 #define REG_G3X_TOON_TABLE_15_L_FIELD( blue30, green30, red30 ) \ 3180 (u16)( \ 3181 ((u32)(blue30) << REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT) | \ 3182 ((u32)(green30) << REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT) | \ 3183 ((u32)(red30) << REG_G3X_TOON_TABLE_15_L_RED30_SHIFT)) 3184 #endif 3185 3186 3187 /* TOON_TABLE_15_H */ 3188 3189 #define REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT 10 3190 #define REG_G3X_TOON_TABLE_15_H_BLUE31_SIZE 5 3191 #define REG_G3X_TOON_TABLE_15_H_BLUE31_MASK 0x7c00 3192 3193 #define REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT 5 3194 #define REG_G3X_TOON_TABLE_15_H_GREEN31_SIZE 5 3195 #define REG_G3X_TOON_TABLE_15_H_GREEN31_MASK 0x03e0 3196 3197 #define REG_G3X_TOON_TABLE_15_H_RED31_SHIFT 0 3198 #define REG_G3X_TOON_TABLE_15_H_RED31_SIZE 5 3199 #define REG_G3X_TOON_TABLE_15_H_RED31_MASK 0x001f 3200 3201 #ifndef SDK_ASM 3202 #define REG_G3X_TOON_TABLE_15_H_FIELD( blue31, green31, red31 ) \ 3203 (u16)( \ 3204 ((u32)(blue31) << REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT) | \ 3205 ((u32)(green31) << REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT) | \ 3206 ((u32)(red31) << REG_G3X_TOON_TABLE_15_H_RED31_SHIFT)) 3207 #endif 3208 3209 3210 /* GXFIFO */ 3211 3212 /* GXSTAT */ 3213 3214 #define REG_G3X_GXSTAT_FI_SHIFT 30 3215 #define REG_G3X_GXSTAT_FI_SIZE 2 3216 #define REG_G3X_GXSTAT_FI_MASK 0xc0000000 3217 3218 #define REG_G3X_GXSTAT_B_SHIFT 27 3219 #define REG_G3X_GXSTAT_B_SIZE 1 3220 #define REG_G3X_GXSTAT_B_MASK 0x08000000 3221 3222 #define REG_G3X_GXSTAT_E_SHIFT 26 3223 #define REG_G3X_GXSTAT_E_SIZE 1 3224 #define REG_G3X_GXSTAT_E_MASK 0x04000000 3225 3226 #define REG_G3X_GXSTAT_H_SHIFT 25 3227 #define REG_G3X_GXSTAT_H_SIZE 1 3228 #define REG_G3X_GXSTAT_H_MASK 0x02000000 3229 3230 #define REG_G3X_GXSTAT_F_SHIFT 24 3231 #define REG_G3X_GXSTAT_F_SIZE 1 3232 #define REG_G3X_GXSTAT_F_MASK 0x01000000 3233 3234 #define REG_G3X_GXSTAT_FIFOCNT_SHIFT 16 3235 #define REG_G3X_GXSTAT_FIFOCNT_SIZE 8 3236 #define REG_G3X_GXSTAT_FIFOCNT_MASK 0x00ff0000 3237 3238 #define REG_G3X_GXSTAT_SE_SHIFT 15 3239 #define REG_G3X_GXSTAT_SE_SIZE 1 3240 #define REG_G3X_GXSTAT_SE_MASK 0x00008000 3241 3242 #define REG_G3X_GXSTAT_SB_SHIFT 14 3243 #define REG_G3X_GXSTAT_SB_SIZE 1 3244 #define REG_G3X_GXSTAT_SB_MASK 0x00004000 3245 3246 #define REG_G3X_GXSTAT_PJ_SHIFT 13 3247 #define REG_G3X_GXSTAT_PJ_SIZE 1 3248 #define REG_G3X_GXSTAT_PJ_MASK 0x00002000 3249 3250 #define REG_G3X_GXSTAT_PV_SHIFT 8 3251 #define REG_G3X_GXSTAT_PV_SIZE 5 3252 #define REG_G3X_GXSTAT_PV_MASK 0x00001f00 3253 3254 #define REG_G3X_GXSTAT_TR_SHIFT 1 3255 #define REG_G3X_GXSTAT_TR_SIZE 1 3256 #define REG_G3X_GXSTAT_TR_MASK 0x00000002 3257 3258 #define REG_G3X_GXSTAT_TB_SHIFT 0 3259 #define REG_G3X_GXSTAT_TB_SIZE 1 3260 #define REG_G3X_GXSTAT_TB_MASK 0x00000001 3261 3262 #ifndef SDK_ASM 3263 #define REG_G3X_GXSTAT_FIELD( fi, b, e, h, f, fifocnt, se, sb, pj, pv, tr, tb ) \ 3264 (u32)( \ 3265 ((u32)(fi) << REG_G3X_GXSTAT_FI_SHIFT) | \ 3266 ((u32)(b) << REG_G3X_GXSTAT_B_SHIFT) | \ 3267 ((u32)(e) << REG_G3X_GXSTAT_E_SHIFT) | \ 3268 ((u32)(h) << REG_G3X_GXSTAT_H_SHIFT) | \ 3269 ((u32)(f) << REG_G3X_GXSTAT_F_SHIFT) | \ 3270 ((u32)(fifocnt) << REG_G3X_GXSTAT_FIFOCNT_SHIFT) | \ 3271 ((u32)(se) << REG_G3X_GXSTAT_SE_SHIFT) | \ 3272 ((u32)(sb) << REG_G3X_GXSTAT_SB_SHIFT) | \ 3273 ((u32)(pj) << REG_G3X_GXSTAT_PJ_SHIFT) | \ 3274 ((u32)(pv) << REG_G3X_GXSTAT_PV_SHIFT) | \ 3275 ((u32)(tr) << REG_G3X_GXSTAT_TR_SHIFT) | \ 3276 ((u32)(tb) << REG_G3X_GXSTAT_TB_SHIFT)) 3277 #endif 3278 3279 3280 /* LISTRAM_COUNT */ 3281 3282 #define REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT 0 3283 #define REG_G3X_LISTRAM_COUNT_RAMCNT_SIZE 12 3284 #define REG_G3X_LISTRAM_COUNT_RAMCNT_MASK 0x0fff 3285 3286 #ifndef SDK_ASM 3287 #define REG_G3X_LISTRAM_COUNT_FIELD( ramcnt ) \ 3288 (u16)( \ 3289 ((u32)(ramcnt) << REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT)) 3290 #endif 3291 3292 3293 /* VTXRAM_COUNT */ 3294 3295 #define REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT 0 3296 #define REG_G3X_VTXRAM_COUNT_VTXCNT_SIZE 13 3297 #define REG_G3X_VTXRAM_COUNT_VTXCNT_MASK 0x1fff 3298 3299 #ifndef SDK_ASM 3300 #define REG_G3X_VTXRAM_COUNT_FIELD( vtxcnt ) \ 3301 (u16)( \ 3302 ((u32)(vtxcnt) << REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT)) 3303 #endif 3304 3305 3306 /* DISP_1DOT_DEPTH */ 3307 3308 #define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT 3 3309 #define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SIZE 12 3310 #define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_MASK 0x7ff8 3311 3312 #define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT 0 3313 #define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SIZE 3 3314 #define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_MASK 0x0007 3315 3316 #ifndef SDK_ASM 3317 #define REG_G3X_DISP_1DOT_DEPTH_FIELD( integer_w, decimal_w ) \ 3318 (u16)( \ 3319 ((u32)(integer_w) << REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT) | \ 3320 ((u32)(decimal_w) << REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT)) 3321 #endif 3322 3323 3324 /* POS_RESULT_X */ 3325 3326 #define REG_G3X_POS_RESULT_X_SX_SHIFT 31 3327 #define REG_G3X_POS_RESULT_X_SX_SIZE 1 3328 #define REG_G3X_POS_RESULT_X_SX_MASK 0x80000000 3329 3330 #define REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT 12 3331 #define REG_G3X_POS_RESULT_X_INTEGER_X_SIZE 19 3332 #define REG_G3X_POS_RESULT_X_INTEGER_X_MASK 0x7ffff000 3333 3334 #define REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT 0 3335 #define REG_G3X_POS_RESULT_X_DECIMAL_X_SIZE 12 3336 #define REG_G3X_POS_RESULT_X_DECIMAL_X_MASK 0x00000fff 3337 3338 #ifndef SDK_ASM 3339 #define REG_G3X_POS_RESULT_X_FIELD( sx, integer_x, decimal_x ) \ 3340 (u32)( \ 3341 ((u32)(sx) << REG_G3X_POS_RESULT_X_SX_SHIFT) | \ 3342 ((u32)(integer_x) << REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT) | \ 3343 ((u32)(decimal_x) << REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT)) 3344 #endif 3345 3346 3347 /* POS_RESULT_Y */ 3348 3349 #define REG_G3X_POS_RESULT_Y_SY_SHIFT 31 3350 #define REG_G3X_POS_RESULT_Y_SY_SIZE 1 3351 #define REG_G3X_POS_RESULT_Y_SY_MASK 0x80000000 3352 3353 #define REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT 12 3354 #define REG_G3X_POS_RESULT_Y_INTEGER_Y_SIZE 19 3355 #define REG_G3X_POS_RESULT_Y_INTEGER_Y_MASK 0x7ffff000 3356 3357 #define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT 0 3358 #define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SIZE 12 3359 #define REG_G3X_POS_RESULT_Y_DECIMAL_Y_MASK 0x00000fff 3360 3361 #ifndef SDK_ASM 3362 #define REG_G3X_POS_RESULT_Y_FIELD( sy, integer_y, decimal_y ) \ 3363 (u32)( \ 3364 ((u32)(sy) << REG_G3X_POS_RESULT_Y_SY_SHIFT) | \ 3365 ((u32)(integer_y) << REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT) | \ 3366 ((u32)(decimal_y) << REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT)) 3367 #endif 3368 3369 3370 /* POS_RESULT_Z */ 3371 3372 #define REG_G3X_POS_RESULT_Z_SZ_SHIFT 31 3373 #define REG_G3X_POS_RESULT_Z_SZ_SIZE 1 3374 #define REG_G3X_POS_RESULT_Z_SZ_MASK 0x80000000 3375 3376 #define REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT 12 3377 #define REG_G3X_POS_RESULT_Z_INTEGER_Z_SIZE 19 3378 #define REG_G3X_POS_RESULT_Z_INTEGER_Z_MASK 0x7ffff000 3379 3380 #define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT 0 3381 #define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SIZE 12 3382 #define REG_G3X_POS_RESULT_Z_DECIMAL_Z_MASK 0x00000fff 3383 3384 #ifndef SDK_ASM 3385 #define REG_G3X_POS_RESULT_Z_FIELD( sz, integer_z, decimal_z ) \ 3386 (u32)( \ 3387 ((u32)(sz) << REG_G3X_POS_RESULT_Z_SZ_SHIFT) | \ 3388 ((u32)(integer_z) << REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT) | \ 3389 ((u32)(decimal_z) << REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT)) 3390 #endif 3391 3392 3393 /* POS_RESULT_W */ 3394 3395 #define REG_G3X_POS_RESULT_W_SW_SHIFT 31 3396 #define REG_G3X_POS_RESULT_W_SW_SIZE 1 3397 #define REG_G3X_POS_RESULT_W_SW_MASK 0x80000000 3398 3399 #define REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT 12 3400 #define REG_G3X_POS_RESULT_W_INTEGER_W_SIZE 19 3401 #define REG_G3X_POS_RESULT_W_INTEGER_W_MASK 0x7ffff000 3402 3403 #define REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT 0 3404 #define REG_G3X_POS_RESULT_W_DECIMAL_W_SIZE 12 3405 #define REG_G3X_POS_RESULT_W_DECIMAL_W_MASK 0x00000fff 3406 3407 #ifndef SDK_ASM 3408 #define REG_G3X_POS_RESULT_W_FIELD( sw, integer_w, decimal_w ) \ 3409 (u32)( \ 3410 ((u32)(sw) << REG_G3X_POS_RESULT_W_SW_SHIFT) | \ 3411 ((u32)(integer_w) << REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT) | \ 3412 ((u32)(decimal_w) << REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT)) 3413 #endif 3414 3415 3416 /* VEC_RESULT_X */ 3417 3418 #define REG_G3X_VEC_RESULT_X_SX_SHIFT 15 3419 #define REG_G3X_VEC_RESULT_X_SX_SIZE 1 3420 #define REG_G3X_VEC_RESULT_X_SX_MASK 0x8000 3421 3422 #define REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT 12 3423 #define REG_G3X_VEC_RESULT_X_INTEGER_X_SIZE 3 3424 #define REG_G3X_VEC_RESULT_X_INTEGER_X_MASK 0x7000 3425 3426 #define REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT 0 3427 #define REG_G3X_VEC_RESULT_X_DECIMAL_X_SIZE 12 3428 #define REG_G3X_VEC_RESULT_X_DECIMAL_X_MASK 0x0fff 3429 3430 #ifndef SDK_ASM 3431 #define REG_G3X_VEC_RESULT_X_FIELD( sx, integer_x, decimal_x ) \ 3432 (u16)( \ 3433 ((u32)(sx) << REG_G3X_VEC_RESULT_X_SX_SHIFT) | \ 3434 ((u32)(integer_x) << REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT) | \ 3435 ((u32)(decimal_x) << REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT)) 3436 #endif 3437 3438 3439 /* VEC_RESULT_Y */ 3440 3441 #define REG_G3X_VEC_RESULT_Y_SY_SHIFT 15 3442 #define REG_G3X_VEC_RESULT_Y_SY_SIZE 1 3443 #define REG_G3X_VEC_RESULT_Y_SY_MASK 0x8000 3444 3445 #define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT 12 3446 #define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SIZE 3 3447 #define REG_G3X_VEC_RESULT_Y_INTEGER_Y_MASK 0x7000 3448 3449 #define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT 0 3450 #define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SIZE 12 3451 #define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_MASK 0x0fff 3452 3453 #ifndef SDK_ASM 3454 #define REG_G3X_VEC_RESULT_Y_FIELD( sy, integer_y, decimal_y ) \ 3455 (u16)( \ 3456 ((u32)(sy) << REG_G3X_VEC_RESULT_Y_SY_SHIFT) | \ 3457 ((u32)(integer_y) << REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT) | \ 3458 ((u32)(decimal_y) << REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT)) 3459 #endif 3460 3461 3462 /* VEC_RESULT_Z */ 3463 3464 #define REG_G3X_VEC_RESULT_Z_SZ_SHIFT 15 3465 #define REG_G3X_VEC_RESULT_Z_SZ_SIZE 1 3466 #define REG_G3X_VEC_RESULT_Z_SZ_MASK 0x8000 3467 3468 #define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT 12 3469 #define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SIZE 3 3470 #define REG_G3X_VEC_RESULT_Z_INTEGER_Z_MASK 0x7000 3471 3472 #define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT 0 3473 #define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SIZE 12 3474 #define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_MASK 0x0fff 3475 3476 #ifndef SDK_ASM 3477 #define REG_G3X_VEC_RESULT_Z_FIELD( sz, integer_z, decimal_z ) \ 3478 (u16)( \ 3479 ((u32)(sz) << REG_G3X_VEC_RESULT_Z_SZ_SHIFT) | \ 3480 ((u32)(integer_z) << REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT) | \ 3481 ((u32)(decimal_z) << REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT)) 3482 #endif 3483 3484 3485 /* CLIPMTX_RESULT_0 */ 3486 3487 #define REG_G3X_CLIPMTX_RESULT_0_S_SHIFT 31 3488 #define REG_G3X_CLIPMTX_RESULT_0_S_SIZE 1 3489 #define REG_G3X_CLIPMTX_RESULT_0_S_MASK 0x80000000 3490 3491 #define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT 12 3492 #define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SIZE 19 3493 #define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_MASK 0x7ffff000 3494 3495 #define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT 0 3496 #define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SIZE 12 3497 #define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_MASK 0x00000fff 3498 3499 #ifndef SDK_ASM 3500 #define REG_G3X_CLIPMTX_RESULT_0_FIELD( s, integer_m0, decimal_m0 ) \ 3501 (u32)( \ 3502 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_0_S_SHIFT) | \ 3503 ((u32)(integer_m0) << REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT) | \ 3504 ((u32)(decimal_m0) << REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT)) 3505 #endif 3506 3507 3508 /* CLIPMTX_RESULT_1 */ 3509 3510 #define REG_G3X_CLIPMTX_RESULT_1_S_SHIFT 31 3511 #define REG_G3X_CLIPMTX_RESULT_1_S_SIZE 1 3512 #define REG_G3X_CLIPMTX_RESULT_1_S_MASK 0x80000000 3513 3514 #define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT 12 3515 #define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SIZE 19 3516 #define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_MASK 0x7ffff000 3517 3518 #define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT 0 3519 #define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SIZE 12 3520 #define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_MASK 0x00000fff 3521 3522 #ifndef SDK_ASM 3523 #define REG_G3X_CLIPMTX_RESULT_1_FIELD( s, integer_m1, decimal_m1 ) \ 3524 (u32)( \ 3525 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_1_S_SHIFT) | \ 3526 ((u32)(integer_m1) << REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT) | \ 3527 ((u32)(decimal_m1) << REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT)) 3528 #endif 3529 3530 3531 /* CLIPMTX_RESULT_2 */ 3532 3533 #define REG_G3X_CLIPMTX_RESULT_2_S_SHIFT 31 3534 #define REG_G3X_CLIPMTX_RESULT_2_S_SIZE 1 3535 #define REG_G3X_CLIPMTX_RESULT_2_S_MASK 0x80000000 3536 3537 #define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT 12 3538 #define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SIZE 19 3539 #define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_MASK 0x7ffff000 3540 3541 #define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT 0 3542 #define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SIZE 12 3543 #define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_MASK 0x00000fff 3544 3545 #ifndef SDK_ASM 3546 #define REG_G3X_CLIPMTX_RESULT_2_FIELD( s, integer_m2, decimal_m2 ) \ 3547 (u32)( \ 3548 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_2_S_SHIFT) | \ 3549 ((u32)(integer_m2) << REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT) | \ 3550 ((u32)(decimal_m2) << REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT)) 3551 #endif 3552 3553 3554 /* CLIPMTX_RESULT_3 */ 3555 3556 #define REG_G3X_CLIPMTX_RESULT_3_S_SHIFT 31 3557 #define REG_G3X_CLIPMTX_RESULT_3_S_SIZE 1 3558 #define REG_G3X_CLIPMTX_RESULT_3_S_MASK 0x80000000 3559 3560 #define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT 12 3561 #define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SIZE 19 3562 #define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_MASK 0x7ffff000 3563 3564 #define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT 0 3565 #define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SIZE 12 3566 #define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_MASK 0x00000fff 3567 3568 #ifndef SDK_ASM 3569 #define REG_G3X_CLIPMTX_RESULT_3_FIELD( s, integer_m3, decimal_m3 ) \ 3570 (u32)( \ 3571 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_3_S_SHIFT) | \ 3572 ((u32)(integer_m3) << REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT) | \ 3573 ((u32)(decimal_m3) << REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT)) 3574 #endif 3575 3576 3577 /* CLIPMTX_RESULT_4 */ 3578 3579 #define REG_G3X_CLIPMTX_RESULT_4_S_SHIFT 31 3580 #define REG_G3X_CLIPMTX_RESULT_4_S_SIZE 1 3581 #define REG_G3X_CLIPMTX_RESULT_4_S_MASK 0x80000000 3582 3583 #define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT 12 3584 #define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SIZE 19 3585 #define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_MASK 0x7ffff000 3586 3587 #define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT 0 3588 #define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SIZE 12 3589 #define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_MASK 0x00000fff 3590 3591 #ifndef SDK_ASM 3592 #define REG_G3X_CLIPMTX_RESULT_4_FIELD( s, integer_m4, decimal_m4 ) \ 3593 (u32)( \ 3594 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_4_S_SHIFT) | \ 3595 ((u32)(integer_m4) << REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT) | \ 3596 ((u32)(decimal_m4) << REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT)) 3597 #endif 3598 3599 3600 /* CLIPMTX_RESULT_5 */ 3601 3602 #define REG_G3X_CLIPMTX_RESULT_5_S_SHIFT 31 3603 #define REG_G3X_CLIPMTX_RESULT_5_S_SIZE 1 3604 #define REG_G3X_CLIPMTX_RESULT_5_S_MASK 0x80000000 3605 3606 #define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT 12 3607 #define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SIZE 19 3608 #define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_MASK 0x7ffff000 3609 3610 #define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT 0 3611 #define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SIZE 12 3612 #define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_MASK 0x00000fff 3613 3614 #ifndef SDK_ASM 3615 #define REG_G3X_CLIPMTX_RESULT_5_FIELD( s, integer_m5, decimal_m5 ) \ 3616 (u32)( \ 3617 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_5_S_SHIFT) | \ 3618 ((u32)(integer_m5) << REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT) | \ 3619 ((u32)(decimal_m5) << REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT)) 3620 #endif 3621 3622 3623 /* CLIPMTX_RESULT_6 */ 3624 3625 #define REG_G3X_CLIPMTX_RESULT_6_S_SHIFT 31 3626 #define REG_G3X_CLIPMTX_RESULT_6_S_SIZE 1 3627 #define REG_G3X_CLIPMTX_RESULT_6_S_MASK 0x80000000 3628 3629 #define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT 12 3630 #define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SIZE 19 3631 #define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_MASK 0x7ffff000 3632 3633 #define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT 0 3634 #define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SIZE 12 3635 #define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_MASK 0x00000fff 3636 3637 #ifndef SDK_ASM 3638 #define REG_G3X_CLIPMTX_RESULT_6_FIELD( s, integer_m6, decimal_m6 ) \ 3639 (u32)( \ 3640 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_6_S_SHIFT) | \ 3641 ((u32)(integer_m6) << REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT) | \ 3642 ((u32)(decimal_m6) << REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT)) 3643 #endif 3644 3645 3646 /* CLIPMTX_RESULT_7 */ 3647 3648 #define REG_G3X_CLIPMTX_RESULT_7_S_SHIFT 31 3649 #define REG_G3X_CLIPMTX_RESULT_7_S_SIZE 1 3650 #define REG_G3X_CLIPMTX_RESULT_7_S_MASK 0x80000000 3651 3652 #define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT 12 3653 #define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SIZE 19 3654 #define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_MASK 0x7ffff000 3655 3656 #define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT 0 3657 #define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SIZE 12 3658 #define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_MASK 0x00000fff 3659 3660 #ifndef SDK_ASM 3661 #define REG_G3X_CLIPMTX_RESULT_7_FIELD( s, integer_m7, decimal_m7 ) \ 3662 (u32)( \ 3663 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_7_S_SHIFT) | \ 3664 ((u32)(integer_m7) << REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT) | \ 3665 ((u32)(decimal_m7) << REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT)) 3666 #endif 3667 3668 3669 /* CLIPMTX_RESULT_8 */ 3670 3671 #define REG_G3X_CLIPMTX_RESULT_8_S_SHIFT 31 3672 #define REG_G3X_CLIPMTX_RESULT_8_S_SIZE 1 3673 #define REG_G3X_CLIPMTX_RESULT_8_S_MASK 0x80000000 3674 3675 #define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT 12 3676 #define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SIZE 19 3677 #define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_MASK 0x7ffff000 3678 3679 #define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT 0 3680 #define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SIZE 12 3681 #define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_MASK 0x00000fff 3682 3683 #ifndef SDK_ASM 3684 #define REG_G3X_CLIPMTX_RESULT_8_FIELD( s, integer_m8, decimal_m8 ) \ 3685 (u32)( \ 3686 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_8_S_SHIFT) | \ 3687 ((u32)(integer_m8) << REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT) | \ 3688 ((u32)(decimal_m8) << REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT)) 3689 #endif 3690 3691 3692 /* CLIPMTX_RESULT_9 */ 3693 3694 #define REG_G3X_CLIPMTX_RESULT_9_S_SHIFT 31 3695 #define REG_G3X_CLIPMTX_RESULT_9_S_SIZE 1 3696 #define REG_G3X_CLIPMTX_RESULT_9_S_MASK 0x80000000 3697 3698 #define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT 12 3699 #define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SIZE 19 3700 #define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_MASK 0x7ffff000 3701 3702 #define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT 0 3703 #define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SIZE 12 3704 #define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_MASK 0x00000fff 3705 3706 #ifndef SDK_ASM 3707 #define REG_G3X_CLIPMTX_RESULT_9_FIELD( s, integer_m9, decimal_m9 ) \ 3708 (u32)( \ 3709 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_9_S_SHIFT) | \ 3710 ((u32)(integer_m9) << REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT) | \ 3711 ((u32)(decimal_m9) << REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT)) 3712 #endif 3713 3714 3715 /* CLIPMTX_RESULT_10 */ 3716 3717 #define REG_G3X_CLIPMTX_RESULT_10_S_SHIFT 31 3718 #define REG_G3X_CLIPMTX_RESULT_10_S_SIZE 1 3719 #define REG_G3X_CLIPMTX_RESULT_10_S_MASK 0x80000000 3720 3721 #define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT 12 3722 #define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SIZE 19 3723 #define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_MASK 0x7ffff000 3724 3725 #define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT 0 3726 #define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SIZE 12 3727 #define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_MASK 0x00000fff 3728 3729 #ifndef SDK_ASM 3730 #define REG_G3X_CLIPMTX_RESULT_10_FIELD( s, integer_m10, decimal_m10 ) \ 3731 (u32)( \ 3732 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_10_S_SHIFT) | \ 3733 ((u32)(integer_m10) << REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT) | \ 3734 ((u32)(decimal_m10) << REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT)) 3735 #endif 3736 3737 3738 /* CLIPMTX_RESULT_11 */ 3739 3740 #define REG_G3X_CLIPMTX_RESULT_11_S_SHIFT 31 3741 #define REG_G3X_CLIPMTX_RESULT_11_S_SIZE 1 3742 #define REG_G3X_CLIPMTX_RESULT_11_S_MASK 0x80000000 3743 3744 #define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT 12 3745 #define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SIZE 19 3746 #define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_MASK 0x7ffff000 3747 3748 #define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT 0 3749 #define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SIZE 12 3750 #define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_MASK 0x00000fff 3751 3752 #ifndef SDK_ASM 3753 #define REG_G3X_CLIPMTX_RESULT_11_FIELD( s, integer_m11, decimal_m11 ) \ 3754 (u32)( \ 3755 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_11_S_SHIFT) | \ 3756 ((u32)(integer_m11) << REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT) | \ 3757 ((u32)(decimal_m11) << REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT)) 3758 #endif 3759 3760 3761 /* CLIPMTX_RESULT_12 */ 3762 3763 #define REG_G3X_CLIPMTX_RESULT_12_S_SHIFT 31 3764 #define REG_G3X_CLIPMTX_RESULT_12_S_SIZE 1 3765 #define REG_G3X_CLIPMTX_RESULT_12_S_MASK 0x80000000 3766 3767 #define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT 12 3768 #define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SIZE 19 3769 #define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_MASK 0x7ffff000 3770 3771 #define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT 0 3772 #define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SIZE 12 3773 #define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_MASK 0x00000fff 3774 3775 #ifndef SDK_ASM 3776 #define REG_G3X_CLIPMTX_RESULT_12_FIELD( s, integer_m12, decimal_m12 ) \ 3777 (u32)( \ 3778 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_12_S_SHIFT) | \ 3779 ((u32)(integer_m12) << REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT) | \ 3780 ((u32)(decimal_m12) << REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT)) 3781 #endif 3782 3783 3784 /* CLIPMTX_RESULT_13 */ 3785 3786 #define REG_G3X_CLIPMTX_RESULT_13_S_SHIFT 31 3787 #define REG_G3X_CLIPMTX_RESULT_13_S_SIZE 1 3788 #define REG_G3X_CLIPMTX_RESULT_13_S_MASK 0x80000000 3789 3790 #define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT 12 3791 #define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SIZE 19 3792 #define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_MASK 0x7ffff000 3793 3794 #define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT 0 3795 #define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SIZE 12 3796 #define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_MASK 0x00000fff 3797 3798 #ifndef SDK_ASM 3799 #define REG_G3X_CLIPMTX_RESULT_13_FIELD( s, integer_m13, decimal_m13 ) \ 3800 (u32)( \ 3801 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_13_S_SHIFT) | \ 3802 ((u32)(integer_m13) << REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT) | \ 3803 ((u32)(decimal_m13) << REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT)) 3804 #endif 3805 3806 3807 /* CLIPMTX_RESULT_14 */ 3808 3809 #define REG_G3X_CLIPMTX_RESULT_14_S_SHIFT 31 3810 #define REG_G3X_CLIPMTX_RESULT_14_S_SIZE 1 3811 #define REG_G3X_CLIPMTX_RESULT_14_S_MASK 0x80000000 3812 3813 #define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT 12 3814 #define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SIZE 19 3815 #define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_MASK 0x7ffff000 3816 3817 #define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT 0 3818 #define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SIZE 12 3819 #define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_MASK 0x00000fff 3820 3821 #ifndef SDK_ASM 3822 #define REG_G3X_CLIPMTX_RESULT_14_FIELD( s, integer_m14, decimal_m14 ) \ 3823 (u32)( \ 3824 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_14_S_SHIFT) | \ 3825 ((u32)(integer_m14) << REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT) | \ 3826 ((u32)(decimal_m14) << REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT)) 3827 #endif 3828 3829 3830 /* CLIPMTX_RESULT_15 */ 3831 3832 #define REG_G3X_CLIPMTX_RESULT_15_S_SHIFT 31 3833 #define REG_G3X_CLIPMTX_RESULT_15_S_SIZE 1 3834 #define REG_G3X_CLIPMTX_RESULT_15_S_MASK 0x80000000 3835 3836 #define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT 12 3837 #define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SIZE 19 3838 #define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_MASK 0x7ffff000 3839 3840 #define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT 0 3841 #define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SIZE 12 3842 #define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_MASK 0x00000fff 3843 3844 #ifndef SDK_ASM 3845 #define REG_G3X_CLIPMTX_RESULT_15_FIELD( s, integer_m15, decimal_m15 ) \ 3846 (u32)( \ 3847 ((u32)(s) << REG_G3X_CLIPMTX_RESULT_15_S_SHIFT) | \ 3848 ((u32)(integer_m15) << REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT) | \ 3849 ((u32)(decimal_m15) << REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT)) 3850 #endif 3851 3852 3853 /* VECMTX_RESULT_0 */ 3854 3855 #define REG_G3X_VECMTX_RESULT_0_S_SHIFT 31 3856 #define REG_G3X_VECMTX_RESULT_0_S_SIZE 1 3857 #define REG_G3X_VECMTX_RESULT_0_S_MASK 0x80000000 3858 3859 #define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT 12 3860 #define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SIZE 19 3861 #define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_MASK 0x7ffff000 3862 3863 #define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT 0 3864 #define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SIZE 12 3865 #define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_MASK 0x00000fff 3866 3867 #ifndef SDK_ASM 3868 #define REG_G3X_VECMTX_RESULT_0_FIELD( s, integer_m0, decimal_m0 ) \ 3869 (u32)( \ 3870 ((u32)(s) << REG_G3X_VECMTX_RESULT_0_S_SHIFT) | \ 3871 ((u32)(integer_m0) << REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT) | \ 3872 ((u32)(decimal_m0) << REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT)) 3873 #endif 3874 3875 3876 /* VECMTX_RESULT_1 */ 3877 3878 #define REG_G3X_VECMTX_RESULT_1_S_SHIFT 31 3879 #define REG_G3X_VECMTX_RESULT_1_S_SIZE 1 3880 #define REG_G3X_VECMTX_RESULT_1_S_MASK 0x80000000 3881 3882 #define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT 12 3883 #define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SIZE 19 3884 #define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_MASK 0x7ffff000 3885 3886 #define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT 0 3887 #define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SIZE 12 3888 #define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_MASK 0x00000fff 3889 3890 #ifndef SDK_ASM 3891 #define REG_G3X_VECMTX_RESULT_1_FIELD( s, integer_m1, decimal_m1 ) \ 3892 (u32)( \ 3893 ((u32)(s) << REG_G3X_VECMTX_RESULT_1_S_SHIFT) | \ 3894 ((u32)(integer_m1) << REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT) | \ 3895 ((u32)(decimal_m1) << REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT)) 3896 #endif 3897 3898 3899 /* VECMTX_RESULT_2 */ 3900 3901 #define REG_G3X_VECMTX_RESULT_2_S_SHIFT 31 3902 #define REG_G3X_VECMTX_RESULT_2_S_SIZE 1 3903 #define REG_G3X_VECMTX_RESULT_2_S_MASK 0x80000000 3904 3905 #define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT 12 3906 #define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SIZE 19 3907 #define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_MASK 0x7ffff000 3908 3909 #define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT 0 3910 #define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SIZE 12 3911 #define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_MASK 0x00000fff 3912 3913 #ifndef SDK_ASM 3914 #define REG_G3X_VECMTX_RESULT_2_FIELD( s, integer_m2, decimal_m2 ) \ 3915 (u32)( \ 3916 ((u32)(s) << REG_G3X_VECMTX_RESULT_2_S_SHIFT) | \ 3917 ((u32)(integer_m2) << REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT) | \ 3918 ((u32)(decimal_m2) << REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT)) 3919 #endif 3920 3921 3922 /* VECMTX_RESULT_3 */ 3923 3924 #define REG_G3X_VECMTX_RESULT_3_S_SHIFT 31 3925 #define REG_G3X_VECMTX_RESULT_3_S_SIZE 1 3926 #define REG_G3X_VECMTX_RESULT_3_S_MASK 0x80000000 3927 3928 #define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT 12 3929 #define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SIZE 19 3930 #define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_MASK 0x7ffff000 3931 3932 #define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT 0 3933 #define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SIZE 12 3934 #define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_MASK 0x00000fff 3935 3936 #ifndef SDK_ASM 3937 #define REG_G3X_VECMTX_RESULT_3_FIELD( s, integer_m3, decimal_m3 ) \ 3938 (u32)( \ 3939 ((u32)(s) << REG_G3X_VECMTX_RESULT_3_S_SHIFT) | \ 3940 ((u32)(integer_m3) << REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT) | \ 3941 ((u32)(decimal_m3) << REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT)) 3942 #endif 3943 3944 3945 /* VECMTX_RESULT_4 */ 3946 3947 #define REG_G3X_VECMTX_RESULT_4_S_SHIFT 31 3948 #define REG_G3X_VECMTX_RESULT_4_S_SIZE 1 3949 #define REG_G3X_VECMTX_RESULT_4_S_MASK 0x80000000 3950 3951 #define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT 12 3952 #define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SIZE 19 3953 #define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_MASK 0x7ffff000 3954 3955 #define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT 0 3956 #define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SIZE 12 3957 #define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_MASK 0x00000fff 3958 3959 #ifndef SDK_ASM 3960 #define REG_G3X_VECMTX_RESULT_4_FIELD( s, integer_m4, decimal_m4 ) \ 3961 (u32)( \ 3962 ((u32)(s) << REG_G3X_VECMTX_RESULT_4_S_SHIFT) | \ 3963 ((u32)(integer_m4) << REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT) | \ 3964 ((u32)(decimal_m4) << REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT)) 3965 #endif 3966 3967 3968 /* VECMTX_RESULT_5 */ 3969 3970 #define REG_G3X_VECMTX_RESULT_5_S_SHIFT 31 3971 #define REG_G3X_VECMTX_RESULT_5_S_SIZE 1 3972 #define REG_G3X_VECMTX_RESULT_5_S_MASK 0x80000000 3973 3974 #define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT 12 3975 #define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SIZE 19 3976 #define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_MASK 0x7ffff000 3977 3978 #define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT 0 3979 #define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SIZE 12 3980 #define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_MASK 0x00000fff 3981 3982 #ifndef SDK_ASM 3983 #define REG_G3X_VECMTX_RESULT_5_FIELD( s, integer_m5, decimal_m5 ) \ 3984 (u32)( \ 3985 ((u32)(s) << REG_G3X_VECMTX_RESULT_5_S_SHIFT) | \ 3986 ((u32)(integer_m5) << REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT) | \ 3987 ((u32)(decimal_m5) << REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT)) 3988 #endif 3989 3990 3991 /* VECMTX_RESULT_6 */ 3992 3993 #define REG_G3X_VECMTX_RESULT_6_S_SHIFT 31 3994 #define REG_G3X_VECMTX_RESULT_6_S_SIZE 1 3995 #define REG_G3X_VECMTX_RESULT_6_S_MASK 0x80000000 3996 3997 #define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT 12 3998 #define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SIZE 19 3999 #define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_MASK 0x7ffff000 4000 4001 #define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT 0 4002 #define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SIZE 12 4003 #define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_MASK 0x00000fff 4004 4005 #ifndef SDK_ASM 4006 #define REG_G3X_VECMTX_RESULT_6_FIELD( s, integer_m6, decimal_m6 ) \ 4007 (u32)( \ 4008 ((u32)(s) << REG_G3X_VECMTX_RESULT_6_S_SHIFT) | \ 4009 ((u32)(integer_m6) << REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT) | \ 4010 ((u32)(decimal_m6) << REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT)) 4011 #endif 4012 4013 4014 /* VECMTX_RESULT_7 */ 4015 4016 #define REG_G3X_VECMTX_RESULT_7_S_SHIFT 31 4017 #define REG_G3X_VECMTX_RESULT_7_S_SIZE 1 4018 #define REG_G3X_VECMTX_RESULT_7_S_MASK 0x80000000 4019 4020 #define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT 12 4021 #define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SIZE 19 4022 #define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_MASK 0x7ffff000 4023 4024 #define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT 0 4025 #define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SIZE 12 4026 #define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_MASK 0x00000fff 4027 4028 #ifndef SDK_ASM 4029 #define REG_G3X_VECMTX_RESULT_7_FIELD( s, integer_m7, decimal_m7 ) \ 4030 (u32)( \ 4031 ((u32)(s) << REG_G3X_VECMTX_RESULT_7_S_SHIFT) | \ 4032 ((u32)(integer_m7) << REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT) | \ 4033 ((u32)(decimal_m7) << REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT)) 4034 #endif 4035 4036 4037 /* VECMTX_RESULT_8 */ 4038 4039 #define REG_G3X_VECMTX_RESULT_8_S_SHIFT 31 4040 #define REG_G3X_VECMTX_RESULT_8_S_SIZE 1 4041 #define REG_G3X_VECMTX_RESULT_8_S_MASK 0x80000000 4042 4043 #define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT 12 4044 #define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SIZE 19 4045 #define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_MASK 0x7ffff000 4046 4047 #define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT 0 4048 #define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SIZE 12 4049 #define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_MASK 0x00000fff 4050 4051 #ifndef SDK_ASM 4052 #define REG_G3X_VECMTX_RESULT_8_FIELD( s, integer_m8, decimal_m8 ) \ 4053 (u32)( \ 4054 ((u32)(s) << REG_G3X_VECMTX_RESULT_8_S_SHIFT) | \ 4055 ((u32)(integer_m8) << REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT) | \ 4056 ((u32)(decimal_m8) << REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT)) 4057 #endif 4058 4059 4060 #ifdef __cplusplus 4061 } /* extern "C" */ 4062 #endif 4063 4064 /* NITRO_HW_ARM9_IOREG_G3X_H_ */ 4065 #endif 4066