1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_G3.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_G3_H_ 18 #define NITRO_HW_ARM9_IOREG_G3_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* MTX_MODE */ 35 36 #define REG_MTX_MODE_OFFSET 0x440 37 #define REG_MTX_MODE_ADDR (HW_REG_BASE + REG_MTX_MODE_OFFSET) 38 #define reg_G3_MTX_MODE (*( REGType32v *) REG_MTX_MODE_ADDR) 39 40 /* MTX_PUSH */ 41 42 #define REG_MTX_PUSH_OFFSET 0x444 43 #define REG_MTX_PUSH_ADDR (HW_REG_BASE + REG_MTX_PUSH_OFFSET) 44 #define reg_G3_MTX_PUSH (*( REGType32v *) REG_MTX_PUSH_ADDR) 45 46 /* MTX_POP */ 47 48 #define REG_MTX_POP_OFFSET 0x448 49 #define REG_MTX_POP_ADDR (HW_REG_BASE + REG_MTX_POP_OFFSET) 50 #define reg_G3_MTX_POP (*( REGType32v *) REG_MTX_POP_ADDR) 51 52 /* MTX_STORE */ 53 54 #define REG_MTX_STORE_OFFSET 0x44c 55 #define REG_MTX_STORE_ADDR (HW_REG_BASE + REG_MTX_STORE_OFFSET) 56 #define reg_G3_MTX_STORE (*( REGType32v *) REG_MTX_STORE_ADDR) 57 58 /* MTX_RESTORE */ 59 60 #define REG_MTX_RESTORE_OFFSET 0x450 61 #define REG_MTX_RESTORE_ADDR (HW_REG_BASE + REG_MTX_RESTORE_OFFSET) 62 #define reg_G3_MTX_RESTORE (*( REGType32v *) REG_MTX_RESTORE_ADDR) 63 64 /* MTX_IDENTITY */ 65 66 #define REG_MTX_IDENTITY_OFFSET 0x454 67 #define REG_MTX_IDENTITY_ADDR (HW_REG_BASE + REG_MTX_IDENTITY_OFFSET) 68 #define reg_G3_MTX_IDENTITY (*( REGType32v *) REG_MTX_IDENTITY_ADDR) 69 70 /* MTX_LOAD_4x4 */ 71 72 #define REG_MTX_LOAD_4x4_OFFSET 0x458 73 #define REG_MTX_LOAD_4x4_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x4_OFFSET) 74 #define reg_G3_MTX_LOAD_4x4 (*( REGType32v *) REG_MTX_LOAD_4x4_ADDR) 75 76 /* MTX_LOAD_4x3 */ 77 78 #define REG_MTX_LOAD_4x3_OFFSET 0x45c 79 #define REG_MTX_LOAD_4x3_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x3_OFFSET) 80 #define reg_G3_MTX_LOAD_4x3 (*( REGType32v *) REG_MTX_LOAD_4x3_ADDR) 81 82 /* MTX_MULT_4x4 */ 83 84 #define REG_MTX_MULT_4x4_OFFSET 0x460 85 #define REG_MTX_MULT_4x4_ADDR (HW_REG_BASE + REG_MTX_MULT_4x4_OFFSET) 86 #define reg_G3_MTX_MULT_4x4 (*( REGType32v *) REG_MTX_MULT_4x4_ADDR) 87 88 /* MTX_MULT_4x3 */ 89 90 #define REG_MTX_MULT_4x3_OFFSET 0x464 91 #define REG_MTX_MULT_4x3_ADDR (HW_REG_BASE + REG_MTX_MULT_4x3_OFFSET) 92 #define reg_G3_MTX_MULT_4x3 (*( REGType32v *) REG_MTX_MULT_4x3_ADDR) 93 94 /* MTX_MULT_3x3 */ 95 96 #define REG_MTX_MULT_3x3_OFFSET 0x468 97 #define REG_MTX_MULT_3x3_ADDR (HW_REG_BASE + REG_MTX_MULT_3x3_OFFSET) 98 #define reg_G3_MTX_MULT_3x3 (*( REGType32v *) REG_MTX_MULT_3x3_ADDR) 99 100 /* MTX_SCALE */ 101 102 #define REG_MTX_SCALE_OFFSET 0x46c 103 #define REG_MTX_SCALE_ADDR (HW_REG_BASE + REG_MTX_SCALE_OFFSET) 104 #define reg_G3_MTX_SCALE (*( REGType32v *) REG_MTX_SCALE_ADDR) 105 106 /* MTX_TRANS */ 107 108 #define REG_MTX_TRANS_OFFSET 0x470 109 #define REG_MTX_TRANS_ADDR (HW_REG_BASE + REG_MTX_TRANS_OFFSET) 110 #define reg_G3_MTX_TRANS (*( REGType32v *) REG_MTX_TRANS_ADDR) 111 112 /* COLOR */ 113 114 #define REG_COLOR_OFFSET 0x480 115 #define REG_COLOR_ADDR (HW_REG_BASE + REG_COLOR_OFFSET) 116 #define reg_G3_COLOR (*( REGType32v *) REG_COLOR_ADDR) 117 118 /* NORMAL */ 119 120 #define REG_NORMAL_OFFSET 0x484 121 #define REG_NORMAL_ADDR (HW_REG_BASE + REG_NORMAL_OFFSET) 122 #define reg_G3_NORMAL (*( REGType32v *) REG_NORMAL_ADDR) 123 124 /* TEXCOORD */ 125 126 #define REG_TEXCOORD_OFFSET 0x488 127 #define REG_TEXCOORD_ADDR (HW_REG_BASE + REG_TEXCOORD_OFFSET) 128 #define reg_G3_TEXCOORD (*( REGType32v *) REG_TEXCOORD_ADDR) 129 130 /* VTX_16 */ 131 132 #define REG_VTX_16_OFFSET 0x48c 133 #define REG_VTX_16_ADDR (HW_REG_BASE + REG_VTX_16_OFFSET) 134 #define reg_G3_VTX_16 (*( REGType32v *) REG_VTX_16_ADDR) 135 136 /* VTX_10 */ 137 138 #define REG_VTX_10_OFFSET 0x490 139 #define REG_VTX_10_ADDR (HW_REG_BASE + REG_VTX_10_OFFSET) 140 #define reg_G3_VTX_10 (*( REGType32v *) REG_VTX_10_ADDR) 141 142 /* VTX_XY */ 143 144 #define REG_VTX_XY_OFFSET 0x494 145 #define REG_VTX_XY_ADDR (HW_REG_BASE + REG_VTX_XY_OFFSET) 146 #define reg_G3_VTX_XY (*( REGType32v *) REG_VTX_XY_ADDR) 147 148 /* VTX_XZ */ 149 150 #define REG_VTX_XZ_OFFSET 0x498 151 #define REG_VTX_XZ_ADDR (HW_REG_BASE + REG_VTX_XZ_OFFSET) 152 #define reg_G3_VTX_XZ (*( REGType32v *) REG_VTX_XZ_ADDR) 153 154 /* VTX_YZ */ 155 156 #define REG_VTX_YZ_OFFSET 0x49c 157 #define REG_VTX_YZ_ADDR (HW_REG_BASE + REG_VTX_YZ_OFFSET) 158 #define reg_G3_VTX_YZ (*( REGType32v *) REG_VTX_YZ_ADDR) 159 160 /* VTX_DIFF */ 161 162 #define REG_VTX_DIFF_OFFSET 0x4a0 163 #define REG_VTX_DIFF_ADDR (HW_REG_BASE + REG_VTX_DIFF_OFFSET) 164 #define reg_G3_VTX_DIFF (*( REGType32v *) REG_VTX_DIFF_ADDR) 165 166 /* POLYGON_ATTR */ 167 168 #define REG_POLYGON_ATTR_OFFSET 0x4a4 169 #define REG_POLYGON_ATTR_ADDR (HW_REG_BASE + REG_POLYGON_ATTR_OFFSET) 170 #define reg_G3_POLYGON_ATTR (*( REGType32v *) REG_POLYGON_ATTR_ADDR) 171 172 /* TEXIMAGE_PARAM */ 173 174 #define REG_TEXIMAGE_PARAM_OFFSET 0x4a8 175 #define REG_TEXIMAGE_PARAM_ADDR (HW_REG_BASE + REG_TEXIMAGE_PARAM_OFFSET) 176 #define reg_G3_TEXIMAGE_PARAM (*( REGType32v *) REG_TEXIMAGE_PARAM_ADDR) 177 178 /* TEXPLTT_BASE */ 179 180 #define REG_TEXPLTT_BASE_OFFSET 0x4ac 181 #define REG_TEXPLTT_BASE_ADDR (HW_REG_BASE + REG_TEXPLTT_BASE_OFFSET) 182 #define reg_G3_TEXPLTT_BASE (*( REGType32v *) REG_TEXPLTT_BASE_ADDR) 183 184 /* DIF_AMB */ 185 186 #define REG_DIF_AMB_OFFSET 0x4c0 187 #define REG_DIF_AMB_ADDR (HW_REG_BASE + REG_DIF_AMB_OFFSET) 188 #define reg_G3_DIF_AMB (*( REGType32v *) REG_DIF_AMB_ADDR) 189 190 /* SPE_EMI */ 191 192 #define REG_SPE_EMI_OFFSET 0x4c4 193 #define REG_SPE_EMI_ADDR (HW_REG_BASE + REG_SPE_EMI_OFFSET) 194 #define reg_G3_SPE_EMI (*( REGType32v *) REG_SPE_EMI_ADDR) 195 196 /* LIGHT_VECTOR */ 197 198 #define REG_LIGHT_VECTOR_OFFSET 0x4c8 199 #define REG_LIGHT_VECTOR_ADDR (HW_REG_BASE + REG_LIGHT_VECTOR_OFFSET) 200 #define reg_G3_LIGHT_VECTOR (*( REGType32v *) REG_LIGHT_VECTOR_ADDR) 201 202 /* LIGHT_COLOR */ 203 204 #define REG_LIGHT_COLOR_OFFSET 0x4cc 205 #define REG_LIGHT_COLOR_ADDR (HW_REG_BASE + REG_LIGHT_COLOR_OFFSET) 206 #define reg_G3_LIGHT_COLOR (*( REGType32v *) REG_LIGHT_COLOR_ADDR) 207 208 /* SHININESS */ 209 210 #define REG_SHININESS_OFFSET 0x4d0 211 #define REG_SHININESS_ADDR (HW_REG_BASE + REG_SHININESS_OFFSET) 212 #define reg_G3_SHININESS (*( REGType32v *) REG_SHININESS_ADDR) 213 214 /* BEGIN_VTXS */ 215 216 #define REG_BEGIN_VTXS_OFFSET 0x500 217 #define REG_BEGIN_VTXS_ADDR (HW_REG_BASE + REG_BEGIN_VTXS_OFFSET) 218 #define reg_G3_BEGIN_VTXS (*( REGType32v *) REG_BEGIN_VTXS_ADDR) 219 220 /* END_VTXS */ 221 222 #define REG_END_VTXS_OFFSET 0x504 223 #define REG_END_VTXS_ADDR (HW_REG_BASE + REG_END_VTXS_OFFSET) 224 #define reg_G3_END_VTXS (*( REGType32v *) REG_END_VTXS_ADDR) 225 226 /* SWAP_BUFFERS */ 227 228 #define REG_SWAP_BUFFERS_OFFSET 0x540 229 #define REG_SWAP_BUFFERS_ADDR (HW_REG_BASE + REG_SWAP_BUFFERS_OFFSET) 230 #define reg_G3_SWAP_BUFFERS (*( REGType32v *) REG_SWAP_BUFFERS_ADDR) 231 232 /* VIEWPORT */ 233 234 #define REG_VIEWPORT_OFFSET 0x580 235 #define REG_VIEWPORT_ADDR (HW_REG_BASE + REG_VIEWPORT_OFFSET) 236 #define reg_G3_VIEWPORT (*( REGType32v *) REG_VIEWPORT_ADDR) 237 238 /* BOX_TEST */ 239 240 #define REG_BOX_TEST_OFFSET 0x5c0 241 #define REG_BOX_TEST_ADDR (HW_REG_BASE + REG_BOX_TEST_OFFSET) 242 #define reg_G3_BOX_TEST (*( REGType32v *) REG_BOX_TEST_ADDR) 243 244 /* POS_TEST */ 245 246 #define REG_POS_TEST_OFFSET 0x5c4 247 #define REG_POS_TEST_ADDR (HW_REG_BASE + REG_POS_TEST_OFFSET) 248 #define reg_G3_POS_TEST (*( REGType32v *) REG_POS_TEST_ADDR) 249 250 /* VEC_TEST */ 251 252 #define REG_VEC_TEST_OFFSET 0x5c8 253 #define REG_VEC_TEST_ADDR (HW_REG_BASE + REG_VEC_TEST_OFFSET) 254 #define reg_G3_VEC_TEST (*( REGType32v *) REG_VEC_TEST_ADDR) 255 256 257 /* 258 * Definitions of Register fields 259 */ 260 261 262 /* MTX_MODE */ 263 264 #define REG_G3_MTX_MODE_M_SHIFT 0 265 #define REG_G3_MTX_MODE_M_SIZE 2 266 #define REG_G3_MTX_MODE_M_MASK 0x00000003 267 268 #ifndef SDK_ASM 269 #define REG_G3_MTX_MODE_FIELD( m ) \ 270 (u32)( \ 271 ((u32)(m) << REG_G3_MTX_MODE_M_SHIFT)) 272 #endif 273 274 275 /* MTX_PUSH */ 276 277 /* MTX_POP */ 278 279 #define REG_G3_MTX_POP_S_SHIFT 5 280 #define REG_G3_MTX_POP_S_SIZE 1 281 #define REG_G3_MTX_POP_S_MASK 0x00000020 282 283 #define REG_G3_MTX_POP_INT_SHIFT 0 284 #define REG_G3_MTX_POP_INT_SIZE 5 285 #define REG_G3_MTX_POP_INT_MASK 0x0000001f 286 287 #ifndef SDK_ASM 288 #define REG_G3_MTX_POP_FIELD( s, int ) \ 289 (u32)( \ 290 ((u32)(s) << REG_G3_MTX_POP_S_SHIFT) | \ 291 ((u32)(int) << REG_G3_MTX_POP_INT_SHIFT)) 292 #endif 293 294 295 /* MTX_STORE */ 296 297 #define REG_G3_MTX_STORE_INDEX_SHIFT 0 298 #define REG_G3_MTX_STORE_INDEX_SIZE 5 299 #define REG_G3_MTX_STORE_INDEX_MASK 0x0000001f 300 301 #ifndef SDK_ASM 302 #define REG_G3_MTX_STORE_FIELD( index ) \ 303 (u32)( \ 304 ((u32)(index) << REG_G3_MTX_STORE_INDEX_SHIFT)) 305 #endif 306 307 308 /* MTX_RESTORE */ 309 310 #define REG_G3_MTX_RESTORE_INDEX_SHIFT 0 311 #define REG_G3_MTX_RESTORE_INDEX_SIZE 5 312 #define REG_G3_MTX_RESTORE_INDEX_MASK 0x0000001f 313 314 #ifndef SDK_ASM 315 #define REG_G3_MTX_RESTORE_FIELD( index ) \ 316 (u32)( \ 317 ((u32)(index) << REG_G3_MTX_RESTORE_INDEX_SHIFT)) 318 #endif 319 320 321 /* MTX_IDENTITY */ 322 323 /* MTX_LOAD_4x4 */ 324 325 #define REG_G3_MTX_LOAD_4x4_S_SHIFT 31 326 #define REG_G3_MTX_LOAD_4x4_S_SIZE 1 327 #define REG_G3_MTX_LOAD_4x4_S_MASK 0x80000000 328 329 #define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT 12 330 #define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SIZE 19 331 #define REG_G3_MTX_LOAD_4x4_INTEGER_M44_MASK 0x7ffff000 332 333 #define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT 0 334 #define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SIZE 12 335 #define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_MASK 0x00000fff 336 337 #ifndef SDK_ASM 338 #define REG_G3_MTX_LOAD_4x4_FIELD( s, integer_m44, decimal_m44 ) \ 339 (u32)( \ 340 ((u32)(s) << REG_G3_MTX_LOAD_4x4_S_SHIFT) | \ 341 ((u32)(integer_m44) << REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT) | \ 342 ((u32)(decimal_m44) << REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT)) 343 #endif 344 345 346 /* MTX_LOAD_4x3 */ 347 348 #define REG_G3_MTX_LOAD_4x3_S_SHIFT 31 349 #define REG_G3_MTX_LOAD_4x3_S_SIZE 1 350 #define REG_G3_MTX_LOAD_4x3_S_MASK 0x80000000 351 352 #define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT 12 353 #define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SIZE 19 354 #define REG_G3_MTX_LOAD_4x3_INTEGER_M43_MASK 0x7ffff000 355 356 #define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT 0 357 #define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SIZE 12 358 #define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_MASK 0x00000fff 359 360 #ifndef SDK_ASM 361 #define REG_G3_MTX_LOAD_4x3_FIELD( s, integer_m43, decimal_m43 ) \ 362 (u32)( \ 363 ((u32)(s) << REG_G3_MTX_LOAD_4x3_S_SHIFT) | \ 364 ((u32)(integer_m43) << REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT) | \ 365 ((u32)(decimal_m43) << REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT)) 366 #endif 367 368 369 /* MTX_MULT_4x4 */ 370 371 #define REG_G3_MTX_MULT_4x4_S_SHIFT 31 372 #define REG_G3_MTX_MULT_4x4_S_SIZE 1 373 #define REG_G3_MTX_MULT_4x4_S_MASK 0x80000000 374 375 #define REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT 12 376 #define REG_G3_MTX_MULT_4x4_INTEGER_M44_SIZE 19 377 #define REG_G3_MTX_MULT_4x4_INTEGER_M44_MASK 0x7ffff000 378 379 #define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT 0 380 #define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SIZE 12 381 #define REG_G3_MTX_MULT_4x4_DECIMAL_M44_MASK 0x00000fff 382 383 #ifndef SDK_ASM 384 #define REG_G3_MTX_MULT_4x4_FIELD( s, integer_m44, decimal_m44 ) \ 385 (u32)( \ 386 ((u32)(s) << REG_G3_MTX_MULT_4x4_S_SHIFT) | \ 387 ((u32)(integer_m44) << REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT) | \ 388 ((u32)(decimal_m44) << REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT)) 389 #endif 390 391 392 /* MTX_MULT_4x3 */ 393 394 #define REG_G3_MTX_MULT_4x3_S_SHIFT 31 395 #define REG_G3_MTX_MULT_4x3_S_SIZE 1 396 #define REG_G3_MTX_MULT_4x3_S_MASK 0x80000000 397 398 #define REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT 12 399 #define REG_G3_MTX_MULT_4x3_INTEGER_M43_SIZE 19 400 #define REG_G3_MTX_MULT_4x3_INTEGER_M43_MASK 0x7ffff000 401 402 #define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT 0 403 #define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SIZE 12 404 #define REG_G3_MTX_MULT_4x3_DECIMAL_M43_MASK 0x00000fff 405 406 #ifndef SDK_ASM 407 #define REG_G3_MTX_MULT_4x3_FIELD( s, integer_m43, decimal_m43 ) \ 408 (u32)( \ 409 ((u32)(s) << REG_G3_MTX_MULT_4x3_S_SHIFT) | \ 410 ((u32)(integer_m43) << REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT) | \ 411 ((u32)(decimal_m43) << REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT)) 412 #endif 413 414 415 /* MTX_MULT_3x3 */ 416 417 #define REG_G3_MTX_MULT_3x3_S_SHIFT 31 418 #define REG_G3_MTX_MULT_3x3_S_SIZE 1 419 #define REG_G3_MTX_MULT_3x3_S_MASK 0x80000000 420 421 #define REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT 12 422 #define REG_G3_MTX_MULT_3x3_INTEGER_M33_SIZE 19 423 #define REG_G3_MTX_MULT_3x3_INTEGER_M33_MASK 0x7ffff000 424 425 #define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT 0 426 #define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SIZE 12 427 #define REG_G3_MTX_MULT_3x3_DECIMAL_M33_MASK 0x00000fff 428 429 #ifndef SDK_ASM 430 #define REG_G3_MTX_MULT_3x3_FIELD( s, integer_m33, decimal_m33 ) \ 431 (u32)( \ 432 ((u32)(s) << REG_G3_MTX_MULT_3x3_S_SHIFT) | \ 433 ((u32)(integer_m33) << REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT) | \ 434 ((u32)(decimal_m33) << REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT)) 435 #endif 436 437 438 /* MTX_SCALE */ 439 440 #define REG_G3_MTX_SCALE_S_SHIFT 31 441 #define REG_G3_MTX_SCALE_S_SIZE 1 442 #define REG_G3_MTX_SCALE_S_MASK 0x80000000 443 444 #define REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT 12 445 #define REG_G3_MTX_SCALE_INTEGER_SCALE_SIZE 19 446 #define REG_G3_MTX_SCALE_INTEGER_SCALE_MASK 0x7ffff000 447 448 #define REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT 0 449 #define REG_G3_MTX_SCALE_DECIMAL_SCALE_SIZE 12 450 #define REG_G3_MTX_SCALE_DECIMAL_SCALE_MASK 0x00000fff 451 452 #ifndef SDK_ASM 453 #define REG_G3_MTX_SCALE_FIELD( s, integer_scale, decimal_scale ) \ 454 (u32)( \ 455 ((u32)(s) << REG_G3_MTX_SCALE_S_SHIFT) | \ 456 ((u32)(integer_scale) << REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT) | \ 457 ((u32)(decimal_scale) << REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT)) 458 #endif 459 460 461 /* MTX_TRANS */ 462 463 #define REG_G3_MTX_TRANS_S_SHIFT 31 464 #define REG_G3_MTX_TRANS_S_SIZE 1 465 #define REG_G3_MTX_TRANS_S_MASK 0x80000000 466 467 #define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT 12 468 #define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SIZE 19 469 #define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_MASK 0x7ffff000 470 471 #define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT 0 472 #define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SIZE 12 473 #define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_MASK 0x00000fff 474 475 #ifndef SDK_ASM 476 #define REG_G3_MTX_TRANS_FIELD( s, integer_translate, decimal_translate ) \ 477 (u32)( \ 478 ((u32)(s) << REG_G3_MTX_TRANS_S_SHIFT) | \ 479 ((u32)(integer_translate) << REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT) | \ 480 ((u32)(decimal_translate) << REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT)) 481 #endif 482 483 484 /* COLOR */ 485 486 #define REG_G3_COLOR_BLUE_SHIFT 10 487 #define REG_G3_COLOR_BLUE_SIZE 5 488 #define REG_G3_COLOR_BLUE_MASK 0x00007c00 489 490 #define REG_G3_COLOR_GREEN_SHIFT 5 491 #define REG_G3_COLOR_GREEN_SIZE 5 492 #define REG_G3_COLOR_GREEN_MASK 0x000003e0 493 494 #define REG_G3_COLOR_RED_SHIFT 0 495 #define REG_G3_COLOR_RED_SIZE 5 496 #define REG_G3_COLOR_RED_MASK 0x0000001f 497 498 #ifndef SDK_ASM 499 #define REG_G3_COLOR_FIELD( blue, green, red ) \ 500 (u32)( \ 501 ((u32)(blue) << REG_G3_COLOR_BLUE_SHIFT) | \ 502 ((u32)(green) << REG_G3_COLOR_GREEN_SHIFT) | \ 503 ((u32)(red) << REG_G3_COLOR_RED_SHIFT)) 504 #endif 505 506 507 /* NORMAL */ 508 509 #define REG_G3_NORMAL_SZ_SHIFT 29 510 #define REG_G3_NORMAL_SZ_SIZE 1 511 #define REG_G3_NORMAL_SZ_MASK 0x20000000 512 513 #define REG_G3_NORMAL_NZ_SHIFT 20 514 #define REG_G3_NORMAL_NZ_SIZE 9 515 #define REG_G3_NORMAL_NZ_MASK 0x1ff00000 516 517 #define REG_G3_NORMAL_SY_SHIFT 19 518 #define REG_G3_NORMAL_SY_SIZE 1 519 #define REG_G3_NORMAL_SY_MASK 0x00080000 520 521 #define REG_G3_NORMAL_NY_SHIFT 10 522 #define REG_G3_NORMAL_NY_SIZE 9 523 #define REG_G3_NORMAL_NY_MASK 0x0007fc00 524 525 #define REG_G3_NORMAL_SX_SHIFT 9 526 #define REG_G3_NORMAL_SX_SIZE 1 527 #define REG_G3_NORMAL_SX_MASK 0x00000200 528 529 #define REG_G3_NORMAL_NX_SHIFT 0 530 #define REG_G3_NORMAL_NX_SIZE 9 531 #define REG_G3_NORMAL_NX_MASK 0x000001ff 532 533 #ifndef SDK_ASM 534 #define REG_G3_NORMAL_FIELD( sz, nz, sy, ny, sx, nx ) \ 535 (u32)( \ 536 ((u32)(sz) << REG_G3_NORMAL_SZ_SHIFT) | \ 537 ((u32)(nz) << REG_G3_NORMAL_NZ_SHIFT) | \ 538 ((u32)(sy) << REG_G3_NORMAL_SY_SHIFT) | \ 539 ((u32)(ny) << REG_G3_NORMAL_NY_SHIFT) | \ 540 ((u32)(sx) << REG_G3_NORMAL_SX_SHIFT) | \ 541 ((u32)(nx) << REG_G3_NORMAL_NX_SHIFT)) 542 #endif 543 544 545 /* TEXCOORD */ 546 547 #define REG_G3_TEXCOORD_ST_SHIFT 31 548 #define REG_G3_TEXCOORD_ST_SIZE 1 549 #define REG_G3_TEXCOORD_ST_MASK 0x80000000 550 551 #define REG_G3_TEXCOORD_INTEGER_SHIFT 20 552 #define REG_G3_TEXCOORD_INTEGER_SIZE 11 553 #define REG_G3_TEXCOORD_INTEGER_MASK 0x7ff00000 554 555 #define REG_G3_TEXCOORD_DECIMAL_T_SHIFT 16 556 #define REG_G3_TEXCOORD_DECIMAL_T_SIZE 4 557 #define REG_G3_TEXCOORD_DECIMAL_T_MASK 0x000f0000 558 559 #define REG_G3_TEXCOORD_SS_SHIFT 15 560 #define REG_G3_TEXCOORD_SS_SIZE 1 561 #define REG_G3_TEXCOORD_SS_MASK 0x00008000 562 563 #define REG_G3_TEXCOORD_INTEGER_S_SHIFT 4 564 #define REG_G3_TEXCOORD_INTEGER_S_SIZE 11 565 #define REG_G3_TEXCOORD_INTEGER_S_MASK 0x00007ff0 566 567 #define REG_G3_TEXCOORD_DECIMAL_S_SHIFT 0 568 #define REG_G3_TEXCOORD_DECIMAL_S_SIZE 4 569 #define REG_G3_TEXCOORD_DECIMAL_S_MASK 0x0000000f 570 571 #ifndef SDK_ASM 572 #define REG_G3_TEXCOORD_FIELD( st, integer, decimal_t, ss, integer_s, decimal_s ) \ 573 (u32)( \ 574 ((u32)(st) << REG_G3_TEXCOORD_ST_SHIFT) | \ 575 ((u32)(integer) << REG_G3_TEXCOORD_INTEGER_SHIFT) | \ 576 ((u32)(decimal_t) << REG_G3_TEXCOORD_DECIMAL_T_SHIFT) | \ 577 ((u32)(ss) << REG_G3_TEXCOORD_SS_SHIFT) | \ 578 ((u32)(integer_s) << REG_G3_TEXCOORD_INTEGER_S_SHIFT) | \ 579 ((u32)(decimal_s) << REG_G3_TEXCOORD_DECIMAL_S_SHIFT)) 580 #endif 581 582 583 /* VTX_16 */ 584 585 #define REG_G3_VTX_16_SY_SHIFT 31 586 #define REG_G3_VTX_16_SY_SIZE 1 587 #define REG_G3_VTX_16_SY_MASK 0x80000000 588 589 #define REG_G3_VTX_16_INT_Y_SHIFT 28 590 #define REG_G3_VTX_16_INT_Y_SIZE 3 591 #define REG_G3_VTX_16_INT_Y_MASK 0x70000000 592 593 #define REG_G3_VTX_16_DECIMAL_Y_SHIFT 16 594 #define REG_G3_VTX_16_DECIMAL_Y_SIZE 12 595 #define REG_G3_VTX_16_DECIMAL_Y_MASK 0x0fff0000 596 597 #define REG_G3_VTX_16_SX_SHIFT 15 598 #define REG_G3_VTX_16_SX_SIZE 1 599 #define REG_G3_VTX_16_SX_MASK 0x00008000 600 601 #define REG_G3_VTX_16_INT_X_SHIFT 12 602 #define REG_G3_VTX_16_INT_X_SIZE 3 603 #define REG_G3_VTX_16_INT_X_MASK 0x00007000 604 605 #define REG_G3_VTX_16_DECIMAL_X_SHIFT 0 606 #define REG_G3_VTX_16_DECIMAL_X_SIZE 12 607 #define REG_G3_VTX_16_DECIMAL_X_MASK 0x00000fff 608 609 #ifndef SDK_ASM 610 #define REG_G3_VTX_16_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ 611 (u32)( \ 612 ((u32)(sy) << REG_G3_VTX_16_SY_SHIFT) | \ 613 ((u32)(int_y) << REG_G3_VTX_16_INT_Y_SHIFT) | \ 614 ((u32)(decimal_y) << REG_G3_VTX_16_DECIMAL_Y_SHIFT) | \ 615 ((u32)(sx) << REG_G3_VTX_16_SX_SHIFT) | \ 616 ((u32)(int_x) << REG_G3_VTX_16_INT_X_SHIFT) | \ 617 ((u32)(decimal_x) << REG_G3_VTX_16_DECIMAL_X_SHIFT)) 618 #endif 619 620 621 /* VTX_10 */ 622 623 #define REG_G3_VTX_10_SZ_SHIFT 29 624 #define REG_G3_VTX_10_SZ_SIZE 1 625 #define REG_G3_VTX_10_SZ_MASK 0x20000000 626 627 #define REG_G3_VTX_10_INT_Z_SHIFT 26 628 #define REG_G3_VTX_10_INT_Z_SIZE 3 629 #define REG_G3_VTX_10_INT_Z_MASK 0x1c000000 630 631 #define REG_G3_VTX_10_DECIMAL_Z_SHIFT 20 632 #define REG_G3_VTX_10_DECIMAL_Z_SIZE 6 633 #define REG_G3_VTX_10_DECIMAL_Z_MASK 0x03f00000 634 635 #define REG_G3_VTX_10_SY_SHIFT 19 636 #define REG_G3_VTX_10_SY_SIZE 1 637 #define REG_G3_VTX_10_SY_MASK 0x00080000 638 639 #define REG_G3_VTX_10_INT_Y_SHIFT 16 640 #define REG_G3_VTX_10_INT_Y_SIZE 3 641 #define REG_G3_VTX_10_INT_Y_MASK 0x00070000 642 643 #define REG_G3_VTX_10_DECIMAL_Y_SHIFT 10 644 #define REG_G3_VTX_10_DECIMAL_Y_SIZE 6 645 #define REG_G3_VTX_10_DECIMAL_Y_MASK 0x0000fc00 646 647 #define REG_G3_VTX_10_SX_SHIFT 9 648 #define REG_G3_VTX_10_SX_SIZE 1 649 #define REG_G3_VTX_10_SX_MASK 0x00000200 650 651 #define REG_G3_VTX_10_INT_X_SHIFT 6 652 #define REG_G3_VTX_10_INT_X_SIZE 3 653 #define REG_G3_VTX_10_INT_X_MASK 0x000001c0 654 655 #define REG_G3_VTX_10_DECIMAL_X_SHIFT 0 656 #define REG_G3_VTX_10_DECIMAL_X_SIZE 6 657 #define REG_G3_VTX_10_DECIMAL_X_MASK 0x0000003f 658 659 #ifndef SDK_ASM 660 #define REG_G3_VTX_10_FIELD( sz, int_z, decimal_z, sy, int_y, decimal_y, sx, int_x, decimal_x ) \ 661 (u32)( \ 662 ((u32)(sz) << REG_G3_VTX_10_SZ_SHIFT) | \ 663 ((u32)(int_z) << REG_G3_VTX_10_INT_Z_SHIFT) | \ 664 ((u32)(decimal_z) << REG_G3_VTX_10_DECIMAL_Z_SHIFT) | \ 665 ((u32)(sy) << REG_G3_VTX_10_SY_SHIFT) | \ 666 ((u32)(int_y) << REG_G3_VTX_10_INT_Y_SHIFT) | \ 667 ((u32)(decimal_y) << REG_G3_VTX_10_DECIMAL_Y_SHIFT) | \ 668 ((u32)(sx) << REG_G3_VTX_10_SX_SHIFT) | \ 669 ((u32)(int_x) << REG_G3_VTX_10_INT_X_SHIFT) | \ 670 ((u32)(decimal_x) << REG_G3_VTX_10_DECIMAL_X_SHIFT)) 671 #endif 672 673 674 /* VTX_XY */ 675 676 #define REG_G3_VTX_XY_SY_SHIFT 31 677 #define REG_G3_VTX_XY_SY_SIZE 1 678 #define REG_G3_VTX_XY_SY_MASK 0x80000000 679 680 #define REG_G3_VTX_XY_INT_Y_SHIFT 28 681 #define REG_G3_VTX_XY_INT_Y_SIZE 3 682 #define REG_G3_VTX_XY_INT_Y_MASK 0x70000000 683 684 #define REG_G3_VTX_XY_DECIMAL_Y_SHIFT 16 685 #define REG_G3_VTX_XY_DECIMAL_Y_SIZE 12 686 #define REG_G3_VTX_XY_DECIMAL_Y_MASK 0x0fff0000 687 688 #define REG_G3_VTX_XY_SX_SHIFT 15 689 #define REG_G3_VTX_XY_SX_SIZE 1 690 #define REG_G3_VTX_XY_SX_MASK 0x00008000 691 692 #define REG_G3_VTX_XY_INT_X_SHIFT 12 693 #define REG_G3_VTX_XY_INT_X_SIZE 3 694 #define REG_G3_VTX_XY_INT_X_MASK 0x00007000 695 696 #define REG_G3_VTX_XY_DECIMAL_X_SHIFT 0 697 #define REG_G3_VTX_XY_DECIMAL_X_SIZE 12 698 #define REG_G3_VTX_XY_DECIMAL_X_MASK 0x00000fff 699 700 #ifndef SDK_ASM 701 #define REG_G3_VTX_XY_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ 702 (u32)( \ 703 ((u32)(sy) << REG_G3_VTX_XY_SY_SHIFT) | \ 704 ((u32)(int_y) << REG_G3_VTX_XY_INT_Y_SHIFT) | \ 705 ((u32)(decimal_y) << REG_G3_VTX_XY_DECIMAL_Y_SHIFT) | \ 706 ((u32)(sx) << REG_G3_VTX_XY_SX_SHIFT) | \ 707 ((u32)(int_x) << REG_G3_VTX_XY_INT_X_SHIFT) | \ 708 ((u32)(decimal_x) << REG_G3_VTX_XY_DECIMAL_X_SHIFT)) 709 #endif 710 711 712 /* VTX_XZ */ 713 714 #define REG_G3_VTX_XZ_SZ_SHIFT 31 715 #define REG_G3_VTX_XZ_SZ_SIZE 1 716 #define REG_G3_VTX_XZ_SZ_MASK 0x80000000 717 718 #define REG_G3_VTX_XZ_INT_Z_SHIFT 28 719 #define REG_G3_VTX_XZ_INT_Z_SIZE 3 720 #define REG_G3_VTX_XZ_INT_Z_MASK 0x70000000 721 722 #define REG_G3_VTX_XZ_DECIMAL_Z_SHIFT 16 723 #define REG_G3_VTX_XZ_DECIMAL_Z_SIZE 12 724 #define REG_G3_VTX_XZ_DECIMAL_Z_MASK 0x0fff0000 725 726 #define REG_G3_VTX_XZ_SX_SHIFT 15 727 #define REG_G3_VTX_XZ_SX_SIZE 1 728 #define REG_G3_VTX_XZ_SX_MASK 0x00008000 729 730 #define REG_G3_VTX_XZ_INT_X_SHIFT 12 731 #define REG_G3_VTX_XZ_INT_X_SIZE 3 732 #define REG_G3_VTX_XZ_INT_X_MASK 0x00007000 733 734 #define REG_G3_VTX_XZ_DECIMAL_X_SHIFT 0 735 #define REG_G3_VTX_XZ_DECIMAL_X_SIZE 12 736 #define REG_G3_VTX_XZ_DECIMAL_X_MASK 0x00000fff 737 738 #ifndef SDK_ASM 739 #define REG_G3_VTX_XZ_FIELD( sz, int_z, decimal_z, sx, int_x, decimal_x ) \ 740 (u32)( \ 741 ((u32)(sz) << REG_G3_VTX_XZ_SZ_SHIFT) | \ 742 ((u32)(int_z) << REG_G3_VTX_XZ_INT_Z_SHIFT) | \ 743 ((u32)(decimal_z) << REG_G3_VTX_XZ_DECIMAL_Z_SHIFT) | \ 744 ((u32)(sx) << REG_G3_VTX_XZ_SX_SHIFT) | \ 745 ((u32)(int_x) << REG_G3_VTX_XZ_INT_X_SHIFT) | \ 746 ((u32)(decimal_x) << REG_G3_VTX_XZ_DECIMAL_X_SHIFT)) 747 #endif 748 749 750 /* VTX_YZ */ 751 752 #define REG_G3_VTX_YZ_SZ_SHIFT 31 753 #define REG_G3_VTX_YZ_SZ_SIZE 1 754 #define REG_G3_VTX_YZ_SZ_MASK 0x80000000 755 756 #define REG_G3_VTX_YZ_INT_Z_SHIFT 28 757 #define REG_G3_VTX_YZ_INT_Z_SIZE 3 758 #define REG_G3_VTX_YZ_INT_Z_MASK 0x70000000 759 760 #define REG_G3_VTX_YZ_DECIMAL_Z_SHIFT 16 761 #define REG_G3_VTX_YZ_DECIMAL_Z_SIZE 12 762 #define REG_G3_VTX_YZ_DECIMAL_Z_MASK 0x0fff0000 763 764 #define REG_G3_VTX_YZ_SY_SHIFT 15 765 #define REG_G3_VTX_YZ_SY_SIZE 1 766 #define REG_G3_VTX_YZ_SY_MASK 0x00008000 767 768 #define REG_G3_VTX_YZ_INT_Y_SHIFT 12 769 #define REG_G3_VTX_YZ_INT_Y_SIZE 3 770 #define REG_G3_VTX_YZ_INT_Y_MASK 0x00007000 771 772 #define REG_G3_VTX_YZ_DECIMAL_Y_SHIFT 0 773 #define REG_G3_VTX_YZ_DECIMAL_Y_SIZE 12 774 #define REG_G3_VTX_YZ_DECIMAL_Y_MASK 0x00000fff 775 776 #ifndef SDK_ASM 777 #define REG_G3_VTX_YZ_FIELD( sz, int_z, decimal_z, sy, int_y, decimal_y ) \ 778 (u32)( \ 779 ((u32)(sz) << REG_G3_VTX_YZ_SZ_SHIFT) | \ 780 ((u32)(int_z) << REG_G3_VTX_YZ_INT_Z_SHIFT) | \ 781 ((u32)(decimal_z) << REG_G3_VTX_YZ_DECIMAL_Z_SHIFT) | \ 782 ((u32)(sy) << REG_G3_VTX_YZ_SY_SHIFT) | \ 783 ((u32)(int_y) << REG_G3_VTX_YZ_INT_Y_SHIFT) | \ 784 ((u32)(decimal_y) << REG_G3_VTX_YZ_DECIMAL_Y_SHIFT)) 785 #endif 786 787 788 /* VTX_DIFF */ 789 790 #define REG_G3_VTX_DIFF_SZ_SHIFT 29 791 #define REG_G3_VTX_DIFF_SZ_SIZE 1 792 #define REG_G3_VTX_DIFF_SZ_MASK 0x20000000 793 794 #define REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT 20 795 #define REG_G3_VTX_DIFF_DECIMAL_Z_SIZE 9 796 #define REG_G3_VTX_DIFF_DECIMAL_Z_MASK 0x1ff00000 797 798 #define REG_G3_VTX_DIFF_SY_SHIFT 19 799 #define REG_G3_VTX_DIFF_SY_SIZE 1 800 #define REG_G3_VTX_DIFF_SY_MASK 0x00080000 801 802 #define REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT 10 803 #define REG_G3_VTX_DIFF_DECIMAL_Y_SIZE 9 804 #define REG_G3_VTX_DIFF_DECIMAL_Y_MASK 0x0007fc00 805 806 #define REG_G3_VTX_DIFF_SX_SHIFT 9 807 #define REG_G3_VTX_DIFF_SX_SIZE 1 808 #define REG_G3_VTX_DIFF_SX_MASK 0x00000200 809 810 #define REG_G3_VTX_DIFF_DECIMAL_X_SHIFT 0 811 #define REG_G3_VTX_DIFF_DECIMAL_X_SIZE 9 812 #define REG_G3_VTX_DIFF_DECIMAL_X_MASK 0x000001ff 813 814 #ifndef SDK_ASM 815 #define REG_G3_VTX_DIFF_FIELD( sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ 816 (u32)( \ 817 ((u32)(sz) << REG_G3_VTX_DIFF_SZ_SHIFT) | \ 818 ((u32)(decimal_z) << REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT) | \ 819 ((u32)(sy) << REG_G3_VTX_DIFF_SY_SHIFT) | \ 820 ((u32)(decimal_y) << REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT) | \ 821 ((u32)(sx) << REG_G3_VTX_DIFF_SX_SHIFT) | \ 822 ((u32)(decimal_x) << REG_G3_VTX_DIFF_DECIMAL_X_SHIFT)) 823 #endif 824 825 826 /* POLYGON_ATTR */ 827 828 #define REG_G3_POLYGON_ATTR_ID_SHIFT 24 829 #define REG_G3_POLYGON_ATTR_ID_SIZE 6 830 #define REG_G3_POLYGON_ATTR_ID_MASK 0x3f000000 831 832 #define REG_G3_POLYGON_ATTR_ALPHA_SHIFT 16 833 #define REG_G3_POLYGON_ATTR_ALPHA_SIZE 5 834 #define REG_G3_POLYGON_ATTR_ALPHA_MASK 0x001f0000 835 836 #define REG_G3_POLYGON_ATTR_FE_SHIFT 15 837 #define REG_G3_POLYGON_ATTR_FE_SIZE 1 838 #define REG_G3_POLYGON_ATTR_FE_MASK 0x00008000 839 840 #define REG_G3_POLYGON_ATTR_DT_SHIFT 14 841 #define REG_G3_POLYGON_ATTR_DT_SIZE 1 842 #define REG_G3_POLYGON_ATTR_DT_MASK 0x00004000 843 844 #define REG_G3_POLYGON_ATTR_D1_SHIFT 13 845 #define REG_G3_POLYGON_ATTR_D1_SIZE 1 846 #define REG_G3_POLYGON_ATTR_D1_MASK 0x00002000 847 848 #define REG_G3_POLYGON_ATTR_FC_SHIFT 12 849 #define REG_G3_POLYGON_ATTR_FC_SIZE 1 850 #define REG_G3_POLYGON_ATTR_FC_MASK 0x00001000 851 852 #define REG_G3_POLYGON_ATTR_XL_SHIFT 11 853 #define REG_G3_POLYGON_ATTR_XL_SIZE 1 854 #define REG_G3_POLYGON_ATTR_XL_MASK 0x00000800 855 856 #define REG_G3_POLYGON_ATTR_FR_SHIFT 7 857 #define REG_G3_POLYGON_ATTR_FR_SIZE 1 858 #define REG_G3_POLYGON_ATTR_FR_MASK 0x00000080 859 860 #define REG_G3_POLYGON_ATTR_BK_SHIFT 6 861 #define REG_G3_POLYGON_ATTR_BK_SIZE 1 862 #define REG_G3_POLYGON_ATTR_BK_MASK 0x00000040 863 864 #define REG_G3_POLYGON_ATTR_PM_SHIFT 4 865 #define REG_G3_POLYGON_ATTR_PM_SIZE 2 866 #define REG_G3_POLYGON_ATTR_PM_MASK 0x00000030 867 868 #define REG_G3_POLYGON_ATTR_LE_SHIFT 0 869 #define REG_G3_POLYGON_ATTR_LE_SIZE 4 870 #define REG_G3_POLYGON_ATTR_LE_MASK 0x0000000f 871 872 #ifndef SDK_ASM 873 #define REG_G3_POLYGON_ATTR_FIELD( id, alpha, fe, dt, d1, fc, xl, fr, bk, pm, le ) \ 874 (u32)( \ 875 ((u32)(id) << REG_G3_POLYGON_ATTR_ID_SHIFT) | \ 876 ((u32)(alpha) << REG_G3_POLYGON_ATTR_ALPHA_SHIFT) | \ 877 ((u32)(fe) << REG_G3_POLYGON_ATTR_FE_SHIFT) | \ 878 ((u32)(dt) << REG_G3_POLYGON_ATTR_DT_SHIFT) | \ 879 ((u32)(d1) << REG_G3_POLYGON_ATTR_D1_SHIFT) | \ 880 ((u32)(fc) << REG_G3_POLYGON_ATTR_FC_SHIFT) | \ 881 ((u32)(xl) << REG_G3_POLYGON_ATTR_XL_SHIFT) | \ 882 ((u32)(fr) << REG_G3_POLYGON_ATTR_FR_SHIFT) | \ 883 ((u32)(bk) << REG_G3_POLYGON_ATTR_BK_SHIFT) | \ 884 ((u32)(pm) << REG_G3_POLYGON_ATTR_PM_SHIFT) | \ 885 ((u32)(le) << REG_G3_POLYGON_ATTR_LE_SHIFT)) 886 #endif 887 888 889 /* TEXIMAGE_PARAM */ 890 891 #define REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT 30 892 #define REG_G3_TEXIMAGE_PARAM_TGEN_SIZE 2 893 #define REG_G3_TEXIMAGE_PARAM_TGEN_MASK 0xc0000000 894 895 #define REG_G3_TEXIMAGE_PARAM_TR_SHIFT 29 896 #define REG_G3_TEXIMAGE_PARAM_TR_SIZE 1 897 #define REG_G3_TEXIMAGE_PARAM_TR_MASK 0x20000000 898 899 #define REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT 26 900 #define REG_G3_TEXIMAGE_PARAM_TEXFMT_SIZE 3 901 #define REG_G3_TEXIMAGE_PARAM_TEXFMT_MASK 0x1c000000 902 903 #define REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT 23 904 #define REG_G3_TEXIMAGE_PARAM_T_SIZE_SIZE 3 905 #define REG_G3_TEXIMAGE_PARAM_T_SIZE_MASK 0x03800000 906 907 #define REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT 20 908 #define REG_G3_TEXIMAGE_PARAM_V_SIZE_SIZE 3 909 #define REG_G3_TEXIMAGE_PARAM_V_SIZE_MASK 0x00700000 910 911 #define REG_G3_TEXIMAGE_PARAM_FT_SHIFT 19 912 #define REG_G3_TEXIMAGE_PARAM_FT_SIZE 1 913 #define REG_G3_TEXIMAGE_PARAM_FT_MASK 0x00080000 914 915 #define REG_G3_TEXIMAGE_PARAM_FS_SHIFT 18 916 #define REG_G3_TEXIMAGE_PARAM_FS_SIZE 1 917 #define REG_G3_TEXIMAGE_PARAM_FS_MASK 0x00040000 918 919 #define REG_G3_TEXIMAGE_PARAM_RT_SHIFT 17 920 #define REG_G3_TEXIMAGE_PARAM_RT_SIZE 1 921 #define REG_G3_TEXIMAGE_PARAM_RT_MASK 0x00020000 922 923 #define REG_G3_TEXIMAGE_PARAM_RS_SHIFT 16 924 #define REG_G3_TEXIMAGE_PARAM_RS_SIZE 1 925 #define REG_G3_TEXIMAGE_PARAM_RS_MASK 0x00010000 926 927 #define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT 0 928 #define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SIZE 16 929 #define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_MASK 0x0000ffff 930 931 #ifndef SDK_ASM 932 #define REG_G3_TEXIMAGE_PARAM_FIELD( tgen, tr, texfmt, t_size, v_size, ft, fs, rt, rs, tex_addr ) \ 933 (u32)( \ 934 ((u32)(tgen) << REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT) | \ 935 ((u32)(tr) << REG_G3_TEXIMAGE_PARAM_TR_SHIFT) | \ 936 ((u32)(texfmt) << REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT) | \ 937 ((u32)(t_size) << REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT) | \ 938 ((u32)(v_size) << REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT) | \ 939 ((u32)(ft) << REG_G3_TEXIMAGE_PARAM_FT_SHIFT) | \ 940 ((u32)(fs) << REG_G3_TEXIMAGE_PARAM_FS_SHIFT) | \ 941 ((u32)(rt) << REG_G3_TEXIMAGE_PARAM_RT_SHIFT) | \ 942 ((u32)(rs) << REG_G3_TEXIMAGE_PARAM_RS_SHIFT) | \ 943 ((u32)(tex_addr) << REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT)) 944 #endif 945 946 947 /* TEXPLTT_BASE */ 948 949 #define REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT 0 950 #define REG_G3_TEXPLTT_BASE_PLTT_BASE_SIZE 13 951 #define REG_G3_TEXPLTT_BASE_PLTT_BASE_MASK 0x00001fff 952 953 #ifndef SDK_ASM 954 #define REG_G3_TEXPLTT_BASE_FIELD( pltt_base ) \ 955 (u32)( \ 956 ((u32)(pltt_base) << REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT)) 957 #endif 958 959 960 /* DIF_AMB */ 961 962 #define REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT 26 963 #define REG_G3_DIF_AMB_AMBIENT_BLUE_SIZE 5 964 #define REG_G3_DIF_AMB_AMBIENT_BLUE_MASK 0x7c000000 965 966 #define REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT 21 967 #define REG_G3_DIF_AMB_AMBIENT_GREEN_SIZE 5 968 #define REG_G3_DIF_AMB_AMBIENT_GREEN_MASK 0x03e00000 969 970 #define REG_G3_DIF_AMB_AMBIENT_RED_SHIFT 16 971 #define REG_G3_DIF_AMB_AMBIENT_RED_SIZE 5 972 #define REG_G3_DIF_AMB_AMBIENT_RED_MASK 0x001f0000 973 974 #define REG_G3_DIF_AMB_C_SHIFT 15 975 #define REG_G3_DIF_AMB_C_SIZE 1 976 #define REG_G3_DIF_AMB_C_MASK 0x00008000 977 978 #define REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT 10 979 #define REG_G3_DIF_AMB_DIFFUSE_BLUE_SIZE 5 980 #define REG_G3_DIF_AMB_DIFFUSE_BLUE_MASK 0x00007c00 981 982 #define REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT 5 983 #define REG_G3_DIF_AMB_DIFFUSE_GREEN_SIZE 5 984 #define REG_G3_DIF_AMB_DIFFUSE_GREEN_MASK 0x000003e0 985 986 #define REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT 0 987 #define REG_G3_DIF_AMB_DIFFUSE_RED_SIZE 5 988 #define REG_G3_DIF_AMB_DIFFUSE_RED_MASK 0x0000001f 989 990 #ifndef SDK_ASM 991 #define REG_G3_DIF_AMB_FIELD( ambient_blue, ambient_green, ambient_red, c, diffuse_blue, diffuse_green, diffuse_red ) \ 992 (u32)( \ 993 ((u32)(ambient_blue) << REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT) | \ 994 ((u32)(ambient_green) << REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT) | \ 995 ((u32)(ambient_red) << REG_G3_DIF_AMB_AMBIENT_RED_SHIFT) | \ 996 ((u32)(c) << REG_G3_DIF_AMB_C_SHIFT) | \ 997 ((u32)(diffuse_blue) << REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT) | \ 998 ((u32)(diffuse_green) << REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT) | \ 999 ((u32)(diffuse_red) << REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT)) 1000 #endif 1001 1002 1003 /* SPE_EMI */ 1004 1005 #define REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT 26 1006 #define REG_G3_SPE_EMI_EMISSION_BLUE_SIZE 5 1007 #define REG_G3_SPE_EMI_EMISSION_BLUE_MASK 0x7c000000 1008 1009 #define REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT 21 1010 #define REG_G3_SPE_EMI_EMISSION_GREEN_SIZE 5 1011 #define REG_G3_SPE_EMI_EMISSION_GREEN_MASK 0x03e00000 1012 1013 #define REG_G3_SPE_EMI_EMISSION_RED_SHIFT 16 1014 #define REG_G3_SPE_EMI_EMISSION_RED_SIZE 5 1015 #define REG_G3_SPE_EMI_EMISSION_RED_MASK 0x001f0000 1016 1017 #define REG_G3_SPE_EMI_S_SHIFT 15 1018 #define REG_G3_SPE_EMI_S_SIZE 1 1019 #define REG_G3_SPE_EMI_S_MASK 0x00008000 1020 1021 #define REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT 10 1022 #define REG_G3_SPE_EMI_SPECULAR_BLUE_SIZE 5 1023 #define REG_G3_SPE_EMI_SPECULAR_BLUE_MASK 0x00007c00 1024 1025 #define REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT 5 1026 #define REG_G3_SPE_EMI_SPECULAR_GREEN_SIZE 5 1027 #define REG_G3_SPE_EMI_SPECULAR_GREEN_MASK 0x000003e0 1028 1029 #define REG_G3_SPE_EMI_SPECULAR_RED_SHIFT 0 1030 #define REG_G3_SPE_EMI_SPECULAR_RED_SIZE 5 1031 #define REG_G3_SPE_EMI_SPECULAR_RED_MASK 0x0000001f 1032 1033 #ifndef SDK_ASM 1034 #define REG_G3_SPE_EMI_FIELD( emission_blue, emission_green, emission_red, s, specular_blue, specular_green, specular_red ) \ 1035 (u32)( \ 1036 ((u32)(emission_blue) << REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT) | \ 1037 ((u32)(emission_green) << REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT) | \ 1038 ((u32)(emission_red) << REG_G3_SPE_EMI_EMISSION_RED_SHIFT) | \ 1039 ((u32)(s) << REG_G3_SPE_EMI_S_SHIFT) | \ 1040 ((u32)(specular_blue) << REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT) | \ 1041 ((u32)(specular_green) << REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT) | \ 1042 ((u32)(specular_red) << REG_G3_SPE_EMI_SPECULAR_RED_SHIFT)) 1043 #endif 1044 1045 1046 /* LIGHT_VECTOR */ 1047 1048 #define REG_G3_LIGHT_VECTOR_LNUM_SHIFT 30 1049 #define REG_G3_LIGHT_VECTOR_LNUM_SIZE 2 1050 #define REG_G3_LIGHT_VECTOR_LNUM_MASK 0xc0000000 1051 1052 #define REG_G3_LIGHT_VECTOR_SZ_SHIFT 29 1053 #define REG_G3_LIGHT_VECTOR_SZ_SIZE 1 1054 #define REG_G3_LIGHT_VECTOR_SZ_MASK 0x20000000 1055 1056 #define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT 20 1057 #define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SIZE 9 1058 #define REG_G3_LIGHT_VECTOR_DECIMAL_Z_MASK 0x1ff00000 1059 1060 #define REG_G3_LIGHT_VECTOR_SY_SHIFT 19 1061 #define REG_G3_LIGHT_VECTOR_SY_SIZE 1 1062 #define REG_G3_LIGHT_VECTOR_SY_MASK 0x00080000 1063 1064 #define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT 10 1065 #define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SIZE 9 1066 #define REG_G3_LIGHT_VECTOR_DECIMAL_Y_MASK 0x0007fc00 1067 1068 #define REG_G3_LIGHT_VECTOR_SX_SHIFT 9 1069 #define REG_G3_LIGHT_VECTOR_SX_SIZE 1 1070 #define REG_G3_LIGHT_VECTOR_SX_MASK 0x00000200 1071 1072 #define REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT 0 1073 #define REG_G3_LIGHT_VECTOR_DECIMAL_X_SIZE 9 1074 #define REG_G3_LIGHT_VECTOR_DECIMAL_X_MASK 0x000001ff 1075 1076 #ifndef SDK_ASM 1077 #define REG_G3_LIGHT_VECTOR_FIELD( lnum, sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ 1078 (u32)( \ 1079 ((u32)(lnum) << REG_G3_LIGHT_VECTOR_LNUM_SHIFT) | \ 1080 ((u32)(sz) << REG_G3_LIGHT_VECTOR_SZ_SHIFT) | \ 1081 ((u32)(decimal_z) << REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT) | \ 1082 ((u32)(sy) << REG_G3_LIGHT_VECTOR_SY_SHIFT) | \ 1083 ((u32)(decimal_y) << REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT) | \ 1084 ((u32)(sx) << REG_G3_LIGHT_VECTOR_SX_SHIFT) | \ 1085 ((u32)(decimal_x) << REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT)) 1086 #endif 1087 1088 1089 /* LIGHT_COLOR */ 1090 1091 #define REG_G3_LIGHT_COLOR_LNUM_SHIFT 30 1092 #define REG_G3_LIGHT_COLOR_LNUM_SIZE 2 1093 #define REG_G3_LIGHT_COLOR_LNUM_MASK 0xc0000000 1094 1095 #define REG_G3_LIGHT_COLOR_BLUE_SHIFT 10 1096 #define REG_G3_LIGHT_COLOR_BLUE_SIZE 5 1097 #define REG_G3_LIGHT_COLOR_BLUE_MASK 0x00007c00 1098 1099 #define REG_G3_LIGHT_COLOR_GREEN_SHIFT 5 1100 #define REG_G3_LIGHT_COLOR_GREEN_SIZE 5 1101 #define REG_G3_LIGHT_COLOR_GREEN_MASK 0x000003e0 1102 1103 #define REG_G3_LIGHT_COLOR_RED_SHIFT 0 1104 #define REG_G3_LIGHT_COLOR_RED_SIZE 5 1105 #define REG_G3_LIGHT_COLOR_RED_MASK 0x0000001f 1106 1107 #ifndef SDK_ASM 1108 #define REG_G3_LIGHT_COLOR_FIELD( lnum, blue, green, red ) \ 1109 (u32)( \ 1110 ((u32)(lnum) << REG_G3_LIGHT_COLOR_LNUM_SHIFT) | \ 1111 ((u32)(blue) << REG_G3_LIGHT_COLOR_BLUE_SHIFT) | \ 1112 ((u32)(green) << REG_G3_LIGHT_COLOR_GREEN_SHIFT) | \ 1113 ((u32)(red) << REG_G3_LIGHT_COLOR_RED_SHIFT)) 1114 #endif 1115 1116 1117 /* SHININESS */ 1118 1119 #define REG_G3_SHININESS_SHININESS3_SHIFT 24 1120 #define REG_G3_SHININESS_SHININESS3_SIZE 8 1121 #define REG_G3_SHININESS_SHININESS3_MASK 0xff000000 1122 1123 #define REG_G3_SHININESS_SHININESS2_SHIFT 16 1124 #define REG_G3_SHININESS_SHININESS2_SIZE 8 1125 #define REG_G3_SHININESS_SHININESS2_MASK 0x00ff0000 1126 1127 #define REG_G3_SHININESS_SHININESS1_SHIFT 8 1128 #define REG_G3_SHININESS_SHININESS1_SIZE 8 1129 #define REG_G3_SHININESS_SHININESS1_MASK 0x0000ff00 1130 1131 #define REG_G3_SHININESS_SHININESS0_SHIFT 0 1132 #define REG_G3_SHININESS_SHININESS0_SIZE 8 1133 #define REG_G3_SHININESS_SHININESS0_MASK 0x000000ff 1134 1135 #ifndef SDK_ASM 1136 #define REG_G3_SHININESS_FIELD( shininess3, shininess2, shininess1, shininess0 ) \ 1137 (u32)( \ 1138 ((u32)(shininess3) << REG_G3_SHININESS_SHININESS3_SHIFT) | \ 1139 ((u32)(shininess2) << REG_G3_SHININESS_SHININESS2_SHIFT) | \ 1140 ((u32)(shininess1) << REG_G3_SHININESS_SHININESS1_SHIFT) | \ 1141 ((u32)(shininess0) << REG_G3_SHININESS_SHININESS0_SHIFT)) 1142 #endif 1143 1144 1145 /* BEGIN_VTXS */ 1146 1147 #define REG_G3_BEGIN_VTXS_TYPE_SHIFT 0 1148 #define REG_G3_BEGIN_VTXS_TYPE_SIZE 2 1149 #define REG_G3_BEGIN_VTXS_TYPE_MASK 0x00000003 1150 1151 #ifndef SDK_ASM 1152 #define REG_G3_BEGIN_VTXS_FIELD( type ) \ 1153 (u32)( \ 1154 ((u32)(type) << REG_G3_BEGIN_VTXS_TYPE_SHIFT)) 1155 #endif 1156 1157 1158 /* END_VTXS */ 1159 1160 /* SWAP_BUFFERS */ 1161 1162 #define REG_G3_SWAP_BUFFERS_DP_SHIFT 1 1163 #define REG_G3_SWAP_BUFFERS_DP_SIZE 1 1164 #define REG_G3_SWAP_BUFFERS_DP_MASK 0x00000002 1165 1166 #define REG_G3_SWAP_BUFFERS_XS_SHIFT 0 1167 #define REG_G3_SWAP_BUFFERS_XS_SIZE 1 1168 #define REG_G3_SWAP_BUFFERS_XS_MASK 0x00000001 1169 1170 #ifndef SDK_ASM 1171 #define REG_G3_SWAP_BUFFERS_FIELD( dp, xs ) \ 1172 (u32)( \ 1173 ((u32)(dp) << REG_G3_SWAP_BUFFERS_DP_SHIFT) | \ 1174 ((u32)(xs) << REG_G3_SWAP_BUFFERS_XS_SHIFT)) 1175 #endif 1176 1177 1178 /* VIEWPORT */ 1179 1180 #define REG_G3_VIEWPORT_INTEGER_Y2_SHIFT 24 1181 #define REG_G3_VIEWPORT_INTEGER_Y2_SIZE 8 1182 #define REG_G3_VIEWPORT_INTEGER_Y2_MASK 0xff000000 1183 1184 #define REG_G3_VIEWPORT_INTEGER_X2_SHIFT 16 1185 #define REG_G3_VIEWPORT_INTEGER_X2_SIZE 8 1186 #define REG_G3_VIEWPORT_INTEGER_X2_MASK 0x00ff0000 1187 1188 #define REG_G3_VIEWPORT_INTEGER_Y1_SHIFT 8 1189 #define REG_G3_VIEWPORT_INTEGER_Y1_SIZE 8 1190 #define REG_G3_VIEWPORT_INTEGER_Y1_MASK 0x0000ff00 1191 1192 #define REG_G3_VIEWPORT_INTEGER_X1_SHIFT 0 1193 #define REG_G3_VIEWPORT_INTEGER_X1_SIZE 8 1194 #define REG_G3_VIEWPORT_INTEGER_X1_MASK 0x000000ff 1195 1196 #ifndef SDK_ASM 1197 #define REG_G3_VIEWPORT_FIELD( integer_y2, integer_x2, integer_y1, integer_x1 ) \ 1198 (u32)( \ 1199 ((u32)(integer_y2) << REG_G3_VIEWPORT_INTEGER_Y2_SHIFT) | \ 1200 ((u32)(integer_x2) << REG_G3_VIEWPORT_INTEGER_X2_SHIFT) | \ 1201 ((u32)(integer_y1) << REG_G3_VIEWPORT_INTEGER_Y1_SHIFT) | \ 1202 ((u32)(integer_x1) << REG_G3_VIEWPORT_INTEGER_X1_SHIFT)) 1203 #endif 1204 1205 1206 /* BOX_TEST */ 1207 1208 #define REG_G3_BOX_TEST_SY_SHIFT 31 1209 #define REG_G3_BOX_TEST_SY_SIZE 1 1210 #define REG_G3_BOX_TEST_SY_MASK 0x80000000 1211 1212 #define REG_G3_BOX_TEST_INT_Y_SHIFT 28 1213 #define REG_G3_BOX_TEST_INT_Y_SIZE 3 1214 #define REG_G3_BOX_TEST_INT_Y_MASK 0x70000000 1215 1216 #define REG_G3_BOX_TEST_DECIMAL_Y_SHIFT 16 1217 #define REG_G3_BOX_TEST_DECIMAL_Y_SIZE 12 1218 #define REG_G3_BOX_TEST_DECIMAL_Y_MASK 0x0fff0000 1219 1220 #define REG_G3_BOX_TEST_SX_SHIFT 15 1221 #define REG_G3_BOX_TEST_SX_SIZE 1 1222 #define REG_G3_BOX_TEST_SX_MASK 0x00008000 1223 1224 #define REG_G3_BOX_TEST_INT_X_SHIFT 12 1225 #define REG_G3_BOX_TEST_INT_X_SIZE 3 1226 #define REG_G3_BOX_TEST_INT_X_MASK 0x00007000 1227 1228 #define REG_G3_BOX_TEST_DECIMAL_X_SHIFT 0 1229 #define REG_G3_BOX_TEST_DECIMAL_X_SIZE 12 1230 #define REG_G3_BOX_TEST_DECIMAL_X_MASK 0x00000fff 1231 1232 #ifndef SDK_ASM 1233 #define REG_G3_BOX_TEST_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ 1234 (u32)( \ 1235 ((u32)(sy) << REG_G3_BOX_TEST_SY_SHIFT) | \ 1236 ((u32)(int_y) << REG_G3_BOX_TEST_INT_Y_SHIFT) | \ 1237 ((u32)(decimal_y) << REG_G3_BOX_TEST_DECIMAL_Y_SHIFT) | \ 1238 ((u32)(sx) << REG_G3_BOX_TEST_SX_SHIFT) | \ 1239 ((u32)(int_x) << REG_G3_BOX_TEST_INT_X_SHIFT) | \ 1240 ((u32)(decimal_x) << REG_G3_BOX_TEST_DECIMAL_X_SHIFT)) 1241 #endif 1242 1243 1244 /* POS_TEST */ 1245 1246 #define REG_G3_POS_TEST_SY_SHIFT 31 1247 #define REG_G3_POS_TEST_SY_SIZE 1 1248 #define REG_G3_POS_TEST_SY_MASK 0x80000000 1249 1250 #define REG_G3_POS_TEST_INT_Y_SHIFT 28 1251 #define REG_G3_POS_TEST_INT_Y_SIZE 3 1252 #define REG_G3_POS_TEST_INT_Y_MASK 0x70000000 1253 1254 #define REG_G3_POS_TEST_DECIMAL_Y_SHIFT 16 1255 #define REG_G3_POS_TEST_DECIMAL_Y_SIZE 12 1256 #define REG_G3_POS_TEST_DECIMAL_Y_MASK 0x0fff0000 1257 1258 #define REG_G3_POS_TEST_SX_SHIFT 15 1259 #define REG_G3_POS_TEST_SX_SIZE 1 1260 #define REG_G3_POS_TEST_SX_MASK 0x00008000 1261 1262 #define REG_G3_POS_TEST_INT_X_SHIFT 12 1263 #define REG_G3_POS_TEST_INT_X_SIZE 3 1264 #define REG_G3_POS_TEST_INT_X_MASK 0x00007000 1265 1266 #define REG_G3_POS_TEST_DECIMAL_X_SHIFT 0 1267 #define REG_G3_POS_TEST_DECIMAL_X_SIZE 12 1268 #define REG_G3_POS_TEST_DECIMAL_X_MASK 0x00000fff 1269 1270 #ifndef SDK_ASM 1271 #define REG_G3_POS_TEST_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ 1272 (u32)( \ 1273 ((u32)(sy) << REG_G3_POS_TEST_SY_SHIFT) | \ 1274 ((u32)(int_y) << REG_G3_POS_TEST_INT_Y_SHIFT) | \ 1275 ((u32)(decimal_y) << REG_G3_POS_TEST_DECIMAL_Y_SHIFT) | \ 1276 ((u32)(sx) << REG_G3_POS_TEST_SX_SHIFT) | \ 1277 ((u32)(int_x) << REG_G3_POS_TEST_INT_X_SHIFT) | \ 1278 ((u32)(decimal_x) << REG_G3_POS_TEST_DECIMAL_X_SHIFT)) 1279 #endif 1280 1281 1282 /* VEC_TEST */ 1283 1284 #define REG_G3_VEC_TEST_SZ_SHIFT 29 1285 #define REG_G3_VEC_TEST_SZ_SIZE 1 1286 #define REG_G3_VEC_TEST_SZ_MASK 0x20000000 1287 1288 #define REG_G3_VEC_TEST_DECIMAL_Z_SHIFT 20 1289 #define REG_G3_VEC_TEST_DECIMAL_Z_SIZE 9 1290 #define REG_G3_VEC_TEST_DECIMAL_Z_MASK 0x1ff00000 1291 1292 #define REG_G3_VEC_TEST_SY_SHIFT 19 1293 #define REG_G3_VEC_TEST_SY_SIZE 1 1294 #define REG_G3_VEC_TEST_SY_MASK 0x00080000 1295 1296 #define REG_G3_VEC_TEST_DECIMAL_Y_SHIFT 10 1297 #define REG_G3_VEC_TEST_DECIMAL_Y_SIZE 9 1298 #define REG_G3_VEC_TEST_DECIMAL_Y_MASK 0x0007fc00 1299 1300 #define REG_G3_VEC_TEST_SX_SHIFT 9 1301 #define REG_G3_VEC_TEST_SX_SIZE 1 1302 #define REG_G3_VEC_TEST_SX_MASK 0x00000200 1303 1304 #define REG_G3_VEC_TEST_DECIMAL_X_SHIFT 0 1305 #define REG_G3_VEC_TEST_DECIMAL_X_SIZE 9 1306 #define REG_G3_VEC_TEST_DECIMAL_X_MASK 0x000001ff 1307 1308 #ifndef SDK_ASM 1309 #define REG_G3_VEC_TEST_FIELD( sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ 1310 (u32)( \ 1311 ((u32)(sz) << REG_G3_VEC_TEST_SZ_SHIFT) | \ 1312 ((u32)(decimal_z) << REG_G3_VEC_TEST_DECIMAL_Z_SHIFT) | \ 1313 ((u32)(sy) << REG_G3_VEC_TEST_SY_SHIFT) | \ 1314 ((u32)(decimal_y) << REG_G3_VEC_TEST_DECIMAL_Y_SHIFT) | \ 1315 ((u32)(sx) << REG_G3_VEC_TEST_SX_SHIFT) | \ 1316 ((u32)(decimal_x) << REG_G3_VEC_TEST_DECIMAL_X_SHIFT)) 1317 #endif 1318 1319 1320 #ifdef __cplusplus 1321 } /* extern "C" */ 1322 #endif 1323 1324 /* NITRO_HW_ARM9_IOREG_G3_H_ */ 1325 #endif 1326