1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: nitro/hw/ARM9/ioreg_EXI.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef NITRO_HW_ARM9_IOREG_EXI_H_ 18 #define NITRO_HW_ARM9_IOREG_EXI_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <nitro/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* SIODATA32 */ 35 36 #define REG_SIODATA32_OFFSET 0x120 37 #define REG_SIODATA32_ADDR (HW_REG_BASE + REG_SIODATA32_OFFSET) 38 #define reg_EXI_SIODATA32 (*( REGType32v *) REG_SIODATA32_ADDR) 39 40 /* SIOCNT */ 41 42 #define REG_SIOCNT_OFFSET 0x128 43 #define REG_SIOCNT_ADDR (HW_REG_BASE + REG_SIOCNT_OFFSET) 44 #define reg_EXI_SIOCNT (*( REGType16v *) REG_SIOCNT_ADDR) 45 46 /* SIOSEL */ 47 48 #define REG_SIOSEL_OFFSET 0x12c 49 #define REG_SIOSEL_ADDR (HW_REG_BASE + REG_SIOSEL_OFFSET) 50 #define reg_EXI_SIOSEL (*( REGType16v *) REG_SIOSEL_ADDR) 51 52 53 /* 54 * Definitions of Register fields 55 */ 56 57 58 /* SIODATA32 */ 59 60 #define REG_EXI_SIODATA32_H_SHIFT 16 61 #define REG_EXI_SIODATA32_H_SIZE 16 62 #define REG_EXI_SIODATA32_H_MASK 0xffff0000 63 64 #define REG_EXI_SIODATA32_L_SHIFT 0 65 #define REG_EXI_SIODATA32_L_SIZE 16 66 #define REG_EXI_SIODATA32_L_MASK 0x0000ffff 67 68 #ifndef SDK_ASM 69 #define REG_EXI_SIODATA32_FIELD( h, l ) \ 70 (u32)( \ 71 ((u32)(h) << REG_EXI_SIODATA32_H_SHIFT) | \ 72 ((u32)(l) << REG_EXI_SIODATA32_L_SHIFT)) 73 #endif 74 75 76 /* SIOCNT */ 77 78 #define REG_EXI_SIOCNT_TSEND_SHIFT 3 79 #define REG_EXI_SIOCNT_TSEND_SIZE 1 80 #define REG_EXI_SIOCNT_TSEND_MASK 0x0008 81 82 #define REG_EXI_SIOCNT_TRECV_SHIFT 2 83 #define REG_EXI_SIOCNT_TRECV_SIZE 1 84 #define REG_EXI_SIOCNT_TRECV_MASK 0x0004 85 86 #ifndef SDK_ASM 87 #define REG_EXI_SIOCNT_FIELD( tsend, trecv ) \ 88 (u16)( \ 89 ((u32)(tsend) << REG_EXI_SIOCNT_TSEND_SHIFT) | \ 90 ((u32)(trecv) << REG_EXI_SIOCNT_TRECV_SHIFT)) 91 #endif 92 93 94 /* SIOSEL */ 95 96 #define REG_EXI_SIOSEL_SEL_SHIFT 0 97 #define REG_EXI_SIOSEL_SEL_SIZE 1 98 #define REG_EXI_SIOSEL_SEL_MASK 0x0001 99 100 #ifndef SDK_ASM 101 #define REG_EXI_SIOSEL_FIELD( sel ) \ 102 (u16)( \ 103 ((u32)(sel) << REG_EXI_SIOSEL_SEL_SHIFT)) 104 #endif 105 106 107 #ifdef __cplusplus 108 } /* extern "C" */ 109 #endif 110 111 /* NITRO_HW_ARM9_IOREG_EXI_H_ */ 112 #endif 113